Re: [Intel-gfx] [PATCH 12/15] drm/i915/guc: Rename client->cookie to match use

On 25/11/2016 09:30, Chris Wilson wrote: The client->cookie is a shadow of the doorbell->cookie value, so rename it to indicate its association with the doorbell, like the doorbell id and offset. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_debugfs.c

Re: [Intel-gfx] [i-g-t PATCH] lib: add option for running generic tests cases only

Op 28-11-16 om 10:37 schreef Abdiel Janulgue: > Pretend to run on a non-intel machine even when running on i915.ko, > so that we could run and gather passrate data. > Signed-off-by: Abdiel Janulgue > --- > lib/drmtest.c | 6 +- > 1 file changed, 5

Re: [Intel-gfx] [PATCH v6 2/8] drm/i915/bxt: IPC WA for Broxton

Hi, Will keep WA number in commit message/WA location. thanks, Regards, -Mahesh On Thursday 24 November 2016 06:21 PM, Lankhorst, Maarten wrote: Mahesh Kumar schreef op do 24-11-2016 om 09:31 [+0530]: If IPC is enabled in BXT, display underruns are observed. WA: The Line Time programmed in

Re: [Intel-gfx] [PATCH] drm/i915: drop the struct_mutex when wedged or trying to reset

On Mon, 28 Nov 2016, Joonas Lahtinen wrote: > On ma, 2016-11-28 at 10:36 +, Matthew Auld wrote: >> We grab the struct_mutex in intel_crtc_page_flip, but if we are wedged >> or a reset is in progress we bail early but never seem to actually >> release the lock.

[Intel-gfx] [PATCH 1/3] drm/i915/debugfs: add dp mst info

From: Libin Yang Add the DP MST info dump in debugfs. Signed-off-by: Libin Yang Signed-off-by: Dhinakaran Pandiyan Reviewed-by: Lyude Signed-off-by: Rodrigo Vivi ---

[Intel-gfx] [PATCH 2/3] drm/i915: abstract ddi being audio enabled

From: Libin Yang Prepare for using the same code for judging ddi being audio enabled. No functional changes. Signed-off-by: Libin Yang Signed-off-by: Dhinakaran Pandiyan Reviewed-by: Lyude

[Intel-gfx] [PATCH 3/3] drm/i915: enable dp mst audio

From: Libin Yang This patch adds support for DP MST audio in i915. Enable audio codec when DP MST is enabled if has_audio flag is set. Disable audio codec when DP MST is disabled if has_audio flag is set. Another separated patches to support DP MST audio will be

Re: [Intel-gfx] [dim PATCH] dim: fix update-branches to fetch all available nightly repos

On 11/28/2016 05:03 PM, Jani Nikula wrote: Update all nightly repos that have a corresponding local remote. Cc: Archit Taneja Signed-off-by: Jani Nikula Tested-by: Archit Taneja --- dim | 9 - 1 file

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [CI,1/5] drm/i915: Rename intel_guc.h to intel_uc.h

== Series Details == Series: series starting with [CI,1/5] drm/i915: Rename intel_guc.h to intel_uc.h URL : https://patchwork.freedesktop.org/series/16034/ State : warning == Summary == Series 16034v1 Series without cover letter

Re: [Intel-gfx] [PATCH v3 2/3] drm/i915/gen9: Fix PCODE polling during CDCLK change notification

On Mon, Nov 28, 2016 at 01:12:57PM +0200, Imre Deak wrote: > commit 848496e5902833600f7992f4faa82dc1546051ba > Author: Ville Syrjälä > Date: Wed Jul 13 16:32:03 2016 +0300 > > drm/i915: Wait up to 3ms for the pcu to ack the cdclk change request on > SKL > >

Re: [Intel-gfx] [PATCH v3 2/3] drm/i915/gen9: Fix PCODE polling during CDCLK change notification

On Mon, Nov 28, 2016 at 03:54:08PM +0200, Imre Deak wrote: > On ma, 2016-11-28 at 15:51 +0200, Ville Syrjälä wrote: > > On Mon, Nov 28, 2016 at 01:12:57PM +0200, Imre Deak wrote: > > > commit 848496e5902833600f7992f4faa82dc1546051ba > > > Author: Ville Syrjälä > > >

[Intel-gfx] [CI 2/5] drm/i915/guc: Drop guc2host/host2guc from names

From: Arkadiusz Hiler To facilitate code reorganization we are renaming everything that contains guc2host or host2guc. host2guc_action() and host2guc_action_response() become guc_send() and guc_recv() respectively. Other host2guc_*() functions become simply guc_*().

[Intel-gfx] [CI 3/5] drm/i915/guc: Move guc_{send, recv}() to intel_uc.c

From: Arkadiusz Hiler guc_send(), guc_recv() and related functions were introduced in the i915_guc_submission.c and their scope was limited only to that file. Those are not submission specific though. This patch moves moves them to intel_uc.c with intel_ prefix added.

[Intel-gfx] [CI 5/5] drm/i915/guc: Remove spurious include

From: Arkadiusz Hiler Cc: Chris Wilson Cc: Michal Winiarski Signed-off-by: Arkadiusz Hiler Reviewed-by: Chris Wilson Link:

[Intel-gfx] [CI 4/5] drm/i915/guc: Init send_mutex in intel_uc_init_early()

From: Arkadiusz Hiler send_mutex is used to serialise communication with GuC via intel_guc_send(). Since functions that utilize it are no longer limited to submission, initialization should be handled as a part of general setup. v2: move initialization to *_early()

[Intel-gfx] [CI 1/5] drm/i915: Rename intel_guc.h to intel_uc.h

From: Arkadiusz Hiler GuC is not the only one micro controller we have. There are also HuC and DMC. Making the file more general will help with code organization. Cc: Chris Wilson Cc: Michal Winiarski

[Intel-gfx] ✓ Fi.CI.BAT: success for GuC code reorganization (rev7)

== Series Details == Series: GuC code reorganization (rev7) URL : https://patchwork.freedesktop.org/series/15896/ State : success == Summary == Series 15896v7 GuC code reorganization https://patchwork.freedesktop.org/api/1.0/series/15896/revisions/7/mbox/ Test kms_pipe_crc_basic:

Re: [Intel-gfx] [alsa-devel] [RFC PATCH v3 1/7] drm/i915: setup bridge for HDMI LPE audio driver

On Sun, Nov 27, 2016 at 12:20:30PM -0600, Pierre-Louis Bossart wrote: > On 11/24/16 7:31 AM, Ville Syrjälä wrote: > >> +static void lpe_audio_irq_unmask(struct irq_data *d) > >> +{ > >> + struct drm_device *dev = d->chip_data; > >> + struct drm_i915_private *dev_priv = to_i915(dev); > >> +

Re: [Intel-gfx] [PATCH 14/15] drm/i915/guc: Keep the execbuf client allocated across reset

On 25/11/2016 09:30, Chris Wilson wrote: In order to avoid some complexity in trying to reconstruct the workqueues across reset, remember them instead. The issue comes when we have to handle a reset between request allocation and submission, the request has reserved space in the wq, but is not

Re: [Intel-gfx] [PATCH 14/15] drm/i915/guc: Keep the execbuf client allocated across reset

On Mon, Nov 28, 2016 at 01:49:03PM +, Tvrtko Ursulin wrote: > > On 25/11/2016 09:30, Chris Wilson wrote: > >In order to avoid some complexity in trying to reconstruct the > >workqueues across reset, remember them instead. The issue comes when we > >have to handle a reset between request

[Intel-gfx] [dim PATCH] dim: fix update-branches to fetch all available nightly repos

Update all nightly repos that have a corresponding local remote. Cc: Archit Taneja Signed-off-by: Jani Nikula --- dim | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/dim b/dim index a709342572ab..3dd2d1dec796 100755 ---

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/3] drm/i915/gen6+: Clear upper data byte during PCODE write

== Series Details == Series: series starting with [v3,1/3] drm/i915/gen6+: Clear upper data byte during PCODE write URL : https://patchwork.freedesktop.org/series/16028/ State : failure == Summary == Series 16028v1 Series without cover letter

Re: [Intel-gfx] [PATCH 13/15] drm/i915/guc: Initialise doorbell cookie to matching value

On 25/11/2016 09:30, Chris Wilson wrote: Set the initial value of the doorbell cookie from the client. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_guc_submission.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [Intel-gfx] [i-g-t PATCH] lib: add option for running generic tests cases only

On Mon, Nov 28, 2016 at 01:07:36PM +0100, Maarten Lankhorst wrote: > Op 28-11-16 om 10:37 schreef Abdiel Janulgue: > > Pretend to run on a non-intel machine even when running on i915.ko, > > so that we could run and gather passrate data. What exactly do you mean? > > Signed-off-by: Abdiel

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [CI,1/5] drm/i915: Rename intel_guc.h to intel_uc.h

On Mon, Nov 28, 2016 at 12:53:27PM +, Patchwork wrote: > == Series Details == > > Series: series starting with [CI,1/5] drm/i915: Rename intel_guc.h to > intel_uc.h > URL : https://patchwork.freedesktop.org/series/16034/ > State : warning > > == Summary == > > Series 16034v1 Series

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Enable HPD interrupts with master ctl interrupt

On 11/23/2016 10:31 PM, Imre Deak wrote: On Wed, 2016-11-23 at 21:48 +0530, Animesh Manna wrote: While suspending the device hpd related interrupts are enabled to get the interrupt when device is in suspend state. Though display is in DC9 but system can be in S0 or S0i3 state. Hot plug

Re: [Intel-gfx] [PATCH v3 2/3] drm/i915/gen9: Fix PCODE polling during CDCLK change notification

On ma, 2016-11-28 at 15:51 +0200, Ville Syrjälä wrote: > On Mon, Nov 28, 2016 at 01:12:57PM +0200, Imre Deak wrote: > > commit 848496e5902833600f7992f4faa82dc1546051ba > > Author: Ville Syrjälä > > Date:   Wed Jul 13 16:32:03 2016 +0300 > > > > drm/i915: Wait

Re: [Intel-gfx] [PATCH] drm/i915: drop the struct_mutex when wedged or trying to reset

On ma, 2016-11-28 at 13:40 +0200, Jani Nikula wrote: > > On Mon, 28 Nov 2016, Joonas Lahtinen > > wrote: > > > > Cc: stable # v4.6 ? > > $ dim fixes 7f1847ebf48b > Fixes: 7f1847ebf48b ("drm/i915: Simplify checking of GPU reset_counter in > display pageflips") >

Re: [Intel-gfx] [PATCH 11/15] drm/i915: Trim i915_guc_info() stack usage

On 28/11/2016 11:35, Chris Wilson wrote: On Mon, Nov 28, 2016 at 11:15:27AM +, Tvrtko Ursulin wrote: On 25/11/2016 09:30, Chris Wilson wrote: i915_guc_info() (part of debugfs output) tries to avoid holding struct_mutex for a long period by copying onto the stack. This causes a warning

Re: [Intel-gfx] [RFC PATCH v3 2/7] drm/i915: Add support for audio driver notifications

On Fri, Nov 25, 2016 at 05:51:00AM +, Anand, Jerome wrote: > > > > -Original Message- > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > > Sent: Thursday, November 24, 2016 7:03 PM > > To: Anand, Jerome > > Cc: intel-gfx@lists.freedesktop.org;

Re: [Intel-gfx] [PATCH v3 2/3] drm/i915/gen9: Fix PCODE polling during CDCLK change notification

On Mon, Nov 28, 2016 at 04:06:05PM +0200, Ville Syrjälä wrote: > On Mon, Nov 28, 2016 at 03:54:08PM +0200, Imre Deak wrote: > > On ma, 2016-11-28 at 15:51 +0200, Ville Syrjälä wrote: > > > On Mon, Nov 28, 2016 at 01:12:57PM +0200, Imre Deak wrote: > > > > commit

Re: [Intel-gfx] [PATCH 11/15] drm/i915: Trim i915_guc_info() stack usage

On Mon, Nov 28, 2016 at 11:15:27AM +, Tvrtko Ursulin wrote: > > On 25/11/2016 09:30, Chris Wilson wrote: > >i915_guc_info() (part of debugfs output) tries to avoid holding > >struct_mutex for a long period by copying onto the stack. This causes a > >warning that the stack frame is massive, so

Re: [Intel-gfx] [PATCH 13/15] drm/i915/guc: Initialise doorbell cookie to matching value

On Mon, Nov 28, 2016 at 12:09:38PM +, Tvrtko Ursulin wrote: > > On 25/11/2016 09:30, Chris Wilson wrote: > >Set the initial value of the doorbell cookie from the client. > > > >Signed-off-by: Chris Wilson > >--- > > drivers/gpu/drm/i915/i915_guc_submission.c | 2 +-

Re: [Intel-gfx] [PATCH 15/15] drm/i915/guc: Split hw submission for replay after GPU reset

On 25/11/2016 09:30, Chris Wilson wrote: Something I missed before sending off the partial series was that the non-scheduler guc reset path was broken (in the full series, this is pushed to the execlists reset handler). The issue is that after a reset, we have to refill the GuC workqueues,

[Intel-gfx] [PATCH 2/2] Revert "drm/i915/execlists: Use a local lock for dfs_link access"

This reverts commit 27745e829a5c ("drm/i915/execlists: Use a local lock for dfs_link access") as the struct_mutex was required to prevent concurrent retiring and freeing, now restored in the previous patch. Signed-off-by: Chris Wilson Cc: David Weinehall

Re: [Intel-gfx] [PATCH 3/3] drm: Track framebuffer references at the point of assignment

On Mon, Nov 28, 2016 at 08:46:11AM +, Chris Wilson wrote: > On Mon, Nov 28, 2016 at 08:48:34AM +0100, Daniel Vetter wrote: > > On Fri, Nov 25, 2016 at 03:32:31PM +, Chris Wilson wrote: > > > --- a/drivers/gpu/drm/drm_atomic.c > > > +++ b/drivers/gpu/drm/drm_atomic.c > > > @@ -1253,7

Re: [Intel-gfx] [PATCH v3 2/3] drm/i915/gen9: Fix PCODE polling during CDCLK change notification

On ma, 2016-11-28 at 16:11 +0200, Ville Syrjälä wrote: > On Mon, Nov 28, 2016 at 04:06:05PM +0200, Ville Syrjälä wrote: > > On Mon, Nov 28, 2016 at 03:54:08PM +0200, Imre Deak wrote: > > > On ma, 2016-11-28 at 15:51 +0200, Ville Syrjälä wrote: > > > > On Mon, Nov 28, 2016 at 01:12:57PM +0200, Imre

[Intel-gfx] [PATCH 1/2] drm/i915: Move priority bumping for flips earlier

David found another issue with priority bumping from mmioflips, where we are accessing the requests concurrently to them being retired and freed. Whilst we are skipping the dependency if has been submitted, that is not sufficient to stop the dependency from disappearing if another thread retires

Re: [Intel-gfx] [PATCH 15/15] drm/i915/guc: Split hw submission for replay after GPU reset

Chris Wilson writes: > On Mon, Nov 28, 2016 at 02:02:33PM +, Tvrtko Ursulin wrote: >> >> On 25/11/2016 09:30, Chris Wilson wrote: >> >Something I missed before sending off the partial series was that the >> >non-scheduler guc reset path was broken (in the full

Re: [Intel-gfx] [PATCH 15/15] drm/i915/guc: Split hw submission for replay after GPU reset

On Mon, Nov 28, 2016 at 02:02:33PM +, Tvrtko Ursulin wrote: > > On 25/11/2016 09:30, Chris Wilson wrote: > >Something I missed before sending off the partial series was that the > >non-scheduler guc reset path was broken (in the full series, this is > >pushed to the execlists reset handler).

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Enable HPD interrupts with master ctl interrupt

On ma, 2016-11-28 at 19:09 +0530, Animesh Manna wrote: > > On 11/23/2016 10:31 PM, Imre Deak wrote: > > On Wed, 2016-11-23 at 21:48 +0530, Animesh Manna wrote: > > > While suspending the device hpd related interrupts are enabled > > > to get the interrupt when device is in suspend state. > > > >

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/debugfs: add dp mst info

== Series Details == Series: series starting with [1/3] drm/i915/debugfs: add dp mst info URL : https://patchwork.freedesktop.org/series/16036/ State : success == Summary == Series 16036v1 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/16036/revisions/1/mbox/

Re: [Intel-gfx] [PATCH 1/3] drm: Hold mode_config.lock to prevent hotplug whilst setting up crtcs

On Mon, Nov 28, 2016 at 08:26:07AM +0100, Daniel Vetter wrote: > On Wed, Nov 23, 2016 at 02:04:15PM +, Chris Wilson wrote: > > +#define drm_fb_helper_for_each_connector(fbh, i__) \ > > + for (({lockdep_assert_held(&(fbh)->dev->mode_config.mutex); 1;}), \ > > +i__ = 0; i__ <

[Intel-gfx] [PATCH v4 3/3] drm/i915/gen9: Fix PCODE polling during SAGV disabling

According to the previous patch, it's possible atm that we call intel_do_sagv_disable() only once during the 1ms period and time out if that call fails. As opposed to this the spec says that we need to keep retrying this request for a 1ms duration, so let's do this similarly to the CDCLK change

Re: [Intel-gfx] [PATCH 3/3] drm: Track framebuffer references at the point of assignment

On Mon, Nov 28, 2016 at 02:44:15PM +, Chris Wilson wrote: > On Mon, Nov 28, 2016 at 03:15:12PM +0100, Daniel Vetter wrote: > > On Mon, Nov 28, 2016 at 08:46:11AM +, Chris Wilson wrote: > > > On Mon, Nov 28, 2016 at 08:48:34AM +0100, Daniel Vetter wrote: > > > > On Fri, Nov 25, 2016 at

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Move priority bumping for flips earlier

== Series Details == Series: series starting with [1/2] drm/i915: Move priority bumping for flips earlier URL : https://patchwork.freedesktop.org/series/16043/ State : success == Summary == Series 16043v1 Series without cover letter

[Intel-gfx] [PATCH v4 1/3] drm/i915/gen6+: Clear upper data byte during PCODE write

The spec calls for the upper data byte to be cleared before most of the PCODE write commands, for others like IPS control it doesn't say anything about this byte. Let's clear it in case it's clobbered somehow, especially that there are places where we only do a PCODE write without a preceeding

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/3] drm/i915/gen6+: Clear upper data byte during PCODE write

== Series Details == Series: series starting with [v4,1/3] drm/i915/gen6+: Clear upper data byte during PCODE write URL : https://patchwork.freedesktop.org/series/16046/ State : success == Summary == Series 16046v1 Series without cover letter

Re: [Intel-gfx] [PATCH 14/15] drm/i915/guc: Keep the execbuf client allocated across reset

On 28/11/2016 14:11, Chris Wilson wrote: On Mon, Nov 28, 2016 at 01:49:03PM +, Tvrtko Ursulin wrote: On 25/11/2016 09:30, Chris Wilson wrote: In order to avoid some complexity in trying to reconstruct the workqueues across reset, remember them instead. The issue comes when we have to

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Enable HPD interrupts with master ctl interrupt

On 11/23/2016 10:40 PM, Ville Syrjälä wrote: On Wed, Nov 23, 2016 at 09:48:27PM +0530, Animesh Manna wrote: While suspending the device hpd related interrupts are enabled to get the interrupt when device is in suspend state. Though display is in DC9 but system can be in S0 or S0i3 state. Hot

Re: [Intel-gfx] [PATCH 3/3] drm: Protect fb_helper list manipulation with a mutex

On Mon, Nov 28, 2016 at 08:38:21AM +, Chris Wilson wrote: > On Mon, Nov 28, 2016 at 08:55:58AM +0100, Daniel Vetter wrote: > > On Wed, Nov 23, 2016 at 02:04:17PM +, Chris Wilson wrote: > > > Though we only walk the kernel_fb_helper_list inside a panic (or single > > > thread debugging), we

Re: [Intel-gfx] [PATCH 3/3] drm: Track framebuffer references at the point of assignment

On Mon, Nov 28, 2016 at 03:15:12PM +0100, Daniel Vetter wrote: > On Mon, Nov 28, 2016 at 08:46:11AM +, Chris Wilson wrote: > > On Mon, Nov 28, 2016 at 08:48:34AM +0100, Daniel Vetter wrote: > > > On Fri, Nov 25, 2016 at 03:32:31PM +, Chris Wilson wrote: > > > > ---

[Intel-gfx] [PATCH v4 2/3] drm/i915/gen9: Fix PCODE polling during CDCLK change notification

commit 848496e5902833600f7992f4faa82dc1546051ba Author: Ville Syrjälä Date: Wed Jul 13 16:32:03 2016 +0300 drm/i915: Wait up to 3ms for the pcu to ack the cdclk change request on SKL increased the timeout to match the spec, but we still see a timeout on at

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Enable HPD interrupts with master ctl interrupt

On Mon, Nov 28, 2016 at 09:19:36PM +0530, Animesh Manna wrote: > > > On 11/23/2016 10:40 PM, Ville Syrjälä wrote: > > On Wed, Nov 23, 2016 at 09:48:27PM +0530, Animesh Manna wrote: > >> While suspending the device hpd related interrupts are enabled > >> to get the interrupt when device is in

Re: [Intel-gfx] [PATCH 1/5] drm/i915/bxt: Corrected the guid for bxt.

On 11/28/2016 4:54 PM, Jani Nikula wrote: On Mon, 28 Nov 2016, Animesh Manna wrote: On 11/23/2016 10:02 PM, Chris Wilson wrote: On Wed, Nov 23, 2016 at 09:48:23PM +0530, Animesh Manna wrote: Guid is changed for bxt platform, so corrected the guid for bxt. v1:

Re: [Intel-gfx] [PATCH v4 2/3] drm/i915/gen9: Fix PCODE polling during CDCLK change notification

On Mon, Nov 28, 2016 at 06:12:51PM +0200, Imre Deak wrote: > On ma, 2016-11-28 at 17:58 +0200, Ville Syrjälä wrote: > > On Mon, Nov 28, 2016 at 05:29:28PM +0200, Imre Deak wrote: > > > commit 848496e5902833600f7992f4faa82dc1546051ba > > > Author: Ville Syrjälä > > >

Re: [Intel-gfx] [PATCH 14/15] drm/i915/guc: Keep the execbuf client allocated across reset

On Mon, Nov 28, 2016 at 03:44:41PM +, Tvrtko Ursulin wrote: > > On 28/11/2016 14:11, Chris Wilson wrote: > >On Mon, Nov 28, 2016 at 01:49:03PM +, Tvrtko Ursulin wrote: > >> > >>On 25/11/2016 09:30, Chris Wilson wrote: > >>>In order to avoid some complexity in trying to reconstruct the >

Re: [Intel-gfx] [PATCH 15/15] drm/i915/guc: Split hw submission for replay after GPU reset

On Mon, Nov 28, 2016 at 03:55:42PM +, Tvrtko Ursulin wrote: > > On 28/11/2016 14:19, Chris Wilson wrote: > >On Mon, Nov 28, 2016 at 02:02:33PM +, Tvrtko Ursulin wrote: > >> > >>On 25/11/2016 09:30, Chris Wilson wrote: > >>>Something I missed before sending off the partial series was that

Re: [Intel-gfx] [PATCH 3/5] drm/i915/bxt: Added _DSM call to set HPD_CTL.

On 11/23/2016 11:47 PM, Ville Syrjälä wrote: On Wed, Nov 23, 2016 at 09:48:25PM +0530, Animesh Manna wrote: _DSM is added to program HPD_CTL(0x1094) register of PMC from i915 driver which will be called based on driver feature flag. PMC hpd control register programming will enable PMC to get

Re: [Intel-gfx] [PATCH v4 2/3] drm/i915/gen9: Fix PCODE polling during CDCLK change notification

On ma, 2016-11-28 at 17:58 +0200, Ville Syrjälä wrote: > On Mon, Nov 28, 2016 at 05:29:28PM +0200, Imre Deak wrote: > > commit 848496e5902833600f7992f4faa82dc1546051ba > > Author: Ville Syrjälä > > Date:   Wed Jul 13 16:32:03 2016 +0300 > > > > drm/i915: Wait

Re: [Intel-gfx] [PATCH 3/5] drm/i915/bxt: Added _DSM call to set HPD_CTL.

On Mon, Nov 28, 2016 at 09:36:51PM +0530, Animesh Manna wrote: > > > On 11/23/2016 11:47 PM, Ville Syrjälä wrote: > > On Wed, Nov 23, 2016 at 09:48:25PM +0530, Animesh Manna wrote: > >> _DSM is added to program HPD_CTL(0x1094) register > >> of PMC from i915 driver which will be called > >> based

[Intel-gfx] [PATCH v5 2/3] drm/i915/gen9: Fix PCODE polling during CDCLK change notification

commit 848496e5902833600f7992f4faa82dc1546051ba Author: Ville Syrjälä Date: Wed Jul 13 16:32:03 2016 +0300 drm/i915: Wait up to 3ms for the pcu to ack the cdclk change request on SKL increased the timeout to match the spec, but we still see a timeout on at

Re: [Intel-gfx] [RFC PATCH v3 2/7] drm/i915: Add support for audio driver notifications

> -Original Message- > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > Sent: Monday, November 28, 2016 7:30 PM > To: Anand, Jerome > Cc: intel-gfx@lists.freedesktop.org; alsa-de...@alsa-project.org; > broo...@kernel.org; ti...@suse.de;

Re: [Intel-gfx] [PATCH v5 2/3] drm/i915/gen9: Fix PCODE polling during CDCLK change notification

On Mon, Nov 28, 2016 at 06:40:33PM +0200, Imre Deak wrote: > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 66c62f3..4e06e92 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7864,6 +7864,59 @@ int

Re: [Intel-gfx] [RFC PATCH v3 2/7] drm/i915: Add support for audio driver notifications

On Mon, Nov 28, 2016 at 04:50:15PM +, Anand, Jerome wrote: > > > > -Original Message- > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > > Sent: Monday, November 28, 2016 7:30 PM > > To: Anand, Jerome > > Cc: intel-gfx@lists.freedesktop.org;

Re: [Intel-gfx] [PATCH 15/15] drm/i915/guc: Split hw submission for replay after GPU reset

On 28/11/2016 14:19, Chris Wilson wrote: On Mon, Nov 28, 2016 at 02:02:33PM +, Tvrtko Ursulin wrote: On 25/11/2016 09:30, Chris Wilson wrote: Something I missed before sending off the partial series was that the non-scheduler guc reset path was broken (in the full series, this is pushed

Re: [Intel-gfx] [PATCH v4 2/3] drm/i915/gen9: Fix PCODE polling during CDCLK change notification

On Mon, Nov 28, 2016 at 05:29:28PM +0200, Imre Deak wrote: > commit 848496e5902833600f7992f4faa82dc1546051ba > Author: Ville Syrjälä > Date: Wed Jul 13 16:32:03 2016 +0300 > > drm/i915: Wait up to 3ms for the pcu to ack the cdclk change request on > SKL > >

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/3] drm/i915/gen6+: Clear upper data byte during PCODE write (rev2)

== Series Details == Series: series starting with [v4,1/3] drm/i915/gen6+: Clear upper data byte during PCODE write (rev2) URL : https://patchwork.freedesktop.org/series/16046/ State : success == Summary == Series 16046v2 Series without cover letter

[Intel-gfx] [PATCH 00/15] drm/i915: VLV/CHV atomic wm prep work

From: Ville Syrjälä A decent pile of prep work split off from my VLV/CHV atomic watermark work. Mostly VLV/CHV specific stuff, but there are a few small things in there that touch other platforms as well. Entire series available here:

[Intel-gfx] [PATCH 12/15] drm/i915: Zero out HOWM registers before writing new WM/HOWM register values

From: Ville Syrjälä On VLV/CHV some of the watermark values are split across two registers: low order bits in one, and high order bits in another. So we may not be able to update a single watermark value atomically, and thus we must be careful that we don't

[Intel-gfx] [PATCH 05/15] drm/i915: Remove duplicated wm setup for vlv and chv

From: Ville Syrjälä The code for vlv and chv wm latency/function pointer setup is identical. Drop one of the copies. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 5 + 1 file changed, 1 insertion(+), 4

[Intel-gfx] [PATCH 02/15] drm/i915: Use the ilk_disable_lp_wm() return value

From: Ville Syrjälä ilk_disable_lp_wm() will tell us whether the LP1+ watermarks were disabled or not, and hence whether we need to for the vblank wait or not. Let's use that information to eliminate some useless vblank waits. Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 03/15] drm/i915: Fix the level 0 max_wm hack on VLV/CHV

From: Ville Syrjälä The watermark should never exceed the FIFO size, so we need to check against the current FIFO size instead of the theoretical maximum when we clamp the level 0 watermark. Signed-off-by: Ville Syrjälä ---

[Intel-gfx] [PATCH 01/15] drm/i915: Drop the nop intel_update_watermarks() call from haswell_crtc_enable()

From: Ville Syrjälä HSW+ all use the .initial_watermarks() hook, so there's no point in calling intel_update_watermarks() from HSW+ specific code. We'll still hang on to the .initial_watermarks NULL check since theoretically if the memory latencies are not

[Intel-gfx] [PATCH 06/15] drm/i915: Organize vlv/chv watermarks by plane_id

From: Ville Syrjälä Store the vlv/chv watermark values in straight up arrays indexed by enum plane_id. Avoids a lot of useless checks for the plane type when we don't have to think which structure member we need to access. Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 08/15] drm/i915: Pass around dev_priv in vlv wm functions

From: Ville Syrjälä Pasing dev_priv instead of dev is the future. Let's make the vlv/chv wm functions respect that idea. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 24 +++- 1 file

[Intel-gfx] [PATCH 09/15] drm/i915: Protect cxsr state with wm_mutex

From: Ville Syrjälä Let's protect the cxsr state with the wm_mutex, since it might get poked from multiple places if there's a parallel plane update happening with a pipe getting enable/disabled. It's still pretty racy for the old platforms, but for vlv/chv it

[Intel-gfx] [PATCH 15/15] drm/i915: Pass crtc state to vlv_compute_wm_level()

From: Ville Syrjälä Rather than accessing crtc->config in vlv_compute_wm_level() let's pass in the crtc state explicitly. One step closer to atomic. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 20

[Intel-gfx] [PATCH 11/15] drm/i915: Protect DSPARB registers with a spinlock

From: Ville Syrjälä Each DSPARB register can house bits for two separate pipes, hence we must protect the registers during reprogramming so that parallel FIFO reconfigurations happening simultaneosly on multiple pipes won't corrupt each others values.

[Intel-gfx] [PATCH 13/15] drm/i915: Write all DDL registers in one go

From: Ville Syrjälä We'll want to decouple the vlv/chv wm register reprogramming from any single pipe. So let's just write all the DDL registers in one go. We already write all the wm registers anyway since the bits are sprinkled all over the place and so writing

[Intel-gfx] [PATCH 07/15] drm/i915: Introduce vlv_invert_wm_value()

From: Ville Syrjälä Add a small helper to do invert the vlv/chv values. Less fragile perhaps, and let's us clearly mark all overlarge wateramarks as disabled (by just making them all USHRT_MAX). Signed-off-by: Ville Syrjälä ---

[Intel-gfx] [PATCH 14/15] drm/i915: Clean up vlv_program_watermarks()

From: Ville Syrjälä Add small helpers to make the intent of the staggered enable/disable sequence in vlv_program_watermarks() easier on the eyes. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 44

Re: [Intel-gfx] [RFC PATCH v3 2/7] drm/i915: Add support for audio driver notifications

On Mon, Nov 28, 2016 at 01:13:31PM -0600, Pierre-Louis Bossart wrote: > > On 11/28/16 11:01 AM, Ville Syrjälä wrote: > >> + if (pdata->notify_audio_lpe) > >> + pdata->notify_audio_lpe( > >> + (eld

[Intel-gfx] [PATCH 04/15] drm/i915: Clean up VLV/CHV maxfifo watermark setup

From: Ville Syrjälä Let's compute the maxfifo watermarks using max() instead of min(). Can't even recall why I did it the other way originally. Anyways using max() avoids having to initialize the watermarks to the max value first. Signed-off-by: Ville Syrjälä

Re: [Intel-gfx] [RFC i-g-t 0/4] intel-gpu-tools: Add support for the Chamelium

As a note: I finally managed to figure out what the problem was with the CRC readback. Turns out when I compiled the chamelium source code, I completely forgot to point it to an arm compiler so the chamelium kept trying to run x86_64 binaries… On Wed, 2016-11-16 at 12:52 +0100, Tomeu Vizoso

Re: [Intel-gfx] [PATCH v5 2/3] drm/i915/gen9: Fix PCODE polling during CDCLK change notification

On ma, 2016-11-28 at 17:13 +, Chris Wilson wrote: > On Mon, Nov 28, 2016 at 06:40:33PM +0200, Imre Deak wrote: > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > b/drivers/gpu/drm/i915/intel_pm.c > > index 66c62f3..4e06e92 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: VLV/CHV atomic wm prep work

== Series Details == Series: drm/i915: VLV/CHV atomic wm prep work URL : https://patchwork.freedesktop.org/series/16049/ State : success == Summary == Series 16049v1 drm/i915: VLV/CHV atomic wm prep work https://patchwork.freedesktop.org/api/1.0/series/16049/revisions/1/mbox/ fi-bdw-5557u

Re: [Intel-gfx] [RFC PATCH v3 2/7] drm/i915: Add support for audio driver notifications

On 11/28/16 11:01 AM, Ville Syrjälä wrote: + if (pdata->notify_audio_lpe) + pdata->notify_audio_lpe( + (eld != NULL) ? >eld : NULL); + else +

Re: [Intel-gfx] [PATCH RFC v3] drm: Add a new connector atomic property for link status

On Thu, Nov 24, 2016 at 08:51:35AM +0100, Daniel Vetter wrote: > On Wed, Nov 23, 2016 at 11:28:21PM -0800, Manasi Navare wrote: > > This is RFC patch for adding a connector link-status property > > and making it atomic by adding it to the drm_connector_state. > > This is to make sure its wired

Re: [Intel-gfx] [PATCH ddx 2/2] intel: Adding Marketing names for Skylake, Kabylake and Apollolake/Broxton.

Chris, any comments? what is still missing? Thanks, Rodrigo. On Thu, Nov 17, 2016 at 2:46 PM, Rodrigo Vivi wrote: > This commit adding all known marketing names for latest gen9 platforms. > > v2: On top of simplified generic string names. > > Cc: Chris Wilson

Re: [Intel-gfx] [RFC PATCH v3 2/7] drm/i915: Add support for audio driver notifications

On 11/28/16 1:30 PM, Ville Syrjälä wrote: On Mon, Nov 28, 2016 at 01:13:31PM -0600, Pierre-Louis Bossart wrote: On 11/28/16 11:01 AM, Ville Syrjälä wrote: + if (pdata->notify_audio_lpe) + pdata->notify_audio_lpe( +

Re: [Intel-gfx] [PATCH RFC] drm: Add a new connector atomic property for link status

On Wed, Nov 23, 2016 at 09:09:28AM +0100, Daniel Vetter wrote: > On Tue, Nov 22, 2016 at 09:27:35PM -0500, Sean Paul wrote: > > On Tue, Nov 22, 2016 at 8:30 PM, Manasi Navare > > wrote: > > > This is RFC patch for adding a connector link-status property > > > and making

Re: [Intel-gfx] [PATCH RFC v3] drm: Add a new connector atomic property for link status

On Thu, Nov 24, 2016 at 08:51:35AM +0100, Daniel Vetter wrote: > On Wed, Nov 23, 2016 at 11:28:21PM -0800, Manasi Navare wrote: > > This is RFC patch for adding a connector link-status property > > and making it atomic by adding it to the drm_connector_state. > > This is to make sure its wired

[Intel-gfx] [PATCH] drm/i915: fix compilation warnings on maybe uninitialized pointers

Two warnings are produced by gcc (tested with gcc 6.2.1): drivers/gpu/drm/i915/intel_csr.c: In function ‘csr_load_work_fn’: drivers/gpu/drm/i915/intel_csr.c:400:5: error: ‘fw’ is used uninitialized in this function [-Werror=uninitialized] if (fw) ^ and In file included from

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: fix compilation warnings on maybe uninitialized pointers

== Series Details == Series: drm/i915: fix compilation warnings on maybe uninitialized pointers URL : https://patchwork.freedesktop.org/series/16061/ State : success == Summary == Series 16061v1 drm/i915: fix compilation warnings on maybe uninitialized pointers

[Intel-gfx] [PATCH] drm/i915: Move the release of PT page to the upper caller

a PT page will be released if it doesn't contain any meaningful mappings during PPGTT page table shrinking. The PT entry in the upper level will be set to a scratch entry. Normally this works nicely, but in virtualization world, the PPGTT page table is tracked by hypervisor. Releasing the PT page

Re: [Intel-gfx] [PATCH] drm/i915: Move the release of PT page to the upper caller

Thanks Chirs and Michal :P Please take this patch. :) On 11/29/16 14:55, Zhi Wang wrote: a PT page will be released if it doesn't contain any meaningful mappings during PPGTT page table shrinking. The PT entry in the upper level will be set to a scratch entry. Normally this works nicely, but

[Intel-gfx] [PATCH v3] drm/i915: Move number of scalers initialization to runtime init

In future patches, we require greater flexibility in describing the number of scalers available on each CRTC. To ease that transition we move the current assignment to intel_device_info. Scaler structure initialisation is done if scaler is available on the CRTC. Gen9 check is not required as on

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Moving scaler numbers to runtime init (rev5)

== Series Details == Series: drm/i915: Moving scaler numbers to runtime init (rev5) URL : https://patchwork.freedesktop.org/series/15726/ State : success == Summary == Series 15726v5 drm/i915: Moving scaler numbers to runtime init

Re: [Intel-gfx] [PATCH v6 8/8] drm/i915/gen9: WM memory bandwidth related workaround

Hi, On Thursday 24 November 2016 06:21 PM, Lankhorst, Maarten wrote: Mahesh Kumar schreef op do 24-11-2016 om 09:31 [+0530]: This patch implemnets Workariunds related to display arbitrated memory bandwidth. These WA are applicabe for all gen-9 based platforms. Changes since v1: - Rebase on

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