[Intel-gfx] ✗ Fi.CI.BAT: warning for HuC Loading Patches

[Patchwork]

== Series Details ==

Series: HuC Loading Patches
URL   : https://patchwork.freedesktop.org/series/18008/
State : warning

== Summary ==

Series 18008v1 HuC Loading Patches
https://patchwork.freedesktop.org/api/1.0/series/18008/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
pass   -> DMESG-WARN (fi-bxt-j4205)

fi-bdw-5557u total:246  pass:232  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050 total:246  pass:207  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:246  pass:223  dwarn:1   dfail:0   fail:0   skip:22 
fi-bxt-t5700 total:82   pass:69   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:246  pass:219  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-ivb-3520m total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770  total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6260u total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hqtotal:246  pass:226  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k total:246  pass:222  dwarn:3   dfail:0   fail:0   skip:21 
fi-skl-6770hqtotal:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2520m total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-snb-2600  total:246  pass:214  dwarn:0   dfail:0   fail:0   skip:32 

a957dfe613ab43c6af84833f2b88ea941320250f drm-tip: 2017y-01m-13d-18h-49m-04s UTC 
integration manifest
e8ce497 drm/i915/get_params: Add HuC status to getparams
0faab16 drm/i915/huc: Support HuC authentication
46c0d55 drm/i915/huc: Add debugfs for HuC loading status check
36c724c drm/i915/HuC: Add KBL huC loading Support
eb9329d drm/i915/huc: Add BXT HuC Loading Support
e9fa83c drm/i915/huc: Add HuC fw loading support
82a4dd5 drm/i915/huc: Unified css_header struct for GuC and HuC
9276f97 drm/i915/guc: Make the GuC fw loading helper functions general

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3518/
___
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[Intel-gfx] [PATCH 0/8] HuC Loading Patches

[Anusha Srivatsa]

The patches add HuC loading support. The driver builds a frame level
workload which is stored in the graphics memory. This workload is presented
to HuC for processing. The driver, therefore should first determine if the
HuC is enabled and also read the huC athentication status bit to determine
if HuC was successfully loaded. The GuC is required to authenticate the HuC.
The userspace patches that check for a fully loaded HuC firmware and use it
can be found at:

https://lists.freedesktop.org/archives/libva/2016-September/004554.html
https://lists.freedesktop.org/archives/libva/2016-September/004555.html

More information regarding the HuC, batch commands that configure the
HuC etc can be found at-
https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol02a-commandreference-instructions-huc.pdf
https://www.x.org/docs/intel/CHV/intel-gfx-prm-osrc-chv-bsw-vol10-hevc.pdf

v2: rebased. Changed the code following the review comments.
v3: rebased. Organize code. Move contents of intel_huc.h to intel_uc.h.
Update function intel_huc_load(),intel_huc_init() and intel_uc_fw_fetch()
to accept dev_priv instead of dev.
v4: rebased. Remove intel_is_huc_valid() since it is called onoly once.
Refactor the code to reduce redundency. Remove fiels like uc_dev which
are no longer used.
v5: rebased. Beautify the code- remove comments that no longer hold
good, add newlines etc.
v6: rebased. Remove further redundency. Correct comments. Replace wait_for
with intel_wait_for_register() for optimisation purpose.Make fw_type an enum.
v7: rebased. Rename intel_huc_loader() to intel_huc(). Move intel_guc_auth_huc()
from intel_uc.c to intel_huc.c. Add return values to DRM_ERRORs.
v8: Use DRM_INFO instead of DRM_ERROR in places that are non-erraneous.
Remove invalidates that are no longer required.

Anusha Srivatsa (8):
  drm/i915/guc: Make the GuC fw loading helper functions general
  drm/i915/huc: Unified css_header struct for GuC and HuC
  drm/i915/huc: Add HuC fw loading support
  drm/i915/huc: Add BXT HuC Loading Support
  drm/i915/HuC: Add KBL huC loading Support
  drm/i915/huc: Add debugfs for HuC loading status check
  drm/i915/huc: Support HuC authentication
  drm/i915/get_params: Add HuC status to getparams

 drivers/gpu/drm/i915/Makefile  |   1 +
 drivers/gpu/drm/i915/i915_debugfs.c|  43 +++-
 drivers/gpu/drm/i915/i915_drv.c|  10 +
 drivers/gpu/drm/i915/i915_drv.h|   2 +
 drivers/gpu/drm/i915/i915_guc_reg.h|   6 +
 drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
 drivers/gpu/drm/i915/intel_guc_fwif.h  |  24 +-
 drivers/gpu/drm/i915/intel_guc_loader.c| 196 +
 drivers/gpu/drm/i915/intel_huc.c   | 342 +
 drivers/gpu/drm/i915/intel_uc.h|  60 +++--
 include/uapi/drm/i915_drm.h|   1 +
 11 files changed, 569 insertions(+), 120 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_huc.c

-- 
2.7.4

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[Intel-gfx] [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Anusha Srivatsa]

The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.

v2: rebased on top of drm-tip. Changed name format and upped
version 1.7.
v3: changed wait_for_atomic to wait_for
v4: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
and place the prototype in intel_guc.h,correct the comments.
v5: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
AUTHENTICATE_HUC
v6: rebased. Add newline on DRM_ERRORs that already dont have one.
v7: rebased. Replace wait_for with intel_wait_for_register() since
the latter employs sleep optimisations for quick responses- as pointed
out by Chris Wilson.
v8: rebased. Cleanup the intel_guc_auth_huc() by removing checks
already performed in earlier functions. Make comments more descriptive.
v9: rebased. Changed the bias for pinning the HuC object. Move
intel_guc_auth_huc() to intel_huc.c. Change DRM_DEBUGs to DRM_ERRORs
in intel_guc_auth_huc(). Add return status to DRM_ERRORs.
v10: Remove message not required for the user..

Cc: Chris Wilson 
Cc: Arkadiusz Hiler 
Cc: Michal Wajdeczko 
Tested-by: Xiang Haihao 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Alex Dai 
Signed-off-by: Peter Antoine 
---
 drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
 drivers/gpu/drm/i915/intel_huc.c| 49 +
 drivers/gpu/drm/i915/intel_uc.h |  1 +
 4 files changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index ed1ab40..25691f0 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -505,6 +505,7 @@ enum intel_guc_action {
INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
+   INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
INTEL_GUC_ACTION_LIMIT
 };
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 527558f..bb127a4 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -530,6 +530,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
intel_uc_fw_status_repr(guc_fw->fetch_status),
intel_uc_fw_status_repr(guc_fw->load_status));
 
+   intel_guc_auth_huc(dev_priv);
+
if (i915.enable_guc_submission) {
if (i915.guc_log_level >= 0)
gen9_enable_guc_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 8b84ba8..897ef31 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -284,3 +284,52 @@ void intel_huc_fini(struct drm_i915_private *dev_priv)
huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
 }
 
+/**
+ * intel_guc_auth_huc() - authenticate ucode
+ * @dev_priv: the drm_i915_device
+ *
+ * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
+ * authenticate_huc interface.
+ */
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
+{
+   struct intel_guc *guc = _priv->guc;
+   struct intel_huc *huc = _priv->huc;
+   struct i915_vma *vma;
+   int ret;
+   u32 data[2];
+
+   vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
+   PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
+   if (IS_ERR(vma)) {
+   DRM_ERROR("failed to pin huc fw object %d\n",
+   (int)PTR_ERR(vma));
+   return;
+   }
+
+   /* Specify auth action and where public signature is. */
+   data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
+   data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
+
+   ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
+   if (ret) {
+   DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
+   goto out;
+   }
+
+   /* Check authentication status, it should be done by now */
+   ret = intel_wait_for_register(dev_priv,
+   HUC_STATUS2,
+   HUC_FW_VERIFIED,
+   HUC_FW_VERIFIED,
+   50);
+
+   if (ret) {
+   DRM_ERROR("HuC: Authentication failed %d\n", ret);
+   goto out;
+   }
+
+out:
+   i915_vma_unpin(vma);
+}
+
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 65c7d6e..27f8b6f 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -227,5 

[Intel-gfx] [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC

[Anusha Srivatsa]

HuC firmware css header has almost exactly same definition as GuC
firmware except for the sw_version. Also, add a new member fw_type
into intel_uc_fw to indicate what kind of fw it is. So, the loader
will pull right sw_version from header.

v2: rebased on-top of drm-intel-nightly
v3: rebased. Rename device_id to guc_branch_client_version,
make guc_sw_version a union. . Put UC_FW_TYPE_GUC
and UC_FW_TYPE_HUC into an enum.
v4: rebased on top of drm-tip.Update dev to dev_priv in
intel_uc_fw_fetch.
v5: rebased. Add INTEL_ prefix to an enum. Add fw_type declaration
from patch 1.Combine two different unions for huc and guc version,
reserved etc into one union with two structs.
v6: rebased. Change fw_type to enum.
v7: rebased. Rename the enum fw_type to intel_uc_fw_type.

Cc: Michal Wajdeczko 
Tested-by: Xiang Haihao 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Alex Dai 
Signed-off-by: Peter Antoine 
Reviewed-by: Arkadiusz Hiler 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/intel_guc_fwif.h   | 23 ++
 drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++---
 drivers/gpu/drm/i915/intel_uc.h |  6 +
 3 files changed, 53 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 3202b32..ed1ab40 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -145,7 +145,7 @@
  * The GuC firmware layout looks like this:
  *
  * +---+
- * |guc_css_header |
+ * | uc_css_header |
  * |   |
  * | contains major/minor version  |
  * +---+
@@ -172,9 +172,16 @@
  * 3. Length info of each component can be found in header, in dwords.
  * 4. Modulus and exponent key are not required by driver. They may not appear
  *in fw. So driver will load a truncated firmware in this case.
+ *
+ * HuC firmware layout is same as GuC firmware.
+ *
+ * HuC firmware css header is different. However, the only difference is where
+ * the version information is saved. The uc_css_header is unified to support
+ * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
+ * uc_css_header.guc_sw_version for GuC.
  */
 
-struct guc_css_header {
+struct uc_css_header {
uint32_t module_type;
/* header_size includes all non-uCode bits, including css_header, rsa
 * key, modulus key and exponent data. */
@@ -205,8 +212,16 @@ struct guc_css_header {
 
char username[8];
char buildnumber[12];
-   uint32_t device_id;
-   uint32_t guc_sw_version;
+   union {
+   struct {
+   uint32_t branch_client_version;
+   uint32_t sw_version;
+   } guc;
+   struct {
+   uint32_t sw_version;
+   uint32_t reserved;
+   } huc;
+   };
uint32_t prod_preprod_fw;
uint32_t reserved[12];
uint32_t header_info;
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 5a2c86f..30801ee 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -595,7 +595,7 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
struct pci_dev *pdev = dev_priv->drm.pdev;
struct drm_i915_gem_object *obj;
const struct firmware *fw = NULL;
-   struct guc_css_header *css;
+   struct uc_css_header *css;
size_t size;
int err;
 
@@ -612,19 +612,19 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
uc_fw->path, fw);
 
/* Check the size of the blob before examining buffer contents */
-   if (fw->size < sizeof(struct guc_css_header)) {
+   if (fw->size < sizeof(struct uc_css_header)) {
DRM_NOTE("Firmware header is missing\n");
goto fail;
}
 
-   css = (struct guc_css_header *)fw->data;
+   css = (struct uc_css_header *)fw->data;
 
/* Firmware bits always start from header */
uc_fw->header_offset = 0;
uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
 
-   if (uc_fw->header_size != sizeof(struct guc_css_header)) {
+   if (uc_fw->header_size != sizeof(struct uc_css_header)) {
DRM_NOTE("CSS header definition mismatch\n");
goto fail;
}
@@ -648,21 +648,36 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
goto fail;
}
 
-   /* Header and uCode will be loaded to WOPCM. Size of the two. */
-   size = 

[Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support

[Anusha Srivatsa]

The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
is used for both cases.

HuC loading needs to be before GuC loading. The WOPCM setting must
be done early before loading any of them.

v2: rebased on-top of drm-intel-nightly.
removed if(HAS_GUC()) before the guc call. (D.Gordon)
update huc_version number of format.
v3: rebased to drm-intel-nightly, changed the file name format to
match the one in the huc package.
Changed dev->dev_private to to_i915()
v4: moved function back to where it was.
change wait_for_atomic to wait_for.
v5: rebased. Changed the year in the copyright message to reflect
the right year.Correct the comments,remove the unwanted WARN message,
replace drm_gem_object_unreference() with i915_gem_object_put().Make the
prototypes in intel_huc.h non-extern.
v6: rebased. Update the file construction done by HuC. It is similar to
GuC.Adopted the approach used in-
https://patchwork.freedesktop.org/patch/104355/ 
v7: Change dev to dev_priv in macro definition.
Corrected comments.
v8: rebased on top of drm-tip. Updated functions 
intel_huc_load(),intel_huc_init() and
intel_uc_fw_fetch() to accept dev_priv instead of dev. Moved contents
of intel_huc.h to intel_uc.h
v9: change SKL_FW_ to SKL_HUC_FW_. Add intel_ prefix to guc_wopcm_size().
Remove unwanted checks in intel_uc.h. Rename huc_fw in struct intel_huc to
simply fw to avoid redundency.
v10: rebased. Correct comments. Make intel_huc_fini() accept dev_priv instead 
of dev
like intel_huc_init() and intel_huc_load().Move definition to i915_guc_reg.h 
from
intel_uc.h. Clean DMA_CTRL bits after HuC DMA transfer in huc_ucode_xfer()
instead of guc_ucode_xfer(). Add suitable WARNs to give extra info.
v11: rebased. Add proper bias for HuC and make sure there are
asserts on failure by using guc_ggtt_offset_vma(). Introduce
intel_huc.c and remove intel_huc_loader.c since it has functions that
do more than just loading.Correct year in copyright.
v12: remove invalidates that are not required anymore.

Cc: Arkadiusz Hiler 
Cc: Michal Wajdeczko 
Tested-by: Xiang Haihao 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Alex Dai 
Signed-off-by: Peter Antoine 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/Makefile   |   1 +
 drivers/gpu/drm/i915/i915_drv.c |   3 +
 drivers/gpu/drm/i915/i915_drv.h |   2 +
 drivers/gpu/drm/i915/i915_guc_reg.h |   6 +
 drivers/gpu/drm/i915/intel_guc_loader.c |   7 +-
 drivers/gpu/drm/i915/intel_huc.c| 262 
 drivers/gpu/drm/i915/intel_uc.h |  14 ++
 7 files changed, 292 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_huc.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5196509..1ea051a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -57,6 +57,7 @@ i915-y += i915_cmd_parser.o \
 # general-purpose microcontroller (GuC) support
 i915-y += intel_uc.o \
  intel_guc_loader.o \
+ intel_huc.o \
  i915_guc_submission.o
 
 # autogenerated null render state
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4e5ea58..d7a0b49 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -599,6 +599,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_irq;
 
+   intel_huc_init(dev_priv);
intel_guc_init(dev_priv);
 
ret = i915_gem_init(dev_priv);
@@ -627,6 +628,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
i915_gem_fini(dev_priv);
 cleanup_irq:
intel_guc_fini(dev_priv);
+   intel_huc_fini(dev_priv);
drm_irq_uninstall(dev);
intel_teardown_gmbus(dev_priv);
 cleanup_csr:
@@ -1314,6 +1316,7 @@ void i915_driver_unload(struct drm_device *dev)
drain_workqueue(dev_priv->wq);
 
intel_guc_fini(dev_priv);
+   intel_huc_fini(dev_priv);
i915_gem_fini(dev_priv);
intel_fbc_cleanup_cfb(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f861418..ed845a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2074,6 +2074,7 @@ struct drm_i915_private {
 
struct intel_gvt *gvt;
 
+   struct intel_huc huc;
struct intel_guc guc;
 
struct intel_csr csr;
@@ -2848,6 +2849,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_GUC(dev_priv)  ((dev_priv)->info.has_guc)
 #define HAS_GUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
 #define HAS_GUC_SCHED(dev_priv)(HAS_GUC(dev_priv))
+#define HAS_HUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
 
 #define HAS_RESOURCE_STREAMER(dev_priv) 

[Intel-gfx] [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support

[Anusha Srivatsa]

This patch adds the HuC Loading for the BXT by using
the updated file construction.

Version 1.7 of the HuC firmware.

v2: rebased on to top drm-tip. Rename BXT_FW_MAJOR to BXT_HUC_FW_

Cc: Micha Wajdeczko 
Cc: Tvrtko Ursulin 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Arkadiusz Hiler 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/intel_huc.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 57471f2..8877524 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -40,6 +40,10 @@
  * Note that HuC firmware loading must be done before GuC loading.
  */
 
+#define BXT_HUC_FW_MAJOR 01
+#define BXT_HUC_FW_MINOR 07
+#define BXT_BLD_NUM 1398
+
 #define SKL_HUC_FW_MAJOR 01
 #define SKL_HUC_FW_MINOR 07
 #define SKL_BLD_NUM 1398
@@ -52,6 +56,9 @@
SKL_HUC_FW_MINOR, SKL_BLD_NUM)
 MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
 
+#define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
+   BXT_HUC_FW_MINOR, BXT_BLD_NUM)
+MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
 /**
  * huc_ucode_xfer() - DMA's the firmware
  * @dev_priv: the drm_i915_private device
@@ -154,6 +161,10 @@ void intel_huc_init(struct drm_i915_private *dev_priv)
fw_path = I915_SKL_HUC_UCODE;
huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
+   } else if (IS_BROXTON(dev_priv)) {
+   fw_path = I915_BXT_HUC_UCODE;
+   huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR;
+   huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR;
}
 
huc_fw->path = fw_path;
-- 
2.7.4

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[Intel-gfx] [PATCH 5/8] drm/i915/HuC: Add KBL huC loading Support

[Anusha Srivatsa]

This patch adds the support to load HuC on KBL
Version 2.0

v2: rebased on top of drm-tip. Rename KBL_FW_ to KBL_HUC_FW_
v3: rebased. Remove old checks.

Cc: Michal Wajdeczko 
Cc: Tvrtko Ursulin 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Arkadiusz Hiler 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/intel_huc.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 8877524..8b84ba8 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -48,6 +48,10 @@
 #define SKL_HUC_FW_MINOR 07
 #define SKL_BLD_NUM 1398
 
+#define KBL_HUC_FW_MAJOR 02
+#define KBL_HUC_FW_MINOR 00
+#define KBL_BLD_NUM 1810
+
 #define HUC_FW_PATH(platform, major, minor, bld_num) \
"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
__stringify(minor) "_" __stringify(bld_num) ".bin"
@@ -59,6 +63,11 @@ MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
 #define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
BXT_HUC_FW_MINOR, BXT_BLD_NUM)
 MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
+
+#define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
+   KBL_HUC_FW_MINOR, KBL_BLD_NUM)
+MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
+
 /**
  * huc_ucode_xfer() - DMA's the firmware
  * @dev_priv: the drm_i915_private device
@@ -165,6 +174,10 @@ void intel_huc_init(struct drm_i915_private *dev_priv)
fw_path = I915_BXT_HUC_UCODE;
huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR;
+   } else if (IS_KABYLAKE(dev_priv)) {
+   fw_path = I915_KBL_HUC_UCODE;
+   huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
+   huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
}
 
huc_fw->path = fw_path;
-- 
2.7.4

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[Intel-gfx] [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams

[Anusha Srivatsa]

This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.

v2: removed the forewakes as the registers are already force-woken.
 (T.Ursulin)
v3: rebased on top of drm-tip. Removed any reference to intel_huc.h
v4: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
Remove intel_is_huc_valid() since it is used only in one place.
Put the case of I915_PARAM_HAS_HUC() in the right place.
v5: rebased. Add a comment to specify that I915_READ(reg)
does not read garbage value. The register HUC_STATUS2 is force
woken and no rpm is needed.

Signed-off-by: Anusha Srivatsa 
Signed-off-by: Peter Antoine 
Reviewed-by: Arkadiusz Hiler 
---
 drivers/gpu/drm/i915/i915_drv.c | 7 +++
 include/uapi/drm/i915_drm.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d7a0b49..49a927a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
 #include "i915_trace.h"
 #include "i915_vgpu.h"
 #include "intel_drv.h"
+#include "intel_uc.h"
 
 static struct drm_driver driver;
 
@@ -315,6 +316,12 @@ static int i915_getparam(struct drm_device *dev, void 
*data,
case I915_PARAM_MIN_EU_IN_POOL:
value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
break;
+   case I915_PARAM_HUC_STATUS:
+   /* The register is already force-woken. We dont need
+* any rpm here
+*/
+   value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
+   break;
case I915_PARAM_MMAP_GTT_VERSION:
/* Though we've started our numbering from 1, and so class all
 * earlier versions as 0, in effect their value is undefined as
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index da32c2f..57093b4 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait {
  * priorities and the driver will attempt to execute batches in priority order.
  */
 #define I915_PARAM_HAS_SCHEDULER41
+#define I915_PARAM_HUC_STATUS   42
 
 typedef struct drm_i915_getparam {
__s32 param;
-- 
2.7.4

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[Intel-gfx] [PATCH 6/8] drm/i915/huc: Add debugfs for HuC loading status check

[Anusha Srivatsa]

Add debugfs entry for HuC loading status check.

v2: rebased on top of drm-tip.

Cc: Michal wajdeczko 
Tested-by: Xiang Haihao 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Alex Dai 
Signed-off-by: Peter Antoine 
Reviewed-by: Jeff McGee 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 8ca8423..5829fb4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2352,6 +2352,36 @@ static int i915_llc(struct seq_file *m, void *data)
return 0;
 }
 
+static int i915_huc_load_status_info(struct seq_file *m, void *data)
+{
+   struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   struct intel_uc_fw *huc_fw = _priv->huc.fw;
+
+   if (!HAS_HUC_UCODE(dev_priv))
+   return 0;
+
+   seq_puts(m, "HuC firmware status:\n");
+   seq_printf(m, "\tpath: %s\n", huc_fw->path);
+   seq_printf(m, "\tfetch: %s\n",
+   intel_uc_fw_status_repr(huc_fw->fetch_status));
+   seq_printf(m, "\tload: %s\n",
+   intel_uc_fw_status_repr(huc_fw->load_status));
+   seq_printf(m, "\tversion wanted: %d.%d\n",
+   huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
+   seq_printf(m, "\tversion found: %d.%d\n",
+   huc_fw->major_ver_found, huc_fw->minor_ver_found);
+   seq_printf(m, "\theader: offset is %d; size = %d\n",
+   huc_fw->header_offset, huc_fw->header_size);
+   seq_printf(m, "\tuCode: offset is %d; size = %d\n",
+   huc_fw->ucode_offset, huc_fw->ucode_size);
+   seq_printf(m, "\tRSA: offset is %d; size = %d\n",
+   huc_fw->rsa_offset, huc_fw->rsa_size);
+
+   seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
+
+   return 0;
+}
+
 static int i915_guc_load_status_info(struct seq_file *m, void *data)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4580,6 +4610,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_guc_info", i915_guc_info, 0},
{"i915_guc_load_status", i915_guc_load_status_info, 0},
{"i915_guc_log_dump", i915_guc_log_dump, 0},
+   {"i915_huc_load_status", i915_huc_load_status_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
{"i915_drpc_info", i915_drpc_info, 0},
-- 
2.7.4

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[Intel-gfx] [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general

[Anusha Srivatsa]

Rename some of the GuC fw loading code to make them more general. We
will utilise them for HuC loading as well.
 s/intel_guc_fw/intel_uc_fw/g
 s/GUC_FIRMWARE/INTEL_UC_FIRMWARE/g

Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
same purpose.

v2: rebased on top of nightly.
reapplied the search/replace as upstream code as changed.
v3: removed G from messages in shared fw fetch function.
v4: rebased.Updated dev to dev_priv in intel_guc_setup(), guc_fw_getch()
and intel_guc_init().
v5: rebased. Remove uint32_t fw_type to patch 2. Add INTEL_ prefix for
fields in enum intel_uc_fw_status. Remove uc_dev field since its never
used.Rename uc_fw to just fw and guc_fw to fw to avoid redundency.
v6: rebased. Remove sections of code that were commented and no longer
required.
v7: rebased. Remove uc_fw_ prefix from path and obj fields
in intel_uc_fw struct as suggested by Michal.
v8: rebased. Add declaration of intel_guc_wopcm_size() in
this patch instead of patch 3.

Cc: Michal Wajdeczko 
Cc: Arkadiusz Hiler 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Alex Dai 
Signed-off-by: Peter Antoine 
Reviewed-by: Arkadiusz Hiler 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_debugfs.c|  12 +--
 drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
 drivers/gpu/drm/i915/intel_guc_loader.c| 156 ++---
 drivers/gpu/drm/i915/intel_uc.h|  37 +++
 4 files changed, 105 insertions(+), 104 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index e367f06..8ca8423 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2355,7 +2355,7 @@ static int i915_llc(struct seq_file *m, void *data)
 static int i915_guc_load_status_info(struct seq_file *m, void *data)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct intel_guc_fw *guc_fw = _priv->guc.guc_fw;
+   struct intel_uc_fw *guc_fw = _priv->guc.fw;
u32 tmp, i;
 
if (!HAS_GUC_UCODE(dev_priv))
@@ -2363,15 +2363,15 @@ static int i915_guc_load_status_info(struct seq_file 
*m, void *data)
 
seq_printf(m, "GuC firmware status:\n");
seq_printf(m, "\tpath: %s\n",
-   guc_fw->guc_fw_path);
+   guc_fw->path);
seq_printf(m, "\tfetch: %s\n",
-   intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+   intel_uc_fw_status_repr(guc_fw->fetch_status));
seq_printf(m, "\tload: %s\n",
-   intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+   intel_uc_fw_status_repr(guc_fw->load_status));
seq_printf(m, "\tversion wanted: %d.%d\n",
-   guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+   guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
seq_printf(m, "\tversion found: %d.%d\n",
-   guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
+   guc_fw->major_ver_found, guc_fw->minor_ver_found);
seq_printf(m, "\theader: offset is %d; size = %d\n",
guc_fw->header_offset, guc_fw->header_size);
seq_printf(m, "\tuCode: offset is %d; size = %d\n",
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 913d873..bb7cf95 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1481,7 +1481,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
struct i915_gem_context *ctx;
u32 data[3];
 
-   if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
gen9_disable_guc_interrupts(dev_priv);
@@ -1508,7 +1508,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
struct i915_gem_context *ctx;
u32 data[3];
 
-   if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
if (i915.guc_log_level >= 0)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index b889191..5a2c86f 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
 MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
 
 /* User-friendly representation of an enum */
-const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
+const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
 {
switch (status) {
-   case GUC_FIRMWARE_FAIL:
+   case 

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/7] drm/i915: Name the anonymous structs inside i915_ggtt_view

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/7] drm/i915: Name the anonymous structs 
inside i915_ggtt_view
URL   : https://patchwork.freedesktop.org/series/18006/
State : success

== Summary ==

Series 18006v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/18006/revisions/1/mbox/


fi-bdw-5557u total:246  pass:232  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050 total:246  pass:207  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:246  pass:224  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-t5700 total:82   pass:69   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:246  pass:219  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-ivb-3520m total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770  total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6260u total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hqtotal:246  pass:226  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k total:246  pass:222  dwarn:3   dfail:0   fail:0   skip:21 
fi-skl-6770hqtotal:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2520m total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-snb-2600  total:246  pass:214  dwarn:0   dfail:0   fail:0   skip:32 

a957dfe613ab43c6af84833f2b88ea941320250f drm-tip: 2017y-01m-13d-18h-49m-04s UTC 
integration manifest
3a576ad drm/i915: Eliminate superfluous i915_ggtt_view_normal
2982533 drm/i915: Eliminate superfluous i915_ggtt_view_rotated
067f3f3 drm/i915: Convert i915_ggtt_view to use an anonymous union
3b0cf64 drm/i915: Stop clearing i915_ggtt_view
7d12c51 drm/i915: Compact memcmp in i915_vma_compare()
4cb8a27 drm/i915: Mark the ggtt_view structs as packed
5f20d78 drm/i915: Name the anonymous structs inside i915_ggtt_view

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3517/
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[Intel-gfx] [CI 4/7] drm/i915: Stop clearing i915_ggtt_view

[Chris Wilson]

As we now use a compact memcmp in i915_vma_compare(), we can forgo
clearing the entire view and only set the precise parameters used in
this view.

Signed-off-by: Chris Wilson 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gem.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3bf517e2430a..f034d8d2dd4c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1759,7 +1759,6 @@ compute_partial_view(struct drm_i915_gem_object *obj,
if (i915_gem_object_is_tiled(obj))
chunk = roundup(chunk, tile_row_pages(obj));
 
-   memset(, 0, sizeof(view));
view.type = I915_GGTT_VIEW_PARTIAL;
view.params.partial.offset = rounddown(page_offset, chunk);
view.params.partial.size =
-- 
2.11.0

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[Intel-gfx] [CI 7/7] drm/i915: Eliminate superfluous i915_ggtt_view_normal

[Chris Wilson]

Since commit 058d88c4330f ("drm/i915: Track pinned VMA"), there is only
one user of i915_ggtt_view_normal rodate. Just treat NULL as no special
view in pin_to_display() like everywhere else.

Signed-off-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem.c  | 2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c  | 4 
 drivers/gpu/drm/i915/i915_gem_gtt.h  | 2 --
 drivers/gpu/drm/i915/intel_overlay.c | 3 +--
 4 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d8622fd23f5d..d4c59b53532e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3436,7 +3436,7 @@ i915_gem_object_pin_to_display_plane(struct 
drm_i915_gem_object *obj,
 * try to preserve the existing ABI).
 */
vma = ERR_PTR(-ENOSPC);
-   if (view->type == I915_GGTT_VIEW_NORMAL)
+   if (!view || view->type == I915_GGTT_VIEW_NORMAL)
vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
   PIN_MAPPABLE | PIN_NONBLOCK);
if (IS_ERR(vma)) {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 169d10d81334..4c88745b6078 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -103,10 +103,6 @@
 static int
 i915_get_ggtt_vma_pages(struct i915_vma *vma);
 
-const struct i915_ggtt_view i915_ggtt_view_normal = {
-   .type = I915_GGTT_VIEW_NORMAL,
-};
-
 static void gen6_ggtt_invalidate(struct drm_i915_private *dev_priv)
 {
/* Note that as an uncached mmio write, this should flush the
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index f673544e570e..3c5ef5358cef 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -196,8 +196,6 @@ struct i915_ggtt_view {
};
 };
 
-extern const struct i915_ggtt_view i915_ggtt_view_normal;
-
 enum i915_cache_level;
 
 struct i915_vma;
diff --git a/drivers/gpu/drm/i915/intel_overlay.c 
b/drivers/gpu/drm/i915/intel_overlay.c
index 4473a611c664..0608fad7f593 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -811,8 +811,7 @@ static int intel_overlay_do_put_image(struct intel_overlay 
*overlay,
if (ret != 0)
return ret;
 
-   vma = i915_gem_object_pin_to_display_plane(new_bo, 0,
-  _ggtt_view_normal);
+   vma = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL);
if (IS_ERR(vma))
return PTR_ERR(vma);
 
-- 
2.11.0

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[Intel-gfx] [CI 2/7] drm/i915: Mark the ggtt_view structs as packed

[Chris Wilson]

In the next few patches, we will depend upon there being no
uninitialised bits inside the ggtt_view. To ensure this we add the
__packed attribute and double check with a build bug that gcc hasn't
expanded the struct to include some padding bytes.

Signed-off-by: Chris Wilson 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gem_gtt.h | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 80f0cd534db6..334b61b84376 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -156,12 +156,22 @@ struct intel_rotation_info {
/* tiles */
unsigned int width, height, stride, offset;
} plane[2];
-};
+} __packed;
+
+static inline void assert_intel_rotation_info_is_packed(void)
+{
+   BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned 
int));
+}
 
 struct intel_partial_info {
u64 offset;
unsigned int size;
-};
+} __packed;
+
+static inline void assert_intel_partial_info_is_packed(void)
+{
+   BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + 
sizeof(unsigned int));
+}
 
 struct i915_ggtt_view {
enum i915_ggtt_view_type type;
-- 
2.11.0

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[Intel-gfx] [CI 5/7] drm/i915: Convert i915_ggtt_view to use an anonymous union

[Chris Wilson]

Reading the ggtt_views is much more pleasant without the extra
characters from specifying the union (i.e. ggtt_view.partial rather than
ggtt_view.params.partial). To make this work inside i915_vma_compare()
with only a single memcmp requires us to ensure that there are no
uninitialised bytes within each branch of the union (we make sure the
structs are packed) and we need to store the size of each branch.

v4: Rewrite changelog and add comments explaining the assert.

Signed-off-by: Chris Wilson 
Cc: Daniel Vetter 
---
 drivers/gpu/drm/i915/i915_debugfs.c  | 20 ++--
 drivers/gpu/drm/i915/i915_gem.c  |  8 
 drivers/gpu/drm/i915/i915_gem_gtt.c  |  9 -
 drivers/gpu/drm/i915/i915_gem_gtt.h  |  2 +-
 drivers/gpu/drm/i915/i915_vma.c  |  9 -
 drivers/gpu/drm/i915/i915_vma.h  |  9 -
 drivers/gpu/drm/i915/intel_display.c |  2 +-
 7 files changed, 32 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 32ede342ab94..01fdbbf0fd43 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -167,20 +167,20 @@ describe_obj(struct seq_file *m, struct 
drm_i915_gem_object *obj)
 
case I915_GGTT_VIEW_PARTIAL:
seq_printf(m, ", partial [%08llx+%x]",
-  vma->ggtt_view.params.partial.offset 
<< PAGE_SHIFT,
-  vma->ggtt_view.params.partial.size 
<< PAGE_SHIFT);
+  vma->ggtt_view.partial.offset << 
PAGE_SHIFT,
+  vma->ggtt_view.partial.size << 
PAGE_SHIFT);
break;
 
case I915_GGTT_VIEW_ROTATED:
seq_printf(m, ", rotated [(%ux%u, stride=%u, 
offset=%u), (%ux%u, stride=%u, offset=%u)]",
-  
vma->ggtt_view.params.rotated.plane[0].width,
-  
vma->ggtt_view.params.rotated.plane[0].height,
-  
vma->ggtt_view.params.rotated.plane[0].stride,
-  
vma->ggtt_view.params.rotated.plane[0].offset,
-  
vma->ggtt_view.params.rotated.plane[1].width,
-  
vma->ggtt_view.params.rotated.plane[1].height,
-  
vma->ggtt_view.params.rotated.plane[1].stride,
-  
vma->ggtt_view.params.rotated.plane[1].offset);
+  
vma->ggtt_view.rotated.plane[0].width,
+  
vma->ggtt_view.rotated.plane[0].height,
+  
vma->ggtt_view.rotated.plane[0].stride,
+  
vma->ggtt_view.rotated.plane[0].offset,
+  
vma->ggtt_view.rotated.plane[1].width,
+  
vma->ggtt_view.rotated.plane[1].height,
+  
vma->ggtt_view.rotated.plane[1].stride,
+  
vma->ggtt_view.rotated.plane[1].offset);
break;
 
default:
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f034d8d2dd4c..d8622fd23f5d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1760,10 +1760,10 @@ compute_partial_view(struct drm_i915_gem_object *obj,
chunk = roundup(chunk, tile_row_pages(obj));
 
view.type = I915_GGTT_VIEW_PARTIAL;
-   view.params.partial.offset = rounddown(page_offset, chunk);
-   view.params.partial.size =
+   view.partial.offset = rounddown(page_offset, chunk);
+   view.partial.size =
min_t(unsigned int, chunk,
- (obj->base.size >> PAGE_SHIFT) - 
view.params.partial.offset);
+ (obj->base.size >> PAGE_SHIFT) - view.partial.offset);
 
/* If the partial covers the entire object, just create a normal VMA. */
if (chunk >= obj->base.size >> PAGE_SHIFT)
@@ -1879,7 +1879,7 @@ int i915_gem_fault(struct vm_area_struct *area, struct 
vm_fault *vmf)
 
/* Finally, remap it using the new GTT offset */
ret = remap_io_mapping(area,
-  area->vm_start + 
(vma->ggtt_view.params.partial.offset << PAGE_SHIFT),
+  area->vm_start + (vma->ggtt_view.partial.offset 
<< PAGE_SHIFT),
   (ggtt->mappable_base + vma->node.start) >> 
PAGE_SHIFT,
   min_t(u64, vma->size, area->vm_end - 
area->vm_start),
   >mappable);
diff 

[Intel-gfx] [CI 6/7] drm/i915: Eliminate superfluous i915_ggtt_view_rotated

[Chris Wilson]

It is only being used to clear a struct and set the type, after which it
is overwritten. Since we no longer check the unset bits of the union,
skipping the clear is permissible.

Signed-off-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c  | 3 ---
 drivers/gpu/drm/i915/i915_gem_gtt.h  | 1 -
 drivers/gpu/drm/i915/intel_display.c | 5 ++---
 3 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e24b961c30c6..169d10d81334 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -106,9 +106,6 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma);
 const struct i915_ggtt_view i915_ggtt_view_normal = {
.type = I915_GGTT_VIEW_NORMAL,
 };
-const struct i915_ggtt_view i915_ggtt_view_rotated = {
-   .type = I915_GGTT_VIEW_ROTATED,
-};
 
 static void gen6_ggtt_invalidate(struct drm_i915_private *dev_priv)
 {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 71e7e0a7e2b6..f673544e570e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -197,7 +197,6 @@ struct i915_ggtt_view {
 };
 
 extern const struct i915_ggtt_view i915_ggtt_view_normal;
-extern const struct i915_ggtt_view i915_ggtt_view_rotated;
 
 enum i915_cache_level;
 
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index f4be20f0198a..f523256ef77c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2137,11 +2137,10 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
const struct drm_framebuffer *fb,
unsigned int rotation)
 {
+   view->type = I915_GGTT_VIEW_NORMAL;
if (drm_rotation_90_or_270(rotation)) {
-   *view = i915_ggtt_view_rotated;
+   view->type = I915_GGTT_VIEW_ROTATED;
view->rotated = to_intel_framebuffer(fb)->rot_info;
-   } else {
-   *view = i915_ggtt_view_normal;
}
 }
 
-- 
2.11.0

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[Intel-gfx] [CI 3/7] drm/i915: Compact memcmp in i915_vma_compare()

[Chris Wilson]

In preparation for the next patch to convert to using an anonymous union
and leaving the excess bytes in the union uninitialised, we first need
to make sure we do not compare using those uninitialised bytes. We also
want to preserve the compactness of the code, avoiding a second call to
memcmp or introducing a switch, so we take advantage of using the type
as an encoded size (as well as a unique identifier for each type of view).

v2: Add the rationale for why we encode size into ggtt_view.type as a
comment before the memcmp()
v3: Use a switch to also assert that no two i915_ggtt_view_type have the same
value.

Signed-off-by: Chris Wilson 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gem_gtt.h | 28 +---
 drivers/gpu/drm/i915/i915_vma.h | 20 ++--
 2 files changed, 35 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 334b61b84376..35ea4a18dc77 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -145,12 +145,6 @@ typedef uint64_t gen8_ppgtt_pml4e_t;
 
 struct sg_table;
 
-enum i915_ggtt_view_type {
-   I915_GGTT_VIEW_NORMAL = 0,
-   I915_GGTT_VIEW_ROTATED,
-   I915_GGTT_VIEW_PARTIAL,
-};
-
 struct intel_rotation_info {
struct intel_rotation_plane_info {
/* tiles */
@@ -173,10 +167,30 @@ static inline void 
assert_intel_partial_info_is_packed(void)
BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + 
sizeof(unsigned int));
 }
 
+enum i915_ggtt_view_type {
+   I915_GGTT_VIEW_NORMAL = 0,
+   I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),
+   I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info),
+};
+
+static inline void assert_i915_ggtt_view_type_is_unique(void)
+{
+   /* As we encode the size of each branch inside the union into its type,
+* we have to be careful that each branch has a unique size.
+*/
+   switch ((enum i915_ggtt_view_type)0) {
+   case I915_GGTT_VIEW_NORMAL:
+   case I915_GGTT_VIEW_PARTIAL:
+   case I915_GGTT_VIEW_ROTATED:
+   /* gcc complains if these are identical cases */
+   break;
+   }
+}
+
 struct i915_ggtt_view {
enum i915_ggtt_view_type type;
-
union {
+   /* Members need to contain no holes/padding */
struct intel_partial_info partial;
struct intel_rotation_info rotated;
} params;
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 008cf115f38f..fdbacc036080 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -199,15 +199,23 @@ i915_vma_compare(struct i915_vma *vma,
if (cmp)
return cmp;
 
+   BUILD_BUG_ON(I915_GGTT_VIEW_NORMAL != 0);
+   cmp = vma->ggtt_view.type;
if (!view)
-   return vma->ggtt_view.type;
+   return cmp;
 
-   if (vma->ggtt_view.type != view->type)
-   return vma->ggtt_view.type - view->type;
+   cmp -= view->type;
+   if (cmp)
+   return cmp;
 
-   return memcmp(>ggtt_view.params,
- >params,
- sizeof(view->params));
+   /* ggtt_view.type also encodes its size so that we both distinguish
+* different views using it as a "type" and also use a compact (no
+* accessing of uninitialised padding bytes) memcmp without storing
+* an extra parameter or adding more code.
+*/
+   BUILD_BUG_ON(I915_GGTT_VIEW_NORMAL >= I915_GGTT_VIEW_PARTIAL);
+   BUILD_BUG_ON(I915_GGTT_VIEW_PARTIAL >= I915_GGTT_VIEW_ROTATED);
+   return memcmp(>ggtt_view.params, >params, view->type);
 }
 
 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
-- 
2.11.0

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[Intel-gfx] [CI 1/7] drm/i915: Name the anonymous structs inside i915_ggtt_view

[Chris Wilson]

Naming this pair will become useful shortly...

Signed-off-by: Chris Wilson 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gem_gtt.h | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 9f04c9febe4d..80f0cd534db6 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -152,20 +152,22 @@ enum i915_ggtt_view_type {
 };
 
 struct intel_rotation_info {
-   struct {
+   struct intel_rotation_plane_info {
/* tiles */
unsigned int width, height, stride, offset;
} plane[2];
 };
 
+struct intel_partial_info {
+   u64 offset;
+   unsigned int size;
+};
+
 struct i915_ggtt_view {
enum i915_ggtt_view_type type;
 
union {
-   struct {
-   u64 offset;
-   unsigned int size;
-   } partial;
+   struct intel_partial_info partial;
struct intel_rotation_info rotated;
} params;
 };
-- 
2.11.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for lib/prime_numbers: Suppress warn on kmalloc failure

[Patchwork]

== Series Details ==

Series: lib/prime_numbers: Suppress warn on kmalloc failure
URL   : https://patchwork.freedesktop.org/series/18004/
State : success

== Summary ==

Series 18004v1 lib/prime_numbers: Suppress warn on kmalloc failure
https://patchwork.freedesktop.org/api/1.0/series/18004/revisions/1/mbox/


fi-bdw-5557u total:246  pass:232  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050 total:246  pass:207  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:246  pass:224  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-t5700 total:82   pass:69   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:246  pass:219  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-ivb-3520m total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770  total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6260u total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hqtotal:246  pass:226  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k total:246  pass:222  dwarn:3   dfail:0   fail:0   skip:21 
fi-skl-6770hqtotal:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2520m total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-snb-2600  total:246  pass:214  dwarn:0   dfail:0   fail:0   skip:32 

a957dfe613ab43c6af84833f2b88ea941320250f drm-tip: 2017y-01m-13d-18h-49m-04s UTC 
integration manifest
7b4105e lib/prime_numbers: Suppress warn on kmalloc failure

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3516/
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[Intel-gfx] [PATCH] lib/prime_numbers: Suppress warn on kmalloc failure

[Chris Wilson]

The allocation for the bitmap may become very large, larger than
MAX_ORDER, for large requests. We fail gracefully by falling back to
trail-division, so disable the warning from kmalloc:

  521.961092] WARNING: CPU: 0 PID: 30637 at mm/page_alloc.c:3548 
__alloc_pages_slowpath+0x237/0x9a0
[  521.961105] Modules linked in: i915(+) drm_kms_helper intel_gtt 
prime_numbers [last unloaded: drm_kms_helper]
[  521.961126] CPU: 0 PID: 30637 Comm: drv_selftest Tainted: G U  W   
4.10.0-rc3+ #321
[  521.961137] Hardware name:  /, BIOS 
PYBSWCEL.86A.0027.2015.0507.1758 05/07/2015
[  521.961148] Call Trace:
[  521.961161]  dump_stack+0x4d/0x6f
[  521.961172]  __warn+0xc1/0xe0
[  521.961181]  warn_slowpath_null+0x18/0x20
[  521.961189]  __alloc_pages_slowpath+0x237/0x9a0
[  521.961200]  ? sg_init_table+0x1a/0x40
[  521.961208]  ? get_page_from_freelist+0x3fa/0x910
[  521.961275]  ? i915_gem_object_get_sg+0x272/0x2b0 [i915]
[  521.961285]  __alloc_pages_nodemask+0x1ea/0x220
[  521.961295]  kmalloc_order+0x1c/0x50
[  521.961304]  __kmalloc+0x115/0x170
[  521.961314]  expand_to_next_prime+0x43/0x180 [prime_numbers]
[  521.961324]  next_prime_number+0x47/0xc0 [prime_numbers]
[  521.961377]  igt_vma_rotate+0x386/0x590 [i915]
[  521.961429]  i915_subtests+0x37/0xc0 [i915]
[  521.961481]  i915_vma_mock_selftests+0x3d/0x70 [i915]
[  521.961532]  run_selftests+0x16e/0x1f0 [i915]
[  521.961541]  ? 0xa02a4000
[  521.961592]  i915_mock_selftests+0x29/0x40 [i915]
[  521.961638]  i915_init+0xa/0x5e [i915]
[  521.961646]  ? 0xa02a4000
[  521.961655]  do_one_initcall+0x3e/0x160
[  521.961664]  ? __vunmap+0x7c/0xc0
[  521.961672]  ? vfree+0x29/0x70
[  521.961680]  ? kmem_cache_alloc+0xcf/0x120
[  521.961690]  do_init_module+0x55/0x1c4
[  521.961699]  load_module+0x1f3f/0x25b0
[  521.961707]  ? __symbol_put+0x40/0x40
[  521.961716]  ? kernel_read_file+0x100/0x190
[  521.961725]  SYSC_finit_module+0xbc/0xf0
[  521.961734]  SyS_finit_module+0x9/0x10
[  521.961744]  entry_SYSCALL_64_fastpath+0x17/0x98
[  521.961752] RIP: 0033:0x7f111aca4119
[  521.961760] RSP: 002b:7ffd8be6cbe8 EFLAGS: 0246 ORIG_RAX: 
0139
[  521.961773] RAX: ffda RBX: 0006 RCX: 7f111aca4119
[  521.961781] RDX:  RSI: 55dfc18bc8e0 RDI: 0006
[  521.961789] RBP: 7ffd8be6bbe0 R08:  R09: 
[  521.961796] R10: 0006 R11: 0246 R12: 0005
[  521.961805] R13: 55dfc18bd3a0 R14: 7ffd8be6bbc0 R15: 0005

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Daniel Vetter 
---
 lib/prime_numbers.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/lib/prime_numbers.c b/lib/prime_numbers.c
index c9b3c29614aa..550eec457c2e 100644
--- a/lib/prime_numbers.c
+++ b/lib/prime_numbers.c
@@ -124,7 +124,8 @@ static bool expand_to_next_prime(unsigned long x)
return false;
 
sz = round_up(sz, BITS_PER_LONG);
-   new = kmalloc(sizeof(*new) + bitmap_size(sz), GFP_KERNEL);
+   new = kmalloc(sizeof(*new) + bitmap_size(sz),
+ GFP_KERNEL | __GFP_NOWARN);
if (!new)
return false;
 
-- 
2.11.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Flush the change in debugobject before reallocation

[Patchwork]

== Series Details ==

Series: drm/i915: Flush the change in debugobject before reallocation
URL   : https://patchwork.freedesktop.org/series/17999/
State : success

== Summary ==

Series 17999v1 drm/i915: Flush the change in debugobject before reallocation
https://patchwork.freedesktop.org/api/1.0/series/17999/revisions/1/mbox/


fi-bdw-5557u total:246  pass:232  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050 total:246  pass:207  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:246  pass:224  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-t5700 total:82   pass:69   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:246  pass:219  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-ivb-3520m total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770  total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6260u total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hqtotal:246  pass:226  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k total:246  pass:222  dwarn:3   dfail:0   fail:0   skip:21 
fi-skl-6770hqtotal:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2520m total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-snb-2600  total:246  pass:214  dwarn:0   dfail:0   fail:0   skip:32 

a957dfe613ab43c6af84833f2b88ea941320250f drm-tip: 2017y-01m-13d-18h-49m-04s UTC 
integration manifest
36722f5 drm/i915: Flush the change in debugobject before reallocation

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3515/
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Re: [Intel-gfx] [PATCH v4] lib/scatterlist: Avoid potential scatterlist entry overflow

[Andy Shevchenko]

>>> @@ -402,9 +403,16 @@ int sg_alloc_table_from_pages(struct sg_table *sgt,
>>>
>>> /* compute number of contiguous chunks */
>>> chunks = 1;
>>> -   for (i = 1; i < n_pages; ++i)
>>> -   if (page_to_pfn(pages[i]) != page_to_pfn(pages[i - 1]) +
>>> 1)
>>> +   seg_len = PAGE_SIZE;
>>> +   for (i = 1; i < n_pages; ++i) {
>>> +   if (seg_len >= max_segment ||
>>> +   page_to_pfn(pages[i]) != page_to_pfn(pages[i - 1]) +
>>> 1) {
>>> ++chunks;
>>> +   seg_len = PAGE_SIZE;
>>> +   } else {
>>> +   seg_len += PAGE_SIZE;
>>> +   }
>>> +   }
>>
>>
>> Wouldn't be following looks more readable?
>>
>> seg_len = 0;
>> // Are compilers so stupid doing calculation per iteration in
>> for-conditional?
>> // for (i = 0; i + 1 < n_pages; i++) ?
>
>
> I didn't get what you meant here?

Why do we start from 1? I see here two micro (?) optimizations:
1) starting from 1 on believe that compiler dumb enough to every time
do a calculation in condition;
2) ++i instead of i++, but this is just matter of style, it's not a c++.

>> for (i = 1; i < n_pages; ++i) {
>>   seg_len += PAGE_SIZE;
>>   if (seg_len >= max_segment || page_to_pfn(pages[i]) !=
>> page_to_pfn(pages[i - 1]) + 1) {
>> ++chunks;
>> seg_len = PAGE_SIZE;
>>   }
>> }
>
>
> Tried it in my unit tester but it doesn't work for all scenarios, guess
> there is a subtle bug somewhere. I don't find it that unreadable so would
> prefer to leave it since it works.

Last seems has to be
seg_len = 0;

-- 
With Best Regards,
Andy Shevchenko
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[Intel-gfx] [PATCH] drm/i915: Flush the change in debugobject before reallocation

[Chris Wilson]

When marking the debugobject as freed, be sure that write is flushed
before another CPU may see it on a reallocation path.

Only seen once in CI:

[  159.240873] WARNING: CPU: 3 PID: 6735 at lib/debugobjects.c:263 
debug_print_object+0x87/0xb0
[  159.240897] ODEBUG: init destroyed (active state 0) object type: 
i915_sw_fence hint: submit_notify+0x0/0x4c [i915]
[  159.240902] Modules linked in: snd_hda_intel i915 x86_pkg_temp_thermal 
intel_powerclamp coretemp crct10dif_pclmul snd_hda_codec_realtek crc32_pclmul 
snd_hda_codec_generic snd_hda_codec_hdmi ghash_clmulni_intel snd_hda_codec 
snd_hwdep snd_hda_core snd_pcm mei_me lpc_ich mei e1000e ptp pps_core [last 
unloaded: i915]
[  159.240913] CPU: 3 PID: 6735 Comm: gem_exec_nop Tainted: G U  
4.10.0-rc3-CI-Trybot_479+ #1
[  159.240913] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS FBKT34AUS 
04/24/2013
[  159.240914] Call Trace:
[  159.240916]  dump_stack+0x67/0x92
[  159.240919]  __warn+0xc6/0xe0
[  159.240920]  warn_slowpath_fmt+0x4a/0x50
[  159.240921]  debug_print_object+0x87/0xb0
[  159.240935]  ? __i915_request_wait_for_execute+0x1d0/0x1d0 [i915]
[  159.240936]  __debug_object_init+0xb2/0x410
[  159.240950]  ? __i915_request_wait_for_execute+0x1d0/0x1d0 [i915]
[  159.240951]  debug_object_init+0x16/0x20
[  159.240962]  __i915_sw_fence_init+0x29/0x60 [i915]
[  159.240975]  i915_gem_request_alloc+0x1fb/0x450 [i915]
[  159.240987]  i915_gem_do_execbuffer.isra.15+0x798/0x1b20 [i915]
[  159.241000]  i915_gem_execbuffer2+0xc0/0x250 [i915]
[  159.241003]  drm_ioctl+0x200/0x450
[  159.241016]  ? i915_gem_execbuffer+0x330/0x330 [i915]
[  159.241018]  do_vfs_ioctl+0x90/0x6e0
[  159.241020]  ? trace_hardirqs_on_caller+0x122/0x1b0
[  159.241021]  SyS_ioctl+0x3c/0x70
[  159.241023]  entry_SYSCALL_64_fastpath+0x1c/0xb1
[  159.241024] RIP: 0033:0x7f9bc4f41357
[  159.241025] RSP: 002b:7ffc6cd5c568 EFLAGS: 0246 ORIG_RAX: 
0010
[  159.241026] RAX: ffda RBX:  RCX: 7f9bc4f41357
[  159.241026] RDX: 7ffc6cd5c640 RSI: 40406469 RDI: 0003
[  159.241027] RBP: 7ffc6cd5c640 R08: 00047508 R09: 0001
[  159.241027] R10: 000b58552d323c3d R11: 0246 R12: 40406469
[  159.241028] R13: 0003 R14: 0004 R15: 0001

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_sw_fence.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c 
b/drivers/gpu/drm/i915/i915_sw_fence.c
index f5a88092dacf..40f4e5efaf83 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -63,6 +63,7 @@ static inline void debug_fence_destroy(struct i915_sw_fence 
*fence)
 static inline void debug_fence_free(struct i915_sw_fence *fence)
 {
debug_object_free(fence, _sw_fence_debug_descr);
+   smp_wmb(); /* flush the change in state before reallocation */
 }
 
 static inline void debug_fence_assert(struct i915_sw_fence *fence)
-- 
2.11.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Only call skl_check_plane_surface() for visible planes (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Only call skl_check_plane_surface() for visible planes (rev2)
URL   : https://patchwork.freedesktop.org/series/17996/
State : success

== Summary ==

Series 17996v2 drm/i915: Only call skl_check_plane_surface() for visible planes
https://patchwork.freedesktop.org/api/1.0/series/17996/revisions/2/mbox/


fi-bdw-5557u total:246  pass:232  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050 total:246  pass:207  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:246  pass:224  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-t5700 total:82   pass:69   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:246  pass:219  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-ivb-3520m total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770  total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6260u total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hqtotal:246  pass:226  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k total:246  pass:222  dwarn:3   dfail:0   fail:0   skip:21 
fi-skl-6770hqtotal:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2520m total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-snb-2600  total:246  pass:214  dwarn:0   dfail:0   fail:0   skip:32 

a957dfe613ab43c6af84833f2b88ea941320250f drm-tip: 2017y-01m-13d-18h-49m-04s UTC 
integration manifest
daf8ca0 drm/i915: Only call skl_check_plane_surface() for visible planes (v2)

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3514/
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Re: [Intel-gfx] [PATCH 29/37] drm/i915: Fill different pages of the GTT

[Chris Wilson]

On Fri, Jan 13, 2017 at 09:47:08AM +0200, Joonas Lahtinen wrote:
> On ke, 2017-01-11 at 21:09 +, Chris Wilson wrote:
> > +
> > +   mutex_lock(>drm.struct_mutex);
> > +   drm_mm_for_each_hole(node, >base.mm, this_start, this_end) {
> > +   u64 this_size;
> > +
> > +   if (ggtt->base.mm.color_adjust)
> > +   ggtt->base. mm.color_adjust(node, 0,
> > +   _start, _end);
> > +
> > +   this_size = this_end - this_start;
> > +   if (this_size > hole_size) {
> > +   hole_size = this_size;
> > +   hole_start = this_start;
> > +   hole_end = this_end;
> > +   }
> > +   }
> > +   pr_info("Found GGTT hole [%llx, %llx], size %llx\n",
> > +   hole_start, hole_end, hole_size);
> > +   GEM_BUG_ON(hole_start >= hole_end);
> > +
> 
> Why not just walk all the holes big enough to accommodate GTT_PAGE_SIZE
> for better coverage? But for just one hole, with above;

My interest in test was focused on what happens at the edges. The test
tries to put objects of different sizes next to the edge, and see if we
overstepped in the PTE insertion. Looking at the object next below that
was to try and hit different pagetable boundaries, as the pattern is
slightly different to the earlier tests. In particular I'm trying to
reproduce the NULL pointer dereferences seen in gen8_ppgtt_insert_pte and
gen6_ppgtt_insert_pte, but unsucessfully so far.

Anyway, in regards to this test I was looking for multiple pages, but
that is no reason not to use all holes and just timeout.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] [PATCH] drm/i915: Only call skl_check_plane_surface() for visible planes (v2)

[Matt Roper]

When a plane is fully clipped (either because it's positioned offscreen,
or because the CRTC is currently off), the clipping calculations we do
during check_plane will leave nonsense/negative coordinates in plane's
source rectangle.  This is generally harmless since we recognize that
the plane should be turned off and we don't try to actually do anything
with those values.  However on gen9 platforms, we still try to do
surface offset math in skl_check_plane_surface() which gets confused and
reports "Unable to find suitable display surface offset."  Given that
the plane will be disabled anyway, none of these calculations are
actually necessary, so just skip calling the function on non-visible
planes.

v2: Rebase

Cc: Ville Syrjälä 
Fixes: b63a16f6cd ("drm/i915: Compute display surface offset in the plane check 
hook for SKL+")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98258
Testcase: igt/pm_rpm/legacy-planes
Testcase: igt/pm_rpm/universal-planes
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 drivers/gpu/drm/i915/intel_sprite.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index fd5fbc8..3baba59 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14924,7 +14924,7 @@ intel_check_primary_plane(struct drm_plane *plane,
if (!state->base.fb)
return 0;
 
-   if (INTEL_GEN(dev_priv) >= 9) {
+   if (INTEL_GEN(dev_priv) >= 9 && state->base.visible) {
ret = skl_check_plane_surface(state);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 7031bc7..b7b16a15 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -918,7 +918,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
dst->y1 = crtc_y;
dst->y2 = crtc_y + crtc_h;
 
-   if (INTEL_GEN(dev_priv) >= 9) {
+   if (INTEL_GEN(dev_priv) >= 9 && state->base.visible) {
ret = skl_check_plane_surface(state);
if (ret)
return ret;
-- 
2.10.2

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[Intel-gfx] [PATCH] drm/i915: Only call skl_check_plane_surface() for visible planes

[Matt Roper]

When a plane is fully clipped (either because it's positioned offscreen,
or because the CRTC is currently off), the clipping calculations we do
during check_plane will leave nonsense/negative coordinates in plane's
source rectangle.  This is generally harmless since we recognize that
the plane should be turned off and we don't try to actually do anything
with those values.  However on gen9 platforms, we still try to do
surface offset math in skl_check_plane_surface() which gets confused and
reports "Unable to find suitable display surface offset."  Given that
the plane will be disabled anyway, none of these calculations are
actually necessary, so just skip calling the function on non-visible
planes.

Cc: Ville Syrjälä 
Fixes: b63a16f6cd ("drm/i915: Compute display surface offset in the plane check 
hook for SKL+")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98258
Testcase: igt/pm_rpm/legacy-planes
Testcase: igt/pm_rpm/universal-planes
Signed-off-by: Matt Roper 
---
There may be additional IGT tests (e.g., in kms_plane) that also trip over
this.  I only listed the two that I was using for debugging when I tracked this
down.

 drivers/gpu/drm/i915/intel_display.c | 2 +-
 drivers/gpu/drm/i915/intel_sprite.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0a38de9..9295f8a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15149,7 +15149,7 @@ intel_check_primary_plane(struct drm_plane *plane,
if (!state->base.fb)
return 0;
 
-   if (INTEL_GEN(dev_priv) >= 9) {
+   if (INTEL_GEN(dev_priv) >= 9 && state->base.visible) {
ret = skl_check_plane_surface(state);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index ada8f7a..5cedea4 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -967,7 +967,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
dst->y1 = crtc_y;
dst->y2 = crtc_y + crtc_h;
 
-   if (INTEL_GEN(dev) >= 9) {
+   if (INTEL_GEN(dev) >= 9 && state->base.visible) {
ret = skl_check_plane_surface(state);
if (ret)
return ret;
-- 
2.10.2

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[Intel-gfx] [PATCH 3/3] intel: Support passing of explicit fencing from execbuf

[Chad Versace]

From: Chris Wilson 

Allow the caller to pass in an fd to an array of fences to control
serialisation of the execbuf in the kernel and on the GPU, and in return
allow creation of a fence fd for signaling the completion (and flushing)
of the batch. When the returned fence is signaled, all writes to the
buffers inside the batch will be complete and coherent from the cpu, or
other consumers. The return fence is a sync_file object and can be
passed to other users (such as atomic modesetting, or other drivers).

Fixes from rantogno:
  - Fix the in/out fence flags on execbuf.

Signed-off-by: Chris Wilson 
Squashed-fixes-from: Rafael Antognolli 
Signed-off-by: Chad Versace 
---
 intel/intel_bufmgr.h |  6 ++
 intel/intel_bufmgr_gem.c | 32 +++-
 2 files changed, 33 insertions(+), 5 deletions(-)

diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h
index 6f128679..49cabf67 100644
--- a/intel/intel_bufmgr.h
+++ b/intel/intel_bufmgr.h
@@ -219,6 +219,12 @@ int drm_intel_gem_context_get_id(drm_intel_context *ctx,
 void drm_intel_gem_context_destroy(drm_intel_context *ctx);
 int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
  int used, unsigned int flags);
+int drm_intel_gem_bo_fence_exec(drm_intel_bo *bo,
+   drm_intel_context *ctx,
+   int used,
+   int in_fence,
+   int *out_fence,
+   unsigned int flags);
 
 int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd);
 drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index c5fc1b36..da993002 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -2376,6 +2376,7 @@ drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
 static int
 do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
+int in_fence, int *out_fence,
 unsigned int flags)
 {
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
@@ -2429,13 +2430,20 @@ do_exec2(drm_intel_bo *bo, int used, drm_intel_context 
*ctx,
i915_execbuffer2_set_context_id(execbuf, 0);
else
i915_execbuffer2_set_context_id(execbuf, ctx->ctx_id);
-   execbuf.rsvd2 = 0;
+   if (in_fence != -1) {
+   execbuf.rsvd2 = in_fence;
+   execbuf.flags |= I915_EXEC_FENCE_IN;
+   }
+   if (out_fence != NULL) {
+   *out_fence = -1;
+   execbuf.flags |= I915_EXEC_FENCE_OUT;
+   }
 
if (bufmgr_gem->no_exec)
goto skip_execution;
 
ret = drmIoctl(bufmgr_gem->fd,
-  DRM_IOCTL_I915_GEM_EXECBUFFER2,
+  DRM_IOCTL_I915_GEM_EXECBUFFER2_WR,
   );
if (ret != 0) {
ret = -errno;
@@ -2451,6 +2459,9 @@ do_exec2(drm_intel_bo *bo, int used, drm_intel_context 
*ctx,
}
drm_intel_update_buffer_offsets2(bufmgr_gem);
 
+   if (out_fence != NULL)
+   *out_fence = execbuf.rsvd2 >> 32;
+
 skip_execution:
if (bufmgr_gem->bufmgr.debug)
drm_intel_gem_dump_validation_list(bufmgr_gem);
@@ -2476,7 +2487,7 @@ drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
   int DR4)
 {
return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
-   I915_EXEC_RENDER);
+   -1, NULL, I915_EXEC_RENDER);
 }
 
 static int
@@ -2485,14 +2496,25 @@ drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
unsigned int flags)
 {
return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
-   flags);
+   -1, NULL, flags);
 }
 
 int
 drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
  int used, unsigned int flags)
 {
-   return do_exec2(bo, used, ctx, NULL, 0, 0, flags);
+   return do_exec2(bo, used, ctx, NULL, 0, 0, -1, NULL, flags);
+}
+
+int
+drm_intel_gem_bo_fence_exec(drm_intel_bo *bo,
+   drm_intel_context *ctx,
+   int used,
+   int in_fence,
+   int *out_fence,
+   unsigned int flags)
+{
+   return do_exec2(bo, used, ctx, NULL, 0, 0, in_fence, out_fence, flags);
 }
 
 static int
-- 
2.11.0.21.ga274e0a

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[Intel-gfx] [PATCH 2/3] intel: Allow the client to control implicit synchronisation

[Chad Versace]

From: Chris Wilson 

The kernel allows implicit synchronisation to be disabled on individual
buffers. Use at your own risk.

Signed-off-by: Chris Wilson 
---
 intel/intel_bufmgr.h |  2 ++
 intel/intel_bufmgr_gem.c | 32 
 2 files changed, 30 insertions(+), 4 deletions(-)

diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h
index 85e4ff78..6f128679 100644
--- a/intel/intel_bufmgr.h
+++ b/intel/intel_bufmgr.h
@@ -184,6 +184,8 @@ int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo);
 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
 
+void drm_intel_gem_bo_disable_implicit_sync(drm_intel_bo *bo);
+
 void *drm_intel_gem_bo_map__cpu(drm_intel_bo *bo);
 void *drm_intel_gem_bo_map__gtt(drm_intel_bo *bo);
 void *drm_intel_gem_bo_map__wc(drm_intel_bo *bo);
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 75949b9f..c5fc1b36 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -195,8 +195,11 @@ struct _drm_intel_bo_gem {
uint32_t swizzle_mode;
unsigned long stride;
 
+   unsigned long kflags;
+
time_t free_time;
 
+
/** Array passed to the DRM containing relocation information. */
struct drm_i915_gem_relocation_entry *relocs;
/**
@@ -575,12 +578,11 @@ drm_intel_add_validate_buffer2(drm_intel_bo *bo, int 
need_fence)
bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
bufmgr_gem->exec2_objects[index].alignment = bo->align;
-   bufmgr_gem->exec2_objects[index].offset = bo_gem->is_softpin ?
-   bo->offset64 : 0;
-   bufmgr_gem->exec_bos[index] = bo;
-   bufmgr_gem->exec2_objects[index].flags = flags;
+   bufmgr_gem->exec2_objects[index].offset = bo->offset64;
+   bufmgr_gem->exec2_objects[index].flags = flags | bo_gem->kflags;
bufmgr_gem->exec2_objects[index].rsvd1 = 0;
bufmgr_gem->exec2_objects[index].rsvd2 = 0;
+   bufmgr_gem->exec_bos[index] = bo;
bufmgr_gem->exec_count++;
 }
 
@@ -1368,6 +1370,7 @@ drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, 
time_t time)
for (i = 0; i < bo_gem->softpin_target_count; i++)

drm_intel_gem_bo_unreference_locked_timed(bo_gem->softpin_target[i],
  time);
+   bo_gem->kflags = 0;
bo_gem->reloc_count = 0;
bo_gem->used_as_reloc_target = false;
bo_gem->softpin_target_count = 0;
@@ -2765,6 +2768,27 @@ drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr 
*bufmgr)
 }
 
 /**
+ * Disables implicit synchronisation before executing the bo
+ *
+ * This will cause rendering corruption unless you correctly manage explicit
+ * fences for all rendering involving this buffer - including use by others.
+ * Disabling the implicit serialisation is only required if that serialisation
+ * is too coarse (for example, you have split the buffer into many
+ * non-overlapping regions and are sharing the whole buffer between concurrent
+ * independent command streams).
+ *
+ * Note the kernel must advertise support via I915_PARAM_HAS_EXEC_ASYNC or
+ * subsequent execbufs involving the bo will generate EINVAL.
+ */
+void
+drm_intel_gem_bo_disable_implicit_sync(drm_intel_bo *bo)
+{
+   drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
+
+   bo_gem->kflags |= EXEC_OBJECT_ASYNC;
+}
+
+/**
  * Enable use of fenced reloc type.
  *
  * New code should enable this to avoid unnecessary fence register
-- 
2.11.0.21.ga274e0a

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[Intel-gfx] ✓ Fi.CI.BAT: success for HuC Loading Patches

[Patchwork]

== Series Details ==

Series: HuC Loading Patches
URL   : https://patchwork.freedesktop.org/series/17992/
State : success

== Summary ==

Series 17992v1 HuC Loading Patches
https://patchwork.freedesktop.org/api/1.0/series/17992/revisions/1/mbox/

Test kms_flip:
Subgroup basic-plain-flip:
dmesg-warn -> PASS   (fi-snb-2520m)

fi-bdw-5557u total:246  pass:232  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050 total:246  pass:207  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:246  pass:224  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-t5700 total:82   pass:69   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:246  pass:219  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-ivb-3520m total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770  total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6260u total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hqtotal:246  pass:226  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k total:246  pass:222  dwarn:3   dfail:0   fail:0   skip:21 
fi-skl-6770hqtotal:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2520m total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-snb-2600  total:246  pass:214  dwarn:0   dfail:0   fail:0   skip:32 

5b8951aa5fc71afeed8cda24ee88bbe64dbea968 drm-tip: 2017y-01m-13d-16h-36m-26s UTC 
integration manifest
609a462 drm/i915/get_params: Add HuC status to getparams
ebaf2cc drm/i915/huc: Support HuC authentication
a0fb71d drm/i915/huc: Add debugfs for HuC loading status check
d1b8f55 drm/i915/HuC: Add KBL huC loading Support
b63f0c9 drm/i915/huc: Add BXT HuC Loading Support
7270f0d drm/i915/huc: Add HuC fw loading support
18a71c0 drm/i915/huc: Unified css_header struct for GuC and HuC
eae7232 drm/i915/guc: Make the GuC fw loading helper functions general

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3512/
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[Intel-gfx] [PATCH 1/3] WAIT: headers: Update drm_i915.h

[Chad Versace]

Generated with `make headers_install`
from tag 'chadv/test/i915-exec-fence-v03'
of .

TODO: Wait until header updates are in upstream kernel.
References: 
http://git.kiwitree.net/cgit/~chadv/linux/tag/?h=chadv/test/i915-exec-fence-v03
Signed-off-by: Chad Versace 
---
 include/drm/i915_drm.h | 277 +++--
 1 file changed, 267 insertions(+), 10 deletions(-)

diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index eb611a7a..48e023fa 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -29,6 +29,10 @@
 
 #include "drm.h"
 
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
 /* Please note that modifications to all structs defined here are
  * subject to backwards-compatibility constraints.
  */
@@ -58,6 +62,30 @@
 #define I915_ERROR_UEVENT  "ERROR"
 #define I915_RESET_UEVENT  "RESET"
 
+/*
+ * MOCS indexes used for GPU surfaces, defining the cacheability of the
+ * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
+ */
+enum i915_mocs_table_index {
+   /*
+* Not cached anywhere, coherency between CPU and GPU accesses is
+* guaranteed.
+*/
+   I915_MOCS_UNCACHED,
+   /*
+* Cacheability and coherency controlled by the kernel automatically
+* based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
+* usage of the surface (used for display scanout or not).
+*/
+   I915_MOCS_PTE,
+   /*
+* Cached in all GPU caches available on the platform.
+* Coherency between CPU and GPU accesses to the surface is not
+* guaranteed without extra synchronization.
+*/
+   I915_MOCS_CACHED,
+};
+
 /* Each region is a minimum of 16k, and there are at most 255 of them.
  */
 #define I915_NR_TEX_REGIONS 255/* table size 2k - maximum due to use
@@ -218,6 +246,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
 #define DRM_I915_OVERLAY_ATTRS 0x28
 #define DRM_I915_GEM_EXECBUFFER2   0x29
+#define DRM_I915_GEM_EXECBUFFER2_WRDRM_I915_GEM_EXECBUFFER2
 #define DRM_I915_GET_SPRITE_COLORKEY   0x2a
 #define DRM_I915_SET_SPRITE_COLORKEY   0x2b
 #define DRM_I915_GEM_WAIT  0x2c
@@ -230,6 +259,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_GEM_USERPTR   0x33
 #define DRM_I915_GEM_CONTEXT_GETPARAM  0x34
 #define DRM_I915_GEM_CONTEXT_SETPARAM  0x35
+#define DRM_I915_PERF_OPEN 0x36
 
 #define DRM_IOCTL_I915_INITDRM_IOW( DRM_COMMAND_BASE + 
DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH   DRM_IO ( DRM_COMMAND_BASE + 
DRM_I915_FLUSH)
@@ -251,6 +281,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_INITDRM_IOW(DRM_COMMAND_BASE + 
DRM_I915_GEM_INIT, struct drm_i915_gem_init)
 #define DRM_IOCTL_I915_GEM_EXECBUFFER  DRM_IOW(DRM_COMMAND_BASE + 
DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + 
DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
+#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR  DRM_IOWR(DRM_COMMAND_BASE + 
DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + 
DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
 #define DRM_IOCTL_I915_GEM_UNPIN   DRM_IOW(DRM_COMMAND_BASE + 
DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
 #define DRM_IOCTL_I915_GEM_BUSYDRM_IOWR(DRM_COMMAND_BASE + 
DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
@@ -283,6 +314,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR 
(DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAMDRM_IOWR (DRM_COMMAND_BASE + 
DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAMDRM_IOWR (DRM_COMMAND_BASE + 
DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
+#define DRM_IOCTL_I915_PERF_OPEN   DRM_IOW(DRM_COMMAND_BASE + 
DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -357,8 +389,28 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_HAS_GPU_RESET35
 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
 #define I915_PARAM_HAS_EXEC_SOFTPIN 37
-#define I915_PARAM_HAS_POOLED_EU 38
-#define I915_PARAM_MIN_EU_IN_POOL39
+#define I915_PARAM_HAS_POOLED_EU38
+#define I915_PARAM_MIN_EU_IN_POOL   39
+#define I915_PARAM_MMAP_GTT_VERSION 40
+
+/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
+ * priorities and the driver will attempt to execute batches in priority order.
+ * The initial priority for each batch is supplied by the context and is
+ * 

[Intel-gfx] [PATCH 0/3] intel: Add fence fd support to execbuf

[Chad Versace]

Chris wrote these patches, and the kernel patches too. I wrote the Mesa
patches that use the new feature. I'm submitting these patches myself to
get things moving.

This series depends on fence fd support in I915_GEM_EXECBUFFER2, which
isn't upstream in the kernel yet.  I tested this with kmscube on
Skylake, and everything looked good to me.

I pushed tags for this series as well as all the code I tested with:

mesa: 
http://git.kiwitree.net/cgit/~chadv/mesa/tag/?h=chadv/review/i965-exec-fence-v03
libdrm: 
http://git.kiwitree.net/cgit/~chadv/libdrm/tag/?h=chadv/review/intel-exec-fence-v01
linux: 
http://git.kiwitree.net/cgit/~chadv/linux/tag/?h=chadv/test/i915-exec-fence-v03
kmscube: 
http://git.kiwitree.net/cgit/~chadv/kmscube/tag/?h=chadv/test/fences-v02

I also sent Mesa patches to mesa-dev. Someone else should submit the
kernel patches, as I tested them but don't grok them.

Chad Versace (1):
  WAIT: headers: Update drm_i915.h

Chris Wilson (2):
  intel: Allow the client to control implicit synchronisation
  intel: Support passing of explicit fencing from execbuf

 include/drm/i915_drm.h   | 277 +--
 intel/intel_bufmgr.h |   8 ++
 intel/intel_bufmgr_gem.c |  64 +--
 3 files changed, 330 insertions(+), 19 deletions(-)

-- 
2.11.0.21.ga274e0a

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Re: [Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

[Rodrigo Vivi]

This and all the remaining patches on this series (6,7,8 and 9) got
merged to dinq.

Thanks for the patches.

On Thu, Jan 12, 2017 at 12:12 PM, Vivi, Rodrigo  wrote:
> Reviewed-by: Rodrigo Vivi 
>
> On Fri, 2017-01-13 at 00:31 +0530, vathsala nagaraju wrote:
>> As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed in
>> psr2 enable sequence.
>> bit 12 : Program Transcoder EDP VSC DIP header with a valid setting for
>> PSR2 and Set CHICKEN_TRANS_EDP(0x420cc) bit 12 for programmable
>> header packet.
>> bit 15 : Set CHICKEN_TRANS_EDP(0x420cc) bit 15 if Y coordinate is supported
>>
>> v2: (Rodrigo)
>> - move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
>>
>> v3:(Rodrigo)
>> - initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0
>>
>> v4:(chris wilson)
>> - use BIT(12), remove CHICKEN_TRANS_BIT12
>> - remove unnecessary comments
>> - update commit message
>>
>> v5:
>> - rename bit 12 PSR2_VSC_ENABLE_PROG_HEADER
>> - rename bit 15 PSR2_ADD_VERTICAL_LINE_COUNT
>>
>> v6:(Rodrigo)
>> - remove TRANS_EDP=3, use cpu_transcoder
>>
>> Cc: Rodrigo Vivi 
>> Cc: Jim Bride 
>> Signed-off-by: vathsala nagaraju 
>> Signed-off-by: Patil Deepti 
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h  | 6 ++
>>  drivers/gpu/drm/i915/intel_psr.c | 7 +++
>>  2 files changed, 13 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 7830e6e..c9c1ccd 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6449,6 +6449,12 @@ enum {
>>  #define  BDW_DPRS_MASK_VBLANK_SRD(1 << 0)
>>  #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, 
>> _CHICKEN_PIPESL_1_B)
>>
>> +#define CHICKEN_TRANS_A 0x420c0
>> +#define CHICKEN_TRANS_B 0x420c4
>> +#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, 
>> CHICKEN_TRANS_B)
>> +#define PSR2_VSC_ENABLE_PROG_HEADER(1<<12)
>> +#define PSR2_ADD_VERTICAL_LINE_COUNT   (1<<15)
>> +
>>  #define DISP_ARB_CTL _MMIO(0x45000)
>>  #define  DISP_FBC_MEMORY_WAKE(1<<31)
>>  #define  DISP_TILE_SURFACE_SWIZZLING (1<<13)
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
>> b/drivers/gpu/drm/i915/intel_psr.c
>> index 36c4045..935402e 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -480,6 +480,9 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>>   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>>   struct drm_device *dev = intel_dig_port->base.base.dev;
>>   struct drm_i915_private *dev_priv = to_i915(dev);
>> + struct intel_crtc *crtc = 
>> to_intel_crtc(intel_dig_port->base.base.crtc);
>> + enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
>> + u32 chicken;
>>
>>   if (!HAS_PSR(dev_priv)) {
>>   DRM_DEBUG_KMS("PSR not supported on this platform\n");
>> @@ -505,6 +508,10 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>>   if (HAS_DDI(dev_priv)) {
>>   if (dev_priv->psr.psr2_support) {
>>   skl_psr_setup_su_vsc(intel_dp);
>> + chicken = PSR2_VSC_ENABLE_PROG_HEADER;
>> + if (dev_priv->psr.y_cord_support)
>> + chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
>> + I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
>>   } else {
>>   /* set up vsc header for psr1 */
>>   hsw_psr_setup_vsc(intel_dp);
>
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Re: [Intel-gfx] [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Chris Wilson]

On Fri, Jan 13, 2017 at 06:19:53PM +, Srivatsa, Anusha wrote:
> >> +  /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> >> +  I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);

This is not required on drm-tip.

> >> +  /* Specify auth action and where public signature is. */
> >> +  data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
> >> +  data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
> >> +
> >> +  ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
> >> +  if (ret) {
> >> +  DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
> >> +  goto out;
> >> +  }
> >> +
> >> +  /* Check authentication status, it should be done by now */
> >> +  ret = intel_wait_for_register(dev_priv,
> >> +  HUC_STATUS2,
> >> +  HUC_FW_VERIFIED,
> >> +  HUC_FW_VERIFIED,
> >> +  50);
> >> +
> >> +  if (ret) {
> >> +  DRM_ERROR("HuC: Authentication failed %d\n", ret);
> >> +  goto out;
> >> +  }
> >> +
> >> +  DRM_INFO("HuC Authentication Successful!\n");

You still seem surprised. Is this a useful user message? What does it
mean for the user? Avoid using jargon when talking to the user.
-Chris

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Re: [Intel-gfx] [PATCH] dim: Triple-check and tripe warning when merging patches that touch files outside i915.

[Rodrigo Vivi]

On Thu, Jan 12, 2017 at 11:04 PM, Jani Nikula  wrote:
> On Fri, 13 Jan 2017, Rodrigo Vivi  wrote:
>> Most of commiters already knows that by heart and also dim already
>> have this warning. So maybe this is just Bart writing to blackboard. Duh!
>>
>> Anyway for my own usage this tripe check will help for sure.
>> Maybe it help someone else in the future.
>
> Well, this has changed with drm-misc; very few of the commits there have
> acks from Dave. And that was sort of the point in that tree, to scale
> better and not depend on his acks on every little detail.

Ah cool!

>
> I suppose the checks in dim could be branch specific.

makes sense. but what is beter for this new check?
1. if is drm-intel-next-queued
2 if not drm-misc

any modification on the current warning?

Thanks,
Rodrigo.

>
> BR,
> Jani.
>
>
>>
>> Cc: Daniel Vetter 
>> Cc: Jani Nikula 
>> Signed-off-by: Rodrigo Vivi 
>> ---
>>  dim   | 4 
>>  drm-intel.rst | 4 +++-
>>  2 files changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/dim b/dim
>> index eec5e43..73f6212 100755
>> --- a/dim
>> +++ b/dim
>> @@ -933,6 +933,10 @@ function checkpatch_commit
>>   echo -e "The following files are outside of i915 
>> maintenance scope:\n"
>>   echo "$non_i915_files"
>>   echo -e "\nConfirm you have appropriate Acked-by and 
>> Reviewed-by for above files."
>> + local acked_by_airlie=$($cmd | grep "Acked-by: Dave 
>> Airlie ")
>> + if [ "$acked_by_airlie" == "" ]; then
>> + echo -e "\nRemind that for drm you should have an 
>> Acked-by from Dave Airlie "
>> + fi
>>   fi
>>   fi
>>  }
>> diff --git a/drm-intel.rst b/drm-intel.rst
>> index 79db1cf..583a687 100644
>> --- a/drm-intel.rst
>> +++ b/drm-intel.rst
>> @@ -300,7 +300,9 @@ the right decisions, and for others to set their the 
>> expectations right.
>>
>>  The short list:
>>
>> -* Only push patches changing `drivers/gpu/drm/i915`.
>> +* Only push patches changing `drivers/gpu/drm/i915`. If dim mentioned that 
>> you
>> +  are touching files outside i915 stop and make sure that you have the 
>> proper
>> +  Acked-by. Specially for drm files an Acked-by from Dave Airlie is 
>> required.
>>
>>  * Only push patches to `drm-intel-next-queued` branch.
>
> --
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Re: [Intel-gfx] [PATCH 35/37] drm/i915: Live testing for context execution

[Chris Wilson]

On Fri, Jan 13, 2017 at 04:28:58PM +0200, Joonas Lahtinen wrote:
> On ke, 2017-01-11 at 21:09 +, Chris Wilson wrote:
> 
> 
> For future synchronization purposes, maybe document where the below was
> cloned from?

It is a routine I've written many times.

> > +   offset = PAGE_SIZE * first_page + offset_in_page;
> > +   offset += vma->node.start;
> > +   for (sz = 0; sz < count; sz++) {
> > +   if (gen >= 8) {
> > +   *cmd++ = MI_STORE_DWORD_IMM_GEN4;
> > +   *cmd++ = lower_32_bits(offset);
> > +   *cmd++ = upper_32_bits(offset);
> > +   *cmd++ = value;
> > +   } else if (gen >= 6) {
> > +   *cmd++ = MI_STORE_DWORD_IMM_GEN4;
> > +   *cmd++ = 0;
> > +   *cmd++ = offset;

> > +static int gpu_fill(struct drm_i915_gem_object *obj,
> > +   struct i915_gem_context *ctx)
> > +{
> > +   struct drm_i915_private *i915 = to_i915(obj->base.dev);
> > +   const unsigned long npages = obj->base.size >> PAGE_SHIFT;
> > +   struct i915_address_space *vm = ctx->ppgtt ? >ppgtt->base : 
> > >ggtt.base;
> 
> vm = &(ctx->ppgtt ?: >ggtt)->base? Or does GCC bork up.

Different types, gcc doesn't like them inside the ternary.
 
> Long line anyway.
> 
> > +   struct intel_engine_cs *engine = i915->engine[RCS];
> 
> rcs_fill as function name (rcs_fill_pages too)?

Now using all engines. Just let me be lazy, just once?

> > +   err = i915_gem_object_set_to_gtt_domain(obj, false);
> 
> Isn't the object most definitely going to be written by GPU?

Yes. But, before we begin I want any CPU writes to be flushed to memory
(if not LLC).
 
> > +
> > +   err = i915_vma_pin(vma, 0, 0, PIN_USER);
> > +   if (err)
> > +   return err;
> > +
> > +   GEM_BUG_ON(!IS_ALIGNED(npages, 1024));
> 
> Ok, #define time 1024 is a very magicy.

You're going to love the replacement magic. No spoilers I'm afraid.
 
> > +   }
> > +
> > +   i915_switch_context(rq);
> 
> GEM_BUG_ON(rq->engine != engine) to help readability.

Don't see how that helps readibility. That's a check that should in the
earlier request construction tests.
 
> This all makes me think how strange our internal API actually is.

Yes.
 
> > +
> > +   ww_mutex_lock(>resv->lock, NULL);
> > +   reservation_object_add_excl_fence(obj->resv, >fence);
> 
> Wasn't there a patch not to mess with the reservation internals (aka,
> wrap it?)

My bad, I keep thinking that it is still private to my tree.
 
> > +   ww_mutex_unlock(>resv->lock);
> > +
> > +   __i915_add_request(rq, true);
> > +   }
> 
> I imagine this work submission helper might come in handy as a separate
> thing?

Not quite yet. But something like this. Kind of waiting for more users
plus. There are some quirks that need some care to avoid upsetting
random tests.
 
> > +   for (n = 0; !err && n < 1024; n++) {
> > +   u32 *map;
> > +
> > +   map = kmap_atomic(i915_gem_object_get_page(obj, n));
> 
> Does some test check the kmap works?

No, it's documented as "just works". So if it doesn't we have plenty of
explosions every where.

> > +static int igt_ctx_exec(void *arg)
> > +{
> 
> 
> 
> > +   mutex_lock(>drm.struct_mutex);
> > +   while (!time_after(jiffies, end_time)) {
> 
> Time budgeted function?
> 
> > +   vm = ctx->ppgtt ? >ppgtt->base : >ggtt.base;
> > +   npages = min(vm->total / 2, 1024ull * 1024 * PAGE_SIZE);
> > +   npages >>= PAGE_SHIFT + 10;
> > +   npages <<= PAGE_SHIFT + 10;
> 
> What? Comment please.

Drop the low 22 bits. What, you'd rather have round_down()? Heresy!

> > +   count = 0;
> > +   list_for_each_entry(obj, , batch_pool_link) {
> > +   if (!err)
> > +   err = cpu_check(obj, count);
> 
> break; count is not used after this point, so why does it matter after?

It was freeing objects until the fake_file trick.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Move GuC log related functions into dedicated file

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Move GuC log related functions into dedicated file
URL   : https://patchwork.freedesktop.org/series/17988/
State : success

== Summary ==

Series 17988v1 drm/i915/guc: Move GuC log related functions into dedicated file
https://patchwork.freedesktop.org/api/1.0/series/17988/revisions/1/mbox/

Test kms_flip:
Subgroup basic-plain-flip:
dmesg-warn -> PASS   (fi-snb-2520m)

fi-bdw-5557u total:246  pass:232  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050 total:246  pass:207  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:246  pass:224  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-t5700 total:82   pass:69   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:246  pass:219  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-ivb-3520m total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770  total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6260u total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hqtotal:246  pass:226  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k total:246  pass:222  dwarn:3   dfail:0   fail:0   skip:21 
fi-snb-2520m total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-snb-2600  total:246  pass:214  dwarn:0   dfail:0   fail:0   skip:32 

5b8951aa5fc71afeed8cda24ee88bbe64dbea968 drm-tip: 2017y-01m-13d-16h-36m-26s UTC 
integration manifest
3e80fb4 drm/i915/guc: Move GuC log related functions into dedicated file

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3511/
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Re: [Intel-gfx] [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Srivatsa, Anusha]

>-Original Message-
>From: Wajdeczko, Michal
>Sent: Friday, January 13, 2017 10:18 AM
>To: Srivatsa, Anusha 
>Cc: intel-gfx@lists.freedesktop.org; Chris Wilson ;
>Hiler, Arkadiusz ; Alex Dai ; 
>Peter
>Antoine 
>Subject: Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication
>
>On Fri, Jan 13, 2017 at 10:08:42AM -0800, Anusha Srivatsa wrote:
>> The HuC authentication is done by host2guc call. The HuC RSA keys are
>> sent to GuC for authentication.
>>
>> v2: rebased on top of drm-tip. Changed name format and upped version
>> 1.7.
>> v3: changed wait_for_atomic to wait_for
>> v4: rebased. Rename intel_huc_auh() to intel_guc_auth_huc() and place
>> the prototype in intel_guc.h,correct the comments.
>> v5: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c to
>> intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
>> Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
>> AUTHENTICATE_HUC
>> v6: rebased. Add newline on DRM_ERRORs that already dont have one.
>> v7: rebased. Replace wait_for with intel_wait_for_register() since the
>> latter employs sleep optimisations for quick responses- as pointed out
>> by Chris Wilson.
>> v8: rebased. Cleanup the intel_guc_auth_huc() by removing checks
>> already performed in earlier functions. Make comments more descriptive.
>> v9: rebased. Changed the bias for pinning the HuC object. Move
>> intel_guc_auth_huc() to intel_huc.c. Change DRM_DEBUGs to DRM_ERRORs
>> in intel_guc_auth_huc(). Add return status to DRM_ERRORs.
>> v10: Replace DRM_ERROR with DRM_INFO for cases that are non-
>> erroneous.
>>
>> Cc: Chris Wilson 
>> Cc: Arkadiusz Hiler 
>> Cc: Michal Wajdeczko 
>> Tested-by: Xiang Haihao 
>> Signed-off-by: Anusha Srivatsa 
>> Signed-off-by: Alex Dai 
>> Signed-off-by: Peter Antoine 
>> ---
>>  drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
>>  drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
>>  drivers/gpu/drm/i915/intel_huc.c| 53
>+
>>  drivers/gpu/drm/i915/intel_uc.h |  1 +
>>  4 files changed, 57 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> index ed1ab40..25691f0 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> @@ -505,6 +505,7 @@ enum intel_guc_action {
>>  INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
>>  INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
>>  INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
>> +INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
>>  INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
>>  INTEL_GUC_ACTION_LIMIT
>>  };
>> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>> b/drivers/gpu/drm/i915/intel_guc_loader.c
>> index 527558f..bb127a4 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>> @@ -530,6 +530,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>>  intel_uc_fw_status_repr(guc_fw->fetch_status),
>>  intel_uc_fw_status_repr(guc_fw->load_status));
>>
>> +intel_guc_auth_huc(dev_priv);
>> +
>>  if (i915.enable_guc_submission) {
>>  if (i915.guc_log_level >= 0)
>>  gen9_enable_guc_interrupts(dev_priv);
>> diff --git a/drivers/gpu/drm/i915/intel_huc.c
>> b/drivers/gpu/drm/i915/intel_huc.c
>> index 8b84ba8..4ae34b5 100644
>> --- a/drivers/gpu/drm/i915/intel_huc.c
>> +++ b/drivers/gpu/drm/i915/intel_huc.c
>> @@ -284,3 +284,56 @@ void intel_huc_fini(struct drm_i915_private *dev_priv)
>>  huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;  }
>>
>> +/**
>> + * intel_guc_auth_huc() - authenticate ucode
>> + * @dev_priv: the drm_i915_device
>> + *
>> + * Triggers a HuC fw authentication request to the GuC via
>> +intel_guc_action_
>> + * authenticate_huc interface.
>> + */
>> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) {
>> +struct intel_guc *guc = _priv->guc;
>> +struct intel_huc *huc = _priv->huc;
>> +struct i915_vma *vma;
>> +int ret;
>> +u32 data[2];
>> +
>> +vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
>> +PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
>> +if (IS_ERR(vma)) {
>> +DRM_ERROR("failed to pin huc fw object %d\n",
>
>Maybe this message should start with "HuC:" to match other error messages used
>below ? Anyway,
>
>Reviewed-by: Michal Wajdeczko 

Thanks a lot Michal!

>Thanks,
>Michal
>
>
>> +(int)PTR_ERR(vma));
>> +return;
>> +}
>> +
>> +/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
>> +I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
>> +
>> +/* 

Re: [Intel-gfx] [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Michal Wajdeczko]

On Fri, Jan 13, 2017 at 10:08:42AM -0800, Anusha Srivatsa wrote:
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
> 
> v2: rebased on top of drm-tip. Changed name format and upped
> version 1.7.
> v3: changed wait_for_atomic to wait_for
> v4: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
> and place the prototype in intel_guc.h,correct the comments.
> v5: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
> to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
> Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
> AUTHENTICATE_HUC
> v6: rebased. Add newline on DRM_ERRORs that already dont have one.
> v7: rebased. Replace wait_for with intel_wait_for_register() since
> the latter employs sleep optimisations for quick responses- as pointed
> out by Chris Wilson.
> v8: rebased. Cleanup the intel_guc_auth_huc() by removing checks
> already performed in earlier functions. Make comments more descriptive.
> v9: rebased. Changed the bias for pinning the HuC object. Move
> intel_guc_auth_huc() to intel_huc.c. Change DRM_DEBUGs to DRM_ERRORs
> in intel_guc_auth_huc(). Add return status to DRM_ERRORs.
> v10: Replace DRM_ERROR with DRM_INFO for cases that are non-
> erroneous.
> 
> Cc: Chris Wilson 
> Cc: Arkadiusz Hiler 
> Cc: Michal Wajdeczko 
> Tested-by: Xiang Haihao 
> Signed-off-by: Anusha Srivatsa 
> Signed-off-by: Alex Dai 
> Signed-off-by: Peter Antoine 
> ---
>  drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
>  drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
>  drivers/gpu/drm/i915/intel_huc.c| 53 
> +
>  drivers/gpu/drm/i915/intel_uc.h |  1 +
>  4 files changed, 57 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
> b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index ed1ab40..25691f0 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -505,6 +505,7 @@ enum intel_guc_action {
>   INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
>   INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
>   INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
> + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
>   INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
>   INTEL_GUC_ACTION_LIMIT
>  };
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
> b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 527558f..bb127a4 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -530,6 +530,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>   intel_uc_fw_status_repr(guc_fw->fetch_status),
>   intel_uc_fw_status_repr(guc_fw->load_status));
>  
> + intel_guc_auth_huc(dev_priv);
> +
>   if (i915.enable_guc_submission) {
>   if (i915.guc_log_level >= 0)
>   gen9_enable_guc_interrupts(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_huc.c 
> b/drivers/gpu/drm/i915/intel_huc.c
> index 8b84ba8..4ae34b5 100644
> --- a/drivers/gpu/drm/i915/intel_huc.c
> +++ b/drivers/gpu/drm/i915/intel_huc.c
> @@ -284,3 +284,56 @@ void intel_huc_fini(struct drm_i915_private *dev_priv)
>   huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
>  }
>  
> +/**
> + * intel_guc_auth_huc() - authenticate ucode
> + * @dev_priv: the drm_i915_device
> + *
> + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
> + * authenticate_huc interface.
> + */
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
> +{
> + struct intel_guc *guc = _priv->guc;
> + struct intel_huc *huc = _priv->huc;
> + struct i915_vma *vma;
> + int ret;
> + u32 data[2];
> +
> + vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
> + PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
> + if (IS_ERR(vma)) {
> + DRM_ERROR("failed to pin huc fw object %d\n",

Maybe this message should start with "HuC:" to match other error
messages used below ? Anyway,

Reviewed-by: Michal Wajdeczko 

Thanks,
Michal


> + (int)PTR_ERR(vma));
> + return;
> + }
> +
> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> + /* Specify auth action and where public signature is. */
> + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
> + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
> +
> + ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
> + if (ret) {
> + DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
> + goto out;
> + }
> +
> + /* Check authentication status, it should be done by now */
> + ret = intel_wait_for_register(dev_priv,
> +   

[Intel-gfx] [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Anusha Srivatsa]

The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.

v2: rebased on top of drm-tip. Changed name format and upped
version 1.7.
v3: changed wait_for_atomic to wait_for
v4: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
and place the prototype in intel_guc.h,correct the comments.
v5: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
AUTHENTICATE_HUC
v6: rebased. Add newline on DRM_ERRORs that already dont have one.
v7: rebased. Replace wait_for with intel_wait_for_register() since
the latter employs sleep optimisations for quick responses- as pointed
out by Chris Wilson.
v8: rebased. Cleanup the intel_guc_auth_huc() by removing checks
already performed in earlier functions. Make comments more descriptive.
v9: rebased. Changed the bias for pinning the HuC object. Move
intel_guc_auth_huc() to intel_huc.c. Change DRM_DEBUGs to DRM_ERRORs
in intel_guc_auth_huc(). Add return status to DRM_ERRORs.
v10: Replace DRM_ERROR with DRM_INFO for cases that are non-
erroneous.

Cc: Chris Wilson 
Cc: Arkadiusz Hiler 
Cc: Michal Wajdeczko 
Tested-by: Xiang Haihao 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Alex Dai 
Signed-off-by: Peter Antoine 
---
 drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
 drivers/gpu/drm/i915/intel_huc.c| 53 +
 drivers/gpu/drm/i915/intel_uc.h |  1 +
 4 files changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index ed1ab40..25691f0 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -505,6 +505,7 @@ enum intel_guc_action {
INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
+   INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
INTEL_GUC_ACTION_LIMIT
 };
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 527558f..bb127a4 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -530,6 +530,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
intel_uc_fw_status_repr(guc_fw->fetch_status),
intel_uc_fw_status_repr(guc_fw->load_status));
 
+   intel_guc_auth_huc(dev_priv);
+
if (i915.enable_guc_submission) {
if (i915.guc_log_level >= 0)
gen9_enable_guc_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 8b84ba8..4ae34b5 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -284,3 +284,56 @@ void intel_huc_fini(struct drm_i915_private *dev_priv)
huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
 }
 
+/**
+ * intel_guc_auth_huc() - authenticate ucode
+ * @dev_priv: the drm_i915_device
+ *
+ * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
+ * authenticate_huc interface.
+ */
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
+{
+   struct intel_guc *guc = _priv->guc;
+   struct intel_huc *huc = _priv->huc;
+   struct i915_vma *vma;
+   int ret;
+   u32 data[2];
+
+   vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
+   PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
+   if (IS_ERR(vma)) {
+   DRM_ERROR("failed to pin huc fw object %d\n",
+   (int)PTR_ERR(vma));
+   return;
+   }
+
+   /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+   I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+   /* Specify auth action and where public signature is. */
+   data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
+   data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
+
+   ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
+   if (ret) {
+   DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
+   goto out;
+   }
+
+   /* Check authentication status, it should be done by now */
+   ret = intel_wait_for_register(dev_priv,
+   HUC_STATUS2,
+   HUC_FW_VERIFIED,
+   HUC_FW_VERIFIED,
+   50);
+
+   if (ret) {
+   DRM_ERROR("HuC: Authentication failed %d\n", ret);
+   goto out;
+   }
+
+   DRM_INFO("HuC Authentication Successful!\n");
+out:
+   

[Intel-gfx] [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC

[Anusha Srivatsa]

HuC firmware css header has almost exactly same definition as GuC
firmware except for the sw_version. Also, add a new member fw_type
into intel_uc_fw to indicate what kind of fw it is. So, the loader
will pull right sw_version from header.

v2: rebased on-top of drm-intel-nightly
v3: rebased. Rename device_id to guc_branch_client_version,
make guc_sw_version a union. . Put UC_FW_TYPE_GUC
and UC_FW_TYPE_HUC into an enum.
v4: rebased on top of drm-tip.Update dev to dev_priv in
intel_uc_fw_fetch.
v5: rebased. Add INTEL_ prefix to an enum. Add fw_type declaration
from patch 1.Combine two different unions for huc and guc version,
reserved etc into one union with two structs.
v6: rebased. Change fw_type to enum.
v7: rebased. Rename the enum fw_type to intel_uc_fw_type.

Cc: Michal Wajdeczko 
Tested-by: Xiang Haihao 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Alex Dai 
Signed-off-by: Peter Antoine 
Reviewed-by: Arkadiusz Hiler 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/intel_guc_fwif.h   | 23 ++
 drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++---
 drivers/gpu/drm/i915/intel_uc.h |  6 +
 3 files changed, 53 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 3202b32..ed1ab40 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -145,7 +145,7 @@
  * The GuC firmware layout looks like this:
  *
  * +---+
- * |guc_css_header |
+ * | uc_css_header |
  * |   |
  * | contains major/minor version  |
  * +---+
@@ -172,9 +172,16 @@
  * 3. Length info of each component can be found in header, in dwords.
  * 4. Modulus and exponent key are not required by driver. They may not appear
  *in fw. So driver will load a truncated firmware in this case.
+ *
+ * HuC firmware layout is same as GuC firmware.
+ *
+ * HuC firmware css header is different. However, the only difference is where
+ * the version information is saved. The uc_css_header is unified to support
+ * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
+ * uc_css_header.guc_sw_version for GuC.
  */
 
-struct guc_css_header {
+struct uc_css_header {
uint32_t module_type;
/* header_size includes all non-uCode bits, including css_header, rsa
 * key, modulus key and exponent data. */
@@ -205,8 +212,16 @@ struct guc_css_header {
 
char username[8];
char buildnumber[12];
-   uint32_t device_id;
-   uint32_t guc_sw_version;
+   union {
+   struct {
+   uint32_t branch_client_version;
+   uint32_t sw_version;
+   } guc;
+   struct {
+   uint32_t sw_version;
+   uint32_t reserved;
+   } huc;
+   };
uint32_t prod_preprod_fw;
uint32_t reserved[12];
uint32_t header_info;
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 5a2c86f..30801ee 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -595,7 +595,7 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
struct pci_dev *pdev = dev_priv->drm.pdev;
struct drm_i915_gem_object *obj;
const struct firmware *fw = NULL;
-   struct guc_css_header *css;
+   struct uc_css_header *css;
size_t size;
int err;
 
@@ -612,19 +612,19 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
uc_fw->path, fw);
 
/* Check the size of the blob before examining buffer contents */
-   if (fw->size < sizeof(struct guc_css_header)) {
+   if (fw->size < sizeof(struct uc_css_header)) {
DRM_NOTE("Firmware header is missing\n");
goto fail;
}
 
-   css = (struct guc_css_header *)fw->data;
+   css = (struct uc_css_header *)fw->data;
 
/* Firmware bits always start from header */
uc_fw->header_offset = 0;
uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
 
-   if (uc_fw->header_size != sizeof(struct guc_css_header)) {
+   if (uc_fw->header_size != sizeof(struct uc_css_header)) {
DRM_NOTE("CSS header definition mismatch\n");
goto fail;
}
@@ -648,21 +648,36 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
goto fail;
}
 
-   /* Header and uCode will be loaded to WOPCM. Size of the two. */
-   size = 

[Intel-gfx] [PATCH 6/8] drm/i915/huc: Add debugfs for HuC loading status check

[Anusha Srivatsa]

Add debugfs entry for HuC loading status check.

v2: rebased on top of drm-tip.

Cc: Michal wajdeczko 
Tested-by: Xiang Haihao 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Alex Dai 
Signed-off-by: Peter Antoine 
Reviewed-by: Jeff McGee 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 8ca8423..5829fb4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2352,6 +2352,36 @@ static int i915_llc(struct seq_file *m, void *data)
return 0;
 }
 
+static int i915_huc_load_status_info(struct seq_file *m, void *data)
+{
+   struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   struct intel_uc_fw *huc_fw = _priv->huc.fw;
+
+   if (!HAS_HUC_UCODE(dev_priv))
+   return 0;
+
+   seq_puts(m, "HuC firmware status:\n");
+   seq_printf(m, "\tpath: %s\n", huc_fw->path);
+   seq_printf(m, "\tfetch: %s\n",
+   intel_uc_fw_status_repr(huc_fw->fetch_status));
+   seq_printf(m, "\tload: %s\n",
+   intel_uc_fw_status_repr(huc_fw->load_status));
+   seq_printf(m, "\tversion wanted: %d.%d\n",
+   huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
+   seq_printf(m, "\tversion found: %d.%d\n",
+   huc_fw->major_ver_found, huc_fw->minor_ver_found);
+   seq_printf(m, "\theader: offset is %d; size = %d\n",
+   huc_fw->header_offset, huc_fw->header_size);
+   seq_printf(m, "\tuCode: offset is %d; size = %d\n",
+   huc_fw->ucode_offset, huc_fw->ucode_size);
+   seq_printf(m, "\tRSA: offset is %d; size = %d\n",
+   huc_fw->rsa_offset, huc_fw->rsa_size);
+
+   seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
+
+   return 0;
+}
+
 static int i915_guc_load_status_info(struct seq_file *m, void *data)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4580,6 +4610,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_guc_info", i915_guc_info, 0},
{"i915_guc_load_status", i915_guc_load_status_info, 0},
{"i915_guc_log_dump", i915_guc_log_dump, 0},
+   {"i915_huc_load_status", i915_huc_load_status_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
{"i915_drpc_info", i915_drpc_info, 0},
-- 
2.7.4

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[Intel-gfx] [PATCH 5/8] drm/i915/HuC: Add KBL huC loading Support

[Anusha Srivatsa]

This patch adds the support to load HuC on KBL
Version 2.0

v2: rebased on top of drm-tip. Rename KBL_FW_ to KBL_HUC_FW_
v3: rebased. Remove old checks.

Cc: Michal Wajdeczko 
Cc: Tvrtko Ursulin 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Arkadiusz Hiler 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/intel_huc.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 8877524..8b84ba8 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -48,6 +48,10 @@
 #define SKL_HUC_FW_MINOR 07
 #define SKL_BLD_NUM 1398
 
+#define KBL_HUC_FW_MAJOR 02
+#define KBL_HUC_FW_MINOR 00
+#define KBL_BLD_NUM 1810
+
 #define HUC_FW_PATH(platform, major, minor, bld_num) \
"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
__stringify(minor) "_" __stringify(bld_num) ".bin"
@@ -59,6 +63,11 @@ MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
 #define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
BXT_HUC_FW_MINOR, BXT_BLD_NUM)
 MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
+
+#define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
+   KBL_HUC_FW_MINOR, KBL_BLD_NUM)
+MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
+
 /**
  * huc_ucode_xfer() - DMA's the firmware
  * @dev_priv: the drm_i915_private device
@@ -165,6 +174,10 @@ void intel_huc_init(struct drm_i915_private *dev_priv)
fw_path = I915_BXT_HUC_UCODE;
huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR;
+   } else if (IS_KABYLAKE(dev_priv)) {
+   fw_path = I915_KBL_HUC_UCODE;
+   huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
+   huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
}
 
huc_fw->path = fw_path;
-- 
2.7.4

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[Intel-gfx] [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support

[Anusha Srivatsa]

This patch adds the HuC Loading for the BXT by using
the updated file construction.

Version 1.7 of the HuC firmware.

v2: rebased on to top drm-tip. Rename BXT_FW_MAJOR to BXT_HUC_FW_

Cc: Micha Wajdeczko 
Cc: Tvrtko Ursulin 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Arkadiusz Hiler 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/intel_huc.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 57471f2..8877524 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -40,6 +40,10 @@
  * Note that HuC firmware loading must be done before GuC loading.
  */
 
+#define BXT_HUC_FW_MAJOR 01
+#define BXT_HUC_FW_MINOR 07
+#define BXT_BLD_NUM 1398
+
 #define SKL_HUC_FW_MAJOR 01
 #define SKL_HUC_FW_MINOR 07
 #define SKL_BLD_NUM 1398
@@ -52,6 +56,9 @@
SKL_HUC_FW_MINOR, SKL_BLD_NUM)
 MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
 
+#define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
+   BXT_HUC_FW_MINOR, BXT_BLD_NUM)
+MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
 /**
  * huc_ucode_xfer() - DMA's the firmware
  * @dev_priv: the drm_i915_private device
@@ -154,6 +161,10 @@ void intel_huc_init(struct drm_i915_private *dev_priv)
fw_path = I915_SKL_HUC_UCODE;
huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
+   } else if (IS_BROXTON(dev_priv)) {
+   fw_path = I915_BXT_HUC_UCODE;
+   huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR;
+   huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR;
}
 
huc_fw->path = fw_path;
-- 
2.7.4

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[Intel-gfx] [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams

[Anusha Srivatsa]

This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.

v2: removed the forewakes as the registers are already force-woken.
 (T.Ursulin)
v3: rebased on top of drm-tip. Removed any reference to intel_huc.h
v4: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
Remove intel_is_huc_valid() since it is used only in one place.
Put the case of I915_PARAM_HAS_HUC() in the right place.
v5: rebased. Add a comment to specify that I915_READ(reg)
does not read garbage value. The register HUC_STATUS2 is force
woken and no rpm is needed.

Signed-off-by: Anusha Srivatsa 
Signed-off-by: Peter Antoine 
Reviewed-by: Arkadiusz Hiler 
---
 drivers/gpu/drm/i915/i915_drv.c | 7 +++
 include/uapi/drm/i915_drm.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d7a0b49..49a927a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
 #include "i915_trace.h"
 #include "i915_vgpu.h"
 #include "intel_drv.h"
+#include "intel_uc.h"
 
 static struct drm_driver driver;
 
@@ -315,6 +316,12 @@ static int i915_getparam(struct drm_device *dev, void 
*data,
case I915_PARAM_MIN_EU_IN_POOL:
value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
break;
+   case I915_PARAM_HUC_STATUS:
+   /* The register is already force-woken. We dont need
+* any rpm here
+*/
+   value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
+   break;
case I915_PARAM_MMAP_GTT_VERSION:
/* Though we've started our numbering from 1, and so class all
 * earlier versions as 0, in effect their value is undefined as
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index da32c2f..57093b4 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait {
  * priorities and the driver will attempt to execute batches in priority order.
  */
 #define I915_PARAM_HAS_SCHEDULER41
+#define I915_PARAM_HUC_STATUS   42
 
 typedef struct drm_i915_getparam {
__s32 param;
-- 
2.7.4

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[Intel-gfx] [PATCH 0/8] HuC Loading Patches

[Anusha Srivatsa]

The patches add HuC loading support. The driver builds a frame level
workload which is stored in the graphics memory. This workload is presented
to HuC for processing. The driver, therefore should first determine if the
HuC is enabled and also read the huC athentication status bit to determine
if HuC was successfully loaded. The GuC is required to authenticate the HuC.
The userspace patches that check for a fully loaded HuC firmware and use it
can be found at:

https://lists.freedesktop.org/archives/libva/2016-September/004554.html
https://lists.freedesktop.org/archives/libva/2016-September/004555.html

More information regarding the HuC, batch commands that configure the
HuC etc can be found at-
https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol02a-commandreference-instructions-huc.pdf
https://www.x.org/docs/intel/CHV/intel-gfx-prm-osrc-chv-bsw-vol10-hevc.pdf

v2: rebased. Changed the code following the review comments.
v3: rebased. Organize code. Move contents of intel_huc.h to intel_uc.h.
Update function intel_huc_load(),intel_huc_init() and intel_uc_fw_fetch()
to accept dev_priv instead of dev.
v4: rebased. Remove intel_is_huc_valid() since it is called onoly once.
Refactor the code to reduce redundency. Remove fiels like uc_dev which
are no longer used.
v5: rebased. Beautify the code- remove comments that no longer hold
good, add newlines etc.
v6: rebased. Remove further redundency. Correct comments. Replace wait_for
with intel_wait_for_register() for optimisation purpose.Make fw_type an enum.
v7: rebased. Rename intel_huc_loader() to intel_huc(). Move intel_guc_auth_huc()
from intel_uc.c to intel_huc.c. Add return values to DRM_ERRORs.
v8: Use DRM_INFO instead of DRM_ERROR in places that are non-erraneous.
Remove invalidates that are no longer required.

Anusha Srivatsa (8):
  drm/i915/guc: Make the GuC fw loading helper functions general
  drm/i915/huc: Unified css_header struct for GuC and HuC
  drm/i915/huc: Add HuC fw loading support
  drm/i915/huc: Add BXT HuC Loading Support
  drm/i915/HuC: Add KBL huC loading Support
  drm/i915/huc: Add debugfs for HuC loading status check
  drm/i915/huc: Support HuC authentication
  drm/i915/get_params: Add HuC status to getparams

 drivers/gpu/drm/i915/Makefile  |   1 +
 drivers/gpu/drm/i915/i915_debugfs.c|  43 +++-
 drivers/gpu/drm/i915/i915_drv.c|  10 +
 drivers/gpu/drm/i915/i915_drv.h|   2 +
 drivers/gpu/drm/i915/i915_guc_reg.h|   6 +
 drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
 drivers/gpu/drm/i915/intel_guc_fwif.h  |  24 +-
 drivers/gpu/drm/i915/intel_guc_loader.c| 196 +
 drivers/gpu/drm/i915/intel_huc.c   | 342 +
 drivers/gpu/drm/i915/intel_uc.h|  60 +++--
 include/uapi/drm/i915_drm.h|   1 +
 11 files changed, 569 insertions(+), 120 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_huc.c

-- 
2.7.4

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[Intel-gfx] [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general

[Anusha Srivatsa]

Rename some of the GuC fw loading code to make them more general. We
will utilise them for HuC loading as well.
 s/intel_guc_fw/intel_uc_fw/g
 s/GUC_FIRMWARE/INTEL_UC_FIRMWARE/g

Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
same purpose.

v2: rebased on top of nightly.
reapplied the search/replace as upstream code as changed.
v3: removed G from messages in shared fw fetch function.
v4: rebased.Updated dev to dev_priv in intel_guc_setup(), guc_fw_getch()
and intel_guc_init().
v5: rebased. Remove uint32_t fw_type to patch 2. Add INTEL_ prefix for
fields in enum intel_uc_fw_status. Remove uc_dev field since its never
used.Rename uc_fw to just fw and guc_fw to fw to avoid redundency.
v6: rebased. Remove sections of code that were commented and no longer
required.
v7: rebased. Remove uc_fw_ prefix from path and obj fields
in intel_uc_fw struct as suggested by Michal.
v8: rebased. Add declaration of intel_guc_wopcm_size() in
this patch instead of patch 3.

Cc: Michal Wajdeczko 
Cc: Arkadiusz Hiler 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Alex Dai 
Signed-off-by: Peter Antoine 
Reviewed-by: Arkadiusz Hiler 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_debugfs.c|  12 +--
 drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
 drivers/gpu/drm/i915/intel_guc_loader.c| 156 ++---
 drivers/gpu/drm/i915/intel_uc.h|  37 +++
 4 files changed, 105 insertions(+), 104 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index e367f06..8ca8423 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2355,7 +2355,7 @@ static int i915_llc(struct seq_file *m, void *data)
 static int i915_guc_load_status_info(struct seq_file *m, void *data)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct intel_guc_fw *guc_fw = _priv->guc.guc_fw;
+   struct intel_uc_fw *guc_fw = _priv->guc.fw;
u32 tmp, i;
 
if (!HAS_GUC_UCODE(dev_priv))
@@ -2363,15 +2363,15 @@ static int i915_guc_load_status_info(struct seq_file 
*m, void *data)
 
seq_printf(m, "GuC firmware status:\n");
seq_printf(m, "\tpath: %s\n",
-   guc_fw->guc_fw_path);
+   guc_fw->path);
seq_printf(m, "\tfetch: %s\n",
-   intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+   intel_uc_fw_status_repr(guc_fw->fetch_status));
seq_printf(m, "\tload: %s\n",
-   intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+   intel_uc_fw_status_repr(guc_fw->load_status));
seq_printf(m, "\tversion wanted: %d.%d\n",
-   guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+   guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
seq_printf(m, "\tversion found: %d.%d\n",
-   guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
+   guc_fw->major_ver_found, guc_fw->minor_ver_found);
seq_printf(m, "\theader: offset is %d; size = %d\n",
guc_fw->header_offset, guc_fw->header_size);
seq_printf(m, "\tuCode: offset is %d; size = %d\n",
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 913d873..bb7cf95 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1481,7 +1481,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
struct i915_gem_context *ctx;
u32 data[3];
 
-   if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
gen9_disable_guc_interrupts(dev_priv);
@@ -1508,7 +1508,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
struct i915_gem_context *ctx;
u32 data[3];
 
-   if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
if (i915.guc_log_level >= 0)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index b889191..5a2c86f 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
 MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
 
 /* User-friendly representation of an enum */
-const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
+const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
 {
switch (status) {
-   case GUC_FIRMWARE_FAIL:
+   case 

[Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support

[Anusha Srivatsa]

The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
is used for both cases.

HuC loading needs to be before GuC loading. The WOPCM setting must
be done early before loading any of them.

v2: rebased on-top of drm-intel-nightly.
removed if(HAS_GUC()) before the guc call. (D.Gordon)
update huc_version number of format.
v3: rebased to drm-intel-nightly, changed the file name format to
match the one in the huc package.
Changed dev->dev_private to to_i915()
v4: moved function back to where it was.
change wait_for_atomic to wait_for.
v5: rebased. Changed the year in the copyright message to reflect
the right year.Correct the comments,remove the unwanted WARN message,
replace drm_gem_object_unreference() with i915_gem_object_put().Make the
prototypes in intel_huc.h non-extern.
v6: rebased. Update the file construction done by HuC. It is similar to
GuC.Adopted the approach used in-
https://patchwork.freedesktop.org/patch/104355/ 
v7: Change dev to dev_priv in macro definition.
Corrected comments.
v8: rebased on top of drm-tip. Updated functions 
intel_huc_load(),intel_huc_init() and
intel_uc_fw_fetch() to accept dev_priv instead of dev. Moved contents
of intel_huc.h to intel_uc.h
v9: change SKL_FW_ to SKL_HUC_FW_. Add intel_ prefix to guc_wopcm_size().
Remove unwanted checks in intel_uc.h. Rename huc_fw in struct intel_huc to
simply fw to avoid redundency.
v10: rebased. Correct comments. Make intel_huc_fini() accept dev_priv instead 
of dev
like intel_huc_init() and intel_huc_load().Move definition to i915_guc_reg.h 
from
intel_uc.h. Clean DMA_CTRL bits after HuC DMA transfer in huc_ucode_xfer()
instead of guc_ucode_xfer(). Add suitable WARNs to give extra info.
v11: rebased. Add proper bias for HuC and make sure there are
asserts on failure by using guc_ggtt_offset_vma(). Introduce
intel_huc.c and remove intel_huc_loader.c since it has functions that
do more than just loading.Correct year in copyright.
v12: remove invalidates that are not required anymore.

Cc: Arkadiusz Hiler 
Cc: Michal Wajdeczko 
Tested-by: Xiang Haihao 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Alex Dai 
Signed-off-by: Peter Antoine 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/Makefile   |   1 +
 drivers/gpu/drm/i915/i915_drv.c |   3 +
 drivers/gpu/drm/i915/i915_drv.h |   2 +
 drivers/gpu/drm/i915/i915_guc_reg.h |   6 +
 drivers/gpu/drm/i915/intel_guc_loader.c |   7 +-
 drivers/gpu/drm/i915/intel_huc.c| 262 
 drivers/gpu/drm/i915/intel_uc.h |  14 ++
 7 files changed, 292 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_huc.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5196509..1ea051a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -57,6 +57,7 @@ i915-y += i915_cmd_parser.o \
 # general-purpose microcontroller (GuC) support
 i915-y += intel_uc.o \
  intel_guc_loader.o \
+ intel_huc.o \
  i915_guc_submission.o
 
 # autogenerated null render state
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4e5ea58..d7a0b49 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -599,6 +599,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_irq;
 
+   intel_huc_init(dev_priv);
intel_guc_init(dev_priv);
 
ret = i915_gem_init(dev_priv);
@@ -627,6 +628,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
i915_gem_fini(dev_priv);
 cleanup_irq:
intel_guc_fini(dev_priv);
+   intel_huc_fini(dev_priv);
drm_irq_uninstall(dev);
intel_teardown_gmbus(dev_priv);
 cleanup_csr:
@@ -1314,6 +1316,7 @@ void i915_driver_unload(struct drm_device *dev)
drain_workqueue(dev_priv->wq);
 
intel_guc_fini(dev_priv);
+   intel_huc_fini(dev_priv);
i915_gem_fini(dev_priv);
intel_fbc_cleanup_cfb(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f861418..ed845a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2074,6 +2074,7 @@ struct drm_i915_private {
 
struct intel_gvt *gvt;
 
+   struct intel_huc huc;
struct intel_guc guc;
 
struct intel_csr csr;
@@ -2848,6 +2849,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_GUC(dev_priv)  ((dev_priv)->info.has_guc)
 #define HAS_GUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
 #define HAS_GUC_SCHED(dev_priv)(HAS_GUC(dev_priv))
+#define HAS_HUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
 
 #define HAS_RESOURCE_STREAMER(dev_priv) 

Re: [Intel-gfx] [RFC] drm/i915/guc: Move GuC log related functions into dedicated file

[Chris Wilson]

On Fri, Jan 13, 2017 at 05:41:57PM +, Michal Wajdeczko wrote:
> Functions supporting GuC logging capabilities were spread across
> many files, with unnecessary exposures and mixed with unrelated
> code. Dedicate file will make maintenance of all GuC functions
> easier as more functions are coming to support GuC submissions.
> 
> Signed-off-by: Michal Wajdeczko 
> Cc: Chris Wilson 

Looks clean enough. I don't expect any objections, anyone?
-Chris

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[Intel-gfx] [RFC] drm/i915/guc: Move GuC log related functions into dedicated file

[Michal Wajdeczko]

Functions supporting GuC logging capabilities were spread across
many files, with unnecessary exposures and mixed with unrelated
code. Dedicate file will make maintenance of all GuC functions
easier as more functions are coming to support GuC submissions.

Signed-off-by: Michal Wajdeczko 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/Makefile  |   1 +
 drivers/gpu/drm/i915/i915_drv.c|   4 +-
 drivers/gpu/drm/i915/i915_guc_submission.c | 594 +-
 drivers/gpu/drm/i915/intel_guc_loader.c|   6 -
 drivers/gpu/drm/i915/intel_guc_log.c   | 658 +
 drivers/gpu/drm/i915/intel_uc.c|  26 --
 drivers/gpu/drm/i915/intel_uc.h|  13 +-
 7 files changed, 673 insertions(+), 629 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_guc_log.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5196509..40185fd 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -56,6 +56,7 @@ i915-y += i915_cmd_parser.o \
 
 # general-purpose microcontroller (GuC) support
 i915-y += intel_uc.o \
+ intel_guc_log.o \
  intel_guc_loader.o \
  i915_guc_submission.o
 
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4e5ea58..350ee06 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1114,7 +1114,7 @@ static void i915_driver_register(struct drm_i915_private 
*dev_priv)
/* Reveal our presence to userspace */
if (drm_dev_register(dev, 0) == 0) {
i915_debugfs_register(dev_priv);
-   i915_guc_register(dev_priv);
+   i915_guc_log_register(dev_priv);
i915_setup_sysfs(dev_priv);
 
/* Depends on sysfs having been initialized */
@@ -1158,7 +1158,7 @@ static void i915_driver_unregister(struct 
drm_i915_private *dev_priv)
i915_perf_unregister(dev_priv);
 
i915_teardown_sysfs(dev_priv);
-   i915_guc_unregister(dev_priv);
+   i915_guc_log_unregister(dev_priv);
i915_debugfs_unregister(dev_priv);
drm_dev_unregister(_priv->drm);
 
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 913d873..73de503 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -22,8 +22,6 @@
  *
  */
 #include 
-#include 
-#include 
 #include "i915_drv.h"
 #include "intel_uc.h"
 
@@ -545,7 +543,7 @@ static void i915_guc_submit(struct drm_i915_gem_request *rq)
  */
 
 /**
- * guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
+ * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
  * @guc:   the guc
  * @size:  size of area to allocate (both virtual space and memory)
  *
@@ -557,7 +555,7 @@ static void i915_guc_submit(struct drm_i915_gem_request *rq)
  *
  * Return: A i915_vma if successful, otherwise an ERR_PTR.
  */
-static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
+struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct drm_i915_gem_object *obj;
@@ -718,7 +716,7 @@ guc_client_alloc(struct drm_i915_private *dev_priv,
}
 
/* The first page is doorbell/proc_desc. Two followed pages are wq. */
-   vma = guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE);
+   vma = intel_guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE);
if (IS_ERR(vma))
goto err;
 
@@ -774,488 +772,7 @@ guc_client_alloc(struct drm_i915_private *dev_priv,
return NULL;
 }
 
-/*
- * Sub buffer switch callback. Called whenever relay has to switch to a new
- * sub buffer, relay stays on the same sub buffer if 0 is returned.
- */
-static int subbuf_start_callback(struct rchan_buf *buf,
-void *subbuf,
-void *prev_subbuf,
-size_t prev_padding)
-{
-   /* Use no-overwrite mode by default, where relay will stop accepting
-* new data if there are no empty sub buffers left.
-* There is no strict synchronization enforced by relay between Consumer
-* and Producer. In overwrite mode, there is a possibility of getting
-* inconsistent/garbled data, the producer could be writing on to the
-* same sub buffer from which Consumer is reading. This can't be avoided
-* unless Consumer is fast enough and can always run in tandem with
-* Producer.
-*/
-   if (relay_buf_full(buf))
-   return 0;
-
-   return 1;
-}
-
-/*
- * file_create() callback. Creates relay file in debugfs.
- */
-static struct dentry *create_buf_file_callback(const char *filename,
-  struct dentry *parent,
-   

Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support

[Srivatsa, Anusha]

>-Original Message-
>From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
>Sent: Friday, January 13, 2017 9:16 AM
>To: Srivatsa, Anusha 
>Cc: intel-gfx@lists.freedesktop.org; Alex Dai ; Peter Antoine
>
>Subject: Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
>
>On Fri, Jan 13, 2017 at 09:06:34AM -0800, Anusha Srivatsa wrote:
>> +/**
>> + * huc_ucode_xfer() - DMA's the firmware
>> + * @dev_priv: the drm_i915_private device
>> + *
>> + * Transfer the firmware image to RAM for execution by the microcontroller.
>> + *
>> + * Return: 0 on success, non-zero on failure  */ static int
>> +huc_ucode_xfer(struct drm_i915_private *dev_priv) {
>> +struct intel_uc_fw *huc_fw = _priv->huc.fw;
>> +struct i915_vma *vma;
>> +unsigned long offset = 0;
>> +u32 size;
>> +int ret;
>> +
>> +ret = i915_gem_object_set_to_gtt_domain(huc_fw->obj, false);
>> +if (ret) {
>> +DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
>> +return ret;
>> +}
>> +
>> +vma = i915_gem_object_ggtt_pin(huc_fw->obj, NULL, 0, 0,
>> +PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
>> +if (IS_ERR(vma)) {
>> +DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
>> +return PTR_ERR(vma);
>> +}
>> +
>> +/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
>> +I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
>
>This invalidate is not required anymore.
>-Chris

When you previously mentioned, I did not expect it to become invalid so soon :)
Will remove it. Thanks.

Anusha 
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Re: [Intel-gfx] [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Srivatsa, Anusha]

>-Original Message-
>From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
>Sent: Friday, January 13, 2017 9:25 AM
>To: Srivatsa, Anusha 
>Cc: intel-gfx@lists.freedesktop.org; Hiler, Arkadiusz 
>;
>Wajdeczko, Michal ; Alex Dai
>; Peter Antoine 
>Subject: Re: [PATCH 7/8] drm/i915/huc: Support HuC authentication
>
>On Fri, Jan 13, 2017 at 09:07:08AM -0800, Anusha Srivatsa wrote:
>> +/**
>> + * intel_guc_auth_huc() - authenticate ucode
>> + * @dev_priv: the drm_i915_device
>> + *
>> + * Triggers a HuC fw authentication request to the GuC via
>> +intel_guc_action_
>> + * authenticate_huc interface.
>> + */
>> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv) {
>> +struct intel_guc *guc = _priv->guc;
>> +struct intel_huc *huc = _priv->huc;
>> +struct i915_vma *vma;
>> +int ret;
>> +u32 data[2];
>> +
>> +vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
>> +PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
>> +if (IS_ERR(vma)) {
>> +DRM_ERROR("failed to pin huc fw object %d\n",
>> +(int)PTR_ERR(vma));
>> +return;
>> +}
>> +
>> +/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
>> +I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
>> +
>> +/* Specify auth action and where public signature is. */
>> +data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
>> +data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
>> +
>> +ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
>> +if (ret) {
>> +DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
>> +goto out;
>> +}
>> +
>> +/* Check authentication status, it should be done by now */
>> +ret = intel_wait_for_register(dev_priv,
>> +HUC_STATUS2,
>> +HUC_FW_VERIFIED,
>> +HUC_FW_VERIFIED,
>> +50);
>> +
>> +if (ret) {
>> +DRM_ERROR("HuC: Authentication failed %d\n", ret);
>> +goto out;
>> +}
>> +
>> +DRM_ERROR("HuC Authentication Successful!\n");
>
>Probably don't want to proclaim using the HuC as an error ;-) -Chris

Oh... I was actually thinking it is good if it proclaimed
Wont it be useful message to know?

Anusha 
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Re: [Intel-gfx] [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Chris Wilson]

On Fri, Jan 13, 2017 at 09:07:08AM -0800, Anusha Srivatsa wrote:
> +/**
> + * intel_guc_auth_huc() - authenticate ucode
> + * @dev_priv: the drm_i915_device
> + *
> + * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
> + * authenticate_huc interface.
> + */
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
> +{
> + struct intel_guc *guc = _priv->guc;
> + struct intel_huc *huc = _priv->huc;
> + struct i915_vma *vma;
> + int ret;
> + u32 data[2];
> +
> + vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
> + PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
> + if (IS_ERR(vma)) {
> + DRM_ERROR("failed to pin huc fw object %d\n",
> + (int)PTR_ERR(vma));
> + return;
> + }
> +
> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> + /* Specify auth action and where public signature is. */
> + data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
> + data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
> +
> + ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
> + if (ret) {
> + DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
> + goto out;
> + }
> +
> + /* Check authentication status, it should be done by now */
> + ret = intel_wait_for_register(dev_priv,
> + HUC_STATUS2,
> + HUC_FW_VERIFIED,
> + HUC_FW_VERIFIED,
> + 50);
> +
> + if (ret) {
> + DRM_ERROR("HuC: Authentication failed %d\n", ret);
> + goto out;
> + }
> +
> + DRM_ERROR("HuC Authentication Successful!\n");

Probably don't want to proclaim using the HuC as an error ;-)
-Chris

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Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support

[Chris Wilson]

On Fri, Jan 13, 2017 at 09:06:34AM -0800, Anusha Srivatsa wrote:
> +/**
> + * huc_ucode_xfer() - DMA's the firmware
> + * @dev_priv: the drm_i915_private device
> + *
> + * Transfer the firmware image to RAM for execution by the microcontroller.
> + *
> + * Return: 0 on success, non-zero on failure
> + */
> +static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uc_fw *huc_fw = _priv->huc.fw;
> + struct i915_vma *vma;
> + unsigned long offset = 0;
> + u32 size;
> + int ret;
> +
> + ret = i915_gem_object_set_to_gtt_domain(huc_fw->obj, false);
> + if (ret) {
> + DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> + return ret;
> + }
> +
> + vma = i915_gem_object_ggtt_pin(huc_fw->obj, NULL, 0, 0,
> + PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
> + if (IS_ERR(vma)) {
> + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> + return PTR_ERR(vma);
> + }
> +
> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);

This invalidate is not required anymore.
-Chris

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[Intel-gfx] [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams

[Anusha Srivatsa]

This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.

v2: removed the forewakes as the registers are already force-woken.
 (T.Ursulin)
v3: rebased on top of drm-tip. Removed any reference to intel_huc.h
v4: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
Remove intel_is_huc_valid() since it is used only in one place.
Put the case of I915_PARAM_HAS_HUC() in the right place.
v5: rebased. Add a comment to specify that I915_READ(reg)
does not read garbage value. The register HUC_STATUS2 is force
woken and no rpm is needed.

Signed-off-by: Anusha Srivatsa 
Signed-off-by: Peter Antoine 
Reviewed-by: Arkadiusz Hiler 
---
 drivers/gpu/drm/i915/i915_drv.c | 7 +++
 include/uapi/drm/i915_drm.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d7a0b49..49a927a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
 #include "i915_trace.h"
 #include "i915_vgpu.h"
 #include "intel_drv.h"
+#include "intel_uc.h"
 
 static struct drm_driver driver;
 
@@ -315,6 +316,12 @@ static int i915_getparam(struct drm_device *dev, void 
*data,
case I915_PARAM_MIN_EU_IN_POOL:
value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
break;
+   case I915_PARAM_HUC_STATUS:
+   /* The register is already force-woken. We dont need
+* any rpm here
+*/
+   value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
+   break;
case I915_PARAM_MMAP_GTT_VERSION:
/* Though we've started our numbering from 1, and so class all
 * earlier versions as 0, in effect their value is undefined as
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index da32c2f..57093b4 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -395,6 +395,7 @@ typedef struct drm_i915_irq_wait {
  * priorities and the driver will attempt to execute batches in priority order.
  */
 #define I915_PARAM_HAS_SCHEDULER41
+#define I915_PARAM_HUC_STATUS   42
 
 typedef struct drm_i915_getparam {
__s32 param;
-- 
2.7.4

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[Intel-gfx] [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC

[Anusha Srivatsa]

HuC firmware css header has almost exactly same definition as GuC
firmware except for the sw_version. Also, add a new member fw_type
into intel_uc_fw to indicate what kind of fw it is. So, the loader
will pull right sw_version from header.

v2: rebased on-top of drm-intel-nightly
v3: rebased. Rename device_id to guc_branch_client_version,
make guc_sw_version a union. . Put UC_FW_TYPE_GUC
and UC_FW_TYPE_HUC into an enum.
v4: rebased on top of drm-tip.Update dev to dev_priv in
intel_uc_fw_fetch.
v5: rebased. Add INTEL_ prefix to an enum. Add fw_type declaration
from patch 1.Combine two different unions for huc and guc version,
reserved etc into one union with two structs.
v6: rebased. Change fw_type to enum.
v7: rebased. Rename the enum fw_type to intel_uc_fw_type.

Cc: Michal Wajdeczko 
Tested-by: Xiang Haihao 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Alex Dai 
Signed-off-by: Peter Antoine 
Reviewed-by: Arkadiusz Hiler 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/intel_guc_fwif.h   | 23 ++
 drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++---
 drivers/gpu/drm/i915/intel_uc.h |  6 +
 3 files changed, 53 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 3202b32..ed1ab40 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -145,7 +145,7 @@
  * The GuC firmware layout looks like this:
  *
  * +---+
- * |guc_css_header |
+ * | uc_css_header |
  * |   |
  * | contains major/minor version  |
  * +---+
@@ -172,9 +172,16 @@
  * 3. Length info of each component can be found in header, in dwords.
  * 4. Modulus and exponent key are not required by driver. They may not appear
  *in fw. So driver will load a truncated firmware in this case.
+ *
+ * HuC firmware layout is same as GuC firmware.
+ *
+ * HuC firmware css header is different. However, the only difference is where
+ * the version information is saved. The uc_css_header is unified to support
+ * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
+ * uc_css_header.guc_sw_version for GuC.
  */
 
-struct guc_css_header {
+struct uc_css_header {
uint32_t module_type;
/* header_size includes all non-uCode bits, including css_header, rsa
 * key, modulus key and exponent data. */
@@ -205,8 +212,16 @@ struct guc_css_header {
 
char username[8];
char buildnumber[12];
-   uint32_t device_id;
-   uint32_t guc_sw_version;
+   union {
+   struct {
+   uint32_t branch_client_version;
+   uint32_t sw_version;
+   } guc;
+   struct {
+   uint32_t sw_version;
+   uint32_t reserved;
+   } huc;
+   };
uint32_t prod_preprod_fw;
uint32_t reserved[12];
uint32_t header_info;
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 9071575..8ca2f62 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -594,7 +594,7 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
struct pci_dev *pdev = dev_priv->drm.pdev;
struct drm_i915_gem_object *obj;
const struct firmware *fw = NULL;
-   struct guc_css_header *css;
+   struct uc_css_header *css;
size_t size;
int err;
 
@@ -611,19 +611,19 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
uc_fw->path, fw);
 
/* Check the size of the blob before examining buffer contents */
-   if (fw->size < sizeof(struct guc_css_header)) {
+   if (fw->size < sizeof(struct uc_css_header)) {
DRM_NOTE("Firmware header is missing\n");
goto fail;
}
 
-   css = (struct guc_css_header *)fw->data;
+   css = (struct uc_css_header *)fw->data;
 
/* Firmware bits always start from header */
uc_fw->header_offset = 0;
uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
 
-   if (uc_fw->header_size != sizeof(struct guc_css_header)) {
+   if (uc_fw->header_size != sizeof(struct uc_css_header)) {
DRM_NOTE("CSS header definition mismatch\n");
goto fail;
}
@@ -647,21 +647,36 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
goto fail;
}
 
-   /* Header and uCode will be loaded to WOPCM. Size of the two. */
-   size = 

[Intel-gfx] [PATCH 7/8] drm/i915/huc: Support HuC authentication

[Anusha Srivatsa]

The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.

v2: rebased on top of drm-tip. Changed name format and upped
version 1.7.
v3: changed wait_for_atomic to wait_for
v4: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
and place the prototype in intel_guc.h,correct the comments.
v5: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
AUTHENTICATE_HUC
v6: rebased. Add newline on DRM_ERRORs that already dont have one.
v7: rebased. Replace wait_for with intel_wait_for_register() since
the latter employs sleep optimisations for quick responses- as pointed
out by Chris Wilson.
v8: rebased. Cleanup the intel_guc_auth_huc() by removing checks
already performed in earlier functions. Make comments more descriptive.
v9: rebased. Changed the bias for pinning the HuC object. Move
intel_guc_auth_huc() to intel_huc.c. Change DRM_DEBUGs to DRM_ERRORs
in intel_guc_auth_huc(). Add return status to DRM_ERRORs.

Cc: Chris Wilson 
Cc: Arkadiusz Hiler 
Cc: Michal Wajdeczko 
Tested-by: Xiang Haihao 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Alex Dai 
Signed-off-by: Peter Antoine 
---
 drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
 drivers/gpu/drm/i915/intel_huc.c| 53 +
 drivers/gpu/drm/i915/intel_uc.h |  1 +
 4 files changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index ed1ab40..25691f0 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -505,6 +505,7 @@ enum intel_guc_action {
INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
+   INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
INTEL_GUC_ACTION_LIMIT
 };
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 861c157..c618d11 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -530,6 +530,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
intel_uc_fw_status_repr(guc_fw->fetch_status),
intel_uc_fw_status_repr(guc_fw->load_status));
 
+   intel_guc_auth_huc(dev_priv);
+
if (i915.enable_guc_submission) {
if (i915.guc_log_level >= 0)
gen9_enable_guc_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 7f3774a..22f1207 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -287,3 +287,56 @@ void intel_huc_fini(struct drm_i915_private *dev_priv)
huc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
 }
 
+/**
+ * intel_guc_auth_huc() - authenticate ucode
+ * @dev_priv: the drm_i915_device
+ *
+ * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
+ * authenticate_huc interface.
+ */
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
+{
+   struct intel_guc *guc = _priv->guc;
+   struct intel_huc *huc = _priv->huc;
+   struct i915_vma *vma;
+   int ret;
+   u32 data[2];
+
+   vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
+   PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
+   if (IS_ERR(vma)) {
+   DRM_ERROR("failed to pin huc fw object %d\n",
+   (int)PTR_ERR(vma));
+   return;
+   }
+
+   /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+   I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+   /* Specify auth action and where public signature is. */
+   data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
+   data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset;
+
+   ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
+   if (ret) {
+   DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
+   goto out;
+   }
+
+   /* Check authentication status, it should be done by now */
+   ret = intel_wait_for_register(dev_priv,
+   HUC_STATUS2,
+   HUC_FW_VERIFIED,
+   HUC_FW_VERIFIED,
+   50);
+
+   if (ret) {
+   DRM_ERROR("HuC: Authentication failed %d\n", ret);
+   goto out;
+   }
+
+   DRM_ERROR("HuC Authentication Successful!\n");
+out:
+   i915_vma_unpin(vma);
+}
+
diff --git a/drivers/gpu/drm/i915/intel_uc.h 

[Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support

[Anusha Srivatsa]

The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
is used for both cases.

HuC loading needs to be before GuC loading. The WOPCM setting must
be done early before loading any of them.

v2: rebased on-top of drm-intel-nightly.
removed if(HAS_GUC()) before the guc call. (D.Gordon)
update huc_version number of format.
v3: rebased to drm-intel-nightly, changed the file name format to
match the one in the huc package.
Changed dev->dev_private to to_i915()
v4: moved function back to where it was.
change wait_for_atomic to wait_for.
v5: rebased. Changed the year in the copyright message to reflect
the right year.Correct the comments,remove the unwanted WARN message,
replace drm_gem_object_unreference() with i915_gem_object_put().Make the
prototypes in intel_huc.h non-extern.
v6: rebased. Update the file construction done by HuC. It is similar to
GuC.Adopted the approach used in-
https://patchwork.freedesktop.org/patch/104355/ 
v7: Change dev to dev_priv in macro definition.
Corrected comments.
v8: rebased on top of drm-tip. Updated functions 
intel_huc_load(),intel_huc_init() and
intel_uc_fw_fetch() to accept dev_priv instead of dev. Moved contents
of intel_huc.h to intel_uc.h
v9: change SKL_FW_ to SKL_HUC_FW_. Add intel_ prefix to guc_wopcm_size().
Remove unwanted checks in intel_uc.h. Rename huc_fw in struct intel_huc to
simply fw to avoid redundency.
v10: rebased. Correct comments. Make intel_huc_fini() accept dev_priv instead 
of dev
like intel_huc_init() and intel_huc_load().Move definition to i915_guc_reg.h 
from
intel_uc.h. Clean DMA_CTRL bits after HuC DMA transfer in huc_ucode_xfer()
instead of guc_ucode_xfer(). Add suitable WARNs to give extra info.
v11: rebased. Add proper bias for HuC and make sure there are
asserts on failure by using guc_ggtt_offset_vma(). Introduce
intel_huc.c and remove intel_huc_loader.c since it has functions that
do more than just loading.Correct year in copyright.

Cc: Arkadiusz Hiler 
Cc: Michal Wajdeczko 
Tested-by: Xiang Haihao 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Alex Dai 
Signed-off-by: Peter Antoine 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/Makefile   |   1 +
 drivers/gpu/drm/i915/i915_drv.c |   3 +
 drivers/gpu/drm/i915/i915_drv.h |   2 +
 drivers/gpu/drm/i915/i915_guc_reg.h |   6 +
 drivers/gpu/drm/i915/intel_guc_loader.c |   7 +-
 drivers/gpu/drm/i915/intel_huc.c| 265 
 drivers/gpu/drm/i915/intel_uc.h |  14 ++
 7 files changed, 295 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_huc.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5196509..1ea051a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -57,6 +57,7 @@ i915-y += i915_cmd_parser.o \
 # general-purpose microcontroller (GuC) support
 i915-y += intel_uc.o \
  intel_guc_loader.o \
+ intel_huc.o \
  i915_guc_submission.o
 
 # autogenerated null render state
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4e5ea58..d7a0b49 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -599,6 +599,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_irq;
 
+   intel_huc_init(dev_priv);
intel_guc_init(dev_priv);
 
ret = i915_gem_init(dev_priv);
@@ -627,6 +628,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
i915_gem_fini(dev_priv);
 cleanup_irq:
intel_guc_fini(dev_priv);
+   intel_huc_fini(dev_priv);
drm_irq_uninstall(dev);
intel_teardown_gmbus(dev_priv);
 cleanup_csr:
@@ -1314,6 +1316,7 @@ void i915_driver_unload(struct drm_device *dev)
drain_workqueue(dev_priv->wq);
 
intel_guc_fini(dev_priv);
+   intel_huc_fini(dev_priv);
i915_gem_fini(dev_priv);
intel_fbc_cleanup_cfb(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b84c1d1..2a17df2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2073,6 +2073,7 @@ struct drm_i915_private {
 
struct intel_gvt *gvt;
 
+   struct intel_huc huc;
struct intel_guc guc;
 
struct intel_csr csr;
@@ -2847,6 +2848,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_GUC(dev_priv)  ((dev_priv)->info.has_guc)
 #define HAS_GUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
 #define HAS_GUC_SCHED(dev_priv)(HAS_GUC(dev_priv))
+#define HAS_HUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
 
 #define HAS_RESOURCE_STREAMER(dev_priv) 
((dev_priv)->info.has_resource_streamer)
 
diff --git 

[Intel-gfx] [PATCH 5/8] drm/i915/HuC: Add KBL huC loading Support

[Anusha Srivatsa]

This patch adds the support to load HuC on KBL
Version 2.0

v2: rebased on top of drm-tip. Rename KBL_FW_ to KBL_HUC_FW_
v3: rebased. Remove old checks.

Cc: Michal Wajdeczko 
Cc: Tvrtko Ursulin 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Arkadiusz Hiler 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/intel_huc.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 9d4dd2b..7f3774a 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -48,6 +48,10 @@
 #define SKL_HUC_FW_MINOR 07
 #define SKL_BLD_NUM 1398
 
+#define KBL_HUC_FW_MAJOR 02
+#define KBL_HUC_FW_MINOR 00
+#define KBL_BLD_NUM 1810
+
 #define HUC_FW_PATH(platform, major, minor, bld_num) \
"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
__stringify(minor) "_" __stringify(bld_num) ".bin"
@@ -59,6 +63,11 @@ MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
 #define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
BXT_HUC_FW_MINOR, BXT_BLD_NUM)
 MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
+
+#define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
+   KBL_HUC_FW_MINOR, KBL_BLD_NUM)
+MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
+
 /**
  * huc_ucode_xfer() - DMA's the firmware
  * @dev_priv: the drm_i915_private device
@@ -168,6 +177,10 @@ void intel_huc_init(struct drm_i915_private *dev_priv)
fw_path = I915_BXT_HUC_UCODE;
huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR;
+   } else if (IS_KABYLAKE(dev_priv)) {
+   fw_path = I915_KBL_HUC_UCODE;
+   huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
+   huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
}
 
huc_fw->path = fw_path;
-- 
2.7.4

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[Intel-gfx] [PATCH 6/8] drm/i915/huc: Add debugfs for HuC loading status check

[Anusha Srivatsa]

Add debugfs entry for HuC loading status check.

v2: rebased on top of drm-tip.

Cc: Michal wajdeczko 
Tested-by: Xiang Haihao 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Alex Dai 
Signed-off-by: Peter Antoine 
Reviewed-by: Jeff McGee 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 19fe38e..d99c406 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2325,6 +2325,36 @@ static int i915_llc(struct seq_file *m, void *data)
return 0;
 }
 
+static int i915_huc_load_status_info(struct seq_file *m, void *data)
+{
+   struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   struct intel_uc_fw *huc_fw = _priv->huc.fw;
+
+   if (!HAS_HUC_UCODE(dev_priv))
+   return 0;
+
+   seq_puts(m, "HuC firmware status:\n");
+   seq_printf(m, "\tpath: %s\n", huc_fw->path);
+   seq_printf(m, "\tfetch: %s\n",
+   intel_uc_fw_status_repr(huc_fw->fetch_status));
+   seq_printf(m, "\tload: %s\n",
+   intel_uc_fw_status_repr(huc_fw->load_status));
+   seq_printf(m, "\tversion wanted: %d.%d\n",
+   huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
+   seq_printf(m, "\tversion found: %d.%d\n",
+   huc_fw->major_ver_found, huc_fw->minor_ver_found);
+   seq_printf(m, "\theader: offset is %d; size = %d\n",
+   huc_fw->header_offset, huc_fw->header_size);
+   seq_printf(m, "\tuCode: offset is %d; size = %d\n",
+   huc_fw->ucode_offset, huc_fw->ucode_size);
+   seq_printf(m, "\tRSA: offset is %d; size = %d\n",
+   huc_fw->rsa_offset, huc_fw->rsa_size);
+
+   seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
+
+   return 0;
+}
+
 static int i915_guc_load_status_info(struct seq_file *m, void *data)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4553,6 +4583,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_guc_info", i915_guc_info, 0},
{"i915_guc_load_status", i915_guc_load_status_info, 0},
{"i915_guc_log_dump", i915_guc_log_dump, 0},
+   {"i915_huc_load_status", i915_huc_load_status_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
{"i915_drpc_info", i915_drpc_info, 0},
-- 
2.7.4

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[Intel-gfx] [PATCH 4/8] drm/i915/huc: Add BXT HuC Loading Support

[Anusha Srivatsa]

This patch adds the HuC Loading for the BXT by using
the updated file construction.

Version 1.7 of the HuC firmware.

v2: rebased on to top drm-tip. Rename BXT_FW_MAJOR to BXT_HUC_FW_

Cc: Micha Wajdeczko 
Cc: Tvrtko Ursulin 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Arkadiusz Hiler 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/intel_huc.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index d567721..9d4dd2b 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -40,6 +40,10 @@
  * Note that HuC firmware loading must be done before GuC loading.
  */
 
+#define BXT_HUC_FW_MAJOR 01
+#define BXT_HUC_FW_MINOR 07
+#define BXT_BLD_NUM 1398
+
 #define SKL_HUC_FW_MAJOR 01
 #define SKL_HUC_FW_MINOR 07
 #define SKL_BLD_NUM 1398
@@ -52,6 +56,9 @@
SKL_HUC_FW_MINOR, SKL_BLD_NUM)
 MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
 
+#define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
+   BXT_HUC_FW_MINOR, BXT_BLD_NUM)
+MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
 /**
  * huc_ucode_xfer() - DMA's the firmware
  * @dev_priv: the drm_i915_private device
@@ -157,6 +164,10 @@ void intel_huc_init(struct drm_i915_private *dev_priv)
fw_path = I915_SKL_HUC_UCODE;
huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
+   } else if (IS_BROXTON(dev_priv)) {
+   fw_path = I915_BXT_HUC_UCODE;
+   huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR;
+   huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR;
}
 
huc_fw->path = fw_path;
-- 
2.7.4

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[Intel-gfx] [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general

[Anusha Srivatsa]

Rename some of the GuC fw loading code to make them more general. We
will utilise them for HuC loading as well.
 s/intel_guc_fw/intel_uc_fw/g
 s/GUC_FIRMWARE/INTEL_UC_FIRMWARE/g

Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
same purpose.

v2: rebased on top of nightly.
reapplied the search/replace as upstream code as changed.
v3: removed G from messages in shared fw fetch function.
v4: rebased.Updated dev to dev_priv in intel_guc_setup(), guc_fw_getch()
and intel_guc_init().
v5: rebased. Remove uint32_t fw_type to patch 2. Add INTEL_ prefix for
fields in enum intel_uc_fw_status. Remove uc_dev field since its never
used.Rename uc_fw to just fw and guc_fw to fw to avoid redundency.
v6: rebased. Remove sections of code that were commented and no longer
required.
v7: rebased. Remove uc_fw_ prefix from path and obj fields
in intel_uc_fw struct as suggested by Michal.
v8: rebased. Add declaration of intel_guc_wopcm_size() in
this patch instead of patch 3.

Cc: Michal Wajdeczko 
Cc: Arkadiusz Hiler 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Alex Dai 
Signed-off-by: Peter Antoine 
Reviewed-by: Arkadiusz Hiler 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_debugfs.c|  12 +--
 drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
 drivers/gpu/drm/i915/intel_guc_loader.c| 156 ++---
 drivers/gpu/drm/i915/intel_uc.h|  37 +++
 4 files changed, 105 insertions(+), 104 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9d7b5a8..19fe38e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2328,7 +2328,7 @@ static int i915_llc(struct seq_file *m, void *data)
 static int i915_guc_load_status_info(struct seq_file *m, void *data)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct intel_guc_fw *guc_fw = _priv->guc.guc_fw;
+   struct intel_uc_fw *guc_fw = _priv->guc.fw;
u32 tmp, i;
 
if (!HAS_GUC_UCODE(dev_priv))
@@ -2336,15 +2336,15 @@ static int i915_guc_load_status_info(struct seq_file 
*m, void *data)
 
seq_printf(m, "GuC firmware status:\n");
seq_printf(m, "\tpath: %s\n",
-   guc_fw->guc_fw_path);
+   guc_fw->path);
seq_printf(m, "\tfetch: %s\n",
-   intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+   intel_uc_fw_status_repr(guc_fw->fetch_status));
seq_printf(m, "\tload: %s\n",
-   intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+   intel_uc_fw_status_repr(guc_fw->load_status));
seq_printf(m, "\tversion wanted: %d.%d\n",
-   guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+   guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
seq_printf(m, "\tversion found: %d.%d\n",
-   guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
+   guc_fw->major_ver_found, guc_fw->minor_ver_found);
seq_printf(m, "\theader: offset is %d; size = %d\n",
guc_fw->header_offset, guc_fw->header_size);
seq_printf(m, "\tuCode: offset is %d; size = %d\n",
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 710fbb9..f0eb62d 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1484,7 +1484,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
struct i915_gem_context *ctx;
u32 data[3];
 
-   if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
gen9_disable_guc_interrupts(dev_priv);
@@ -1511,7 +1511,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
struct i915_gem_context *ctx;
u32 data[3];
 
-   if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
if (i915.guc_log_level >= 0)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 5a6ab87..9071575 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
 MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
 
 /* User-friendly representation of an enum */
-const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
+const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
 {
switch (status) {
-   case GUC_FIRMWARE_FAIL:
+   case 

[Intel-gfx] [PATCH 0/8] HuC Loading Patches

[Anusha Srivatsa]

The patches add HuC loading support. The driver builds a frame level
workload which is stored in the graphics memory. This workload is presented
to HuC for processing. The driver, therefore should first determine if the
HuC is enabled and also read the huC athentication status bit to determine
if HuC was successfully loaded. The GuC is required to authenticate the HuC.
The userspace patches that check for a fully loaded HuC firmware and use it
can be found at:

https://lists.freedesktop.org/archives/libva/2016-September/004554.html
https://lists.freedesktop.org/archives/libva/2016-September/004555.html

More information regarding the HuC, batch commands that configure the
HuC etc can be found at-
https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol02a-commandreference-instructions-huc.pdf
https://www.x.org/docs/intel/CHV/intel-gfx-prm-osrc-chv-bsw-vol10-hevc.pdf

v2: rebased. Changed the code following the review comments.
v3: rebased. Organize code. Move contents of intel_huc.h to intel_uc.h.
Update function intel_huc_load(),intel_huc_init() and intel_uc_fw_fetch()
to accept dev_priv instead of dev.
v4: rebased. Remove intel_is_huc_valid() since it is called onoly once.
Refactor the code to reduce redundency. Remove fiels like uc_dev which
are no longer used.
v5: rebased. Beautify the code- remove comments that no longer hold
good, add newlines etc.
v6: rebased. Remove further redundency. Correct comments. Replace wait_for
with intel_wait_for_register() for optimisation purpose.Make fw_type an enum.
v7: rebased. Rename intel_huc_loader() to intel_huc(). Move intel_guc_auth_huc()
from intel_uc.c to intel_huc.c. Add return values to DRM_ERRORs.

Anusha Srivatsa (8):
  drm/i915/guc: Make the GuC fw loading helper functions general
  drm/i915/huc: Unified css_header struct for GuC and HuC
  drm/i915/huc: Add HuC fw loading support
  drm/i915/huc: Add BXT HuC Loading Support
  drm/i915/HuC: Add KBL huC loading Support
  drm/i915/huc: Add debugfs for HuC loading status check
  drm/i915/huc: Support HuC authentication
  drm/i915/get_params: Add HuC status to getparams

 drivers/gpu/drm/i915/Makefile  |   1 +
 drivers/gpu/drm/i915/i915_debugfs.c|  43 +++-
 drivers/gpu/drm/i915/i915_drv.c|  10 +
 drivers/gpu/drm/i915/i915_drv.h|   2 +
 drivers/gpu/drm/i915/i915_guc_reg.h|   6 +
 drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
 drivers/gpu/drm/i915/intel_guc_fwif.h  |  24 +-
 drivers/gpu/drm/i915/intel_guc_loader.c| 196 +
 drivers/gpu/drm/i915/intel_huc.c   | 342 +
 drivers/gpu/drm/i915/intel_uc.h|  60 +++--
 include/uapi/drm/i915_drm.h|   1 +
 11 files changed, 569 insertions(+), 120 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_huc.c

-- 
2.7.4

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[Intel-gfx] [PATCH 0/8] HuC Loading Patches

[Anusha Srivatsa]

The patches add HuC loading support. The driver builds a frame level
workload which is stored in the graphics memory. This workload is presented
to HuC for processing. The driver, therefore should first determine if the
HuC is enabled and also read the huC athentication status bit to determine
if HuC was successfully loaded. The GuC is required to authenticate the HuC.
The userspace patches that check for a fully loaded HuC firmware and use it
can be found at:

https://lists.freedesktop.org/archives/libva/2016-September/004554.html
https://lists.freedesktop.org/archives/libva/2016-September/004555.html

More information regarding the HuC, batch commands that configure the
HuC etc can be found at-
https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol02a-commandreference-instructions-huc.pdf
https://www.x.org/docs/intel/CHV/intel-gfx-prm-osrc-chv-bsw-vol10-hevc.pdf

v2: rebased. Changed the code following the review comments.
v3: rebased. Organize code. Move contents of intel_huc.h to intel_uc.h.
Update function intel_huc_load(),intel_huc_init() and intel_uc_fw_fetch()
to accept dev_priv instead of dev.
v4: rebased. Remove intel_is_huc_valid() since it is called onoly once.
Refactor the code to reduce redundency. Remove fiels like uc_dev which
are no longer used.
v5: rebased. Beautify the code- remove comments that no longer hold
good, add newlines etc.
v6: rebased. Remove further redundency. Correct comments. Replace wait_for
with intel_wait_for_register() for optimisation purpose.Make fw_type an enum.
v7: rebased. Rename intel_huc_loader() to intel_huc(). Move intel_guc_auth_huc()
from intel_uc.c to intel_huc.c. Add return values to DRM_ERRORs.

Anusha Srivatsa (8):
  drm/i915/guc: Make the GuC fw loading helper functions general
  drm/i915/huc: Unified css_header struct for GuC and HuC
  drm/i915/huc: Add HuC fw loading support
  drm/i915/huc: Add BXT HuC Loading Support
  drm/i915/HuC: Add KBL huC loading Support
  drm/i915/huc: Add debugfs for HuC loading status check
  drm/i915/huc: Support HuC authentication
  drm/i915/get_params: Add HuC status to getparams

 drivers/gpu/drm/i915/Makefile  |   1 +
 drivers/gpu/drm/i915/i915_debugfs.c|  43 +++-
 drivers/gpu/drm/i915/i915_drv.c|  10 +
 drivers/gpu/drm/i915/i915_drv.h|   2 +
 drivers/gpu/drm/i915/i915_guc_reg.h|   6 +
 drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
 drivers/gpu/drm/i915/intel_guc_fwif.h  |  24 +-
 drivers/gpu/drm/i915/intel_guc_loader.c| 196 +
 drivers/gpu/drm/i915/intel_huc.c   | 342 +
 drivers/gpu/drm/i915/intel_uc.h|  60 +++--
 include/uapi/drm/i915_drm.h|   1 +
 11 files changed, 569 insertions(+), 120 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_huc.c

-- 
2.7.4

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[Intel-gfx] [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general

[Anusha Srivatsa]

Rename some of the GuC fw loading code to make them more general. We
will utilise them for HuC loading as well.
 s/intel_guc_fw/intel_uc_fw/g
 s/GUC_FIRMWARE/INTEL_UC_FIRMWARE/g

Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
same purpose.

v2: rebased on top of nightly.
reapplied the search/replace as upstream code as changed.
v3: removed G from messages in shared fw fetch function.
v4: rebased.Updated dev to dev_priv in intel_guc_setup(), guc_fw_getch()
and intel_guc_init().
v5: rebased. Remove uint32_t fw_type to patch 2. Add INTEL_ prefix for
fields in enum intel_uc_fw_status. Remove uc_dev field since its never
used.Rename uc_fw to just fw and guc_fw to fw to avoid redundency.
v6: rebased. Remove sections of code that were commented and no longer
required.
v7: rebased. Remove uc_fw_ prefix from path and obj fields
in intel_uc_fw struct as suggested by Michal.
v8: rebased. Add declaration of intel_guc_wopcm_size() in
this patch instead of patch 3.

Cc: Michal Wajdeczko 
Cc: Arkadiusz Hiler 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Alex Dai 
Signed-off-by: Peter Antoine 
Reviewed-by: Arkadiusz Hiler 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_debugfs.c|  12 +--
 drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
 drivers/gpu/drm/i915/intel_guc_loader.c| 156 ++---
 drivers/gpu/drm/i915/intel_uc.h|  37 +++
 4 files changed, 105 insertions(+), 104 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9d7b5a8..19fe38e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2328,7 +2328,7 @@ static int i915_llc(struct seq_file *m, void *data)
 static int i915_guc_load_status_info(struct seq_file *m, void *data)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct intel_guc_fw *guc_fw = _priv->guc.guc_fw;
+   struct intel_uc_fw *guc_fw = _priv->guc.fw;
u32 tmp, i;
 
if (!HAS_GUC_UCODE(dev_priv))
@@ -2336,15 +2336,15 @@ static int i915_guc_load_status_info(struct seq_file 
*m, void *data)
 
seq_printf(m, "GuC firmware status:\n");
seq_printf(m, "\tpath: %s\n",
-   guc_fw->guc_fw_path);
+   guc_fw->path);
seq_printf(m, "\tfetch: %s\n",
-   intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+   intel_uc_fw_status_repr(guc_fw->fetch_status));
seq_printf(m, "\tload: %s\n",
-   intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+   intel_uc_fw_status_repr(guc_fw->load_status));
seq_printf(m, "\tversion wanted: %d.%d\n",
-   guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+   guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
seq_printf(m, "\tversion found: %d.%d\n",
-   guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
+   guc_fw->major_ver_found, guc_fw->minor_ver_found);
seq_printf(m, "\theader: offset is %d; size = %d\n",
guc_fw->header_offset, guc_fw->header_size);
seq_printf(m, "\tuCode: offset is %d; size = %d\n",
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 710fbb9..f0eb62d 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1484,7 +1484,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
struct i915_gem_context *ctx;
u32 data[3];
 
-   if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
gen9_disable_guc_interrupts(dev_priv);
@@ -1511,7 +1511,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
struct i915_gem_context *ctx;
u32 data[3];
 
-   if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
if (i915.guc_log_level >= 0)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 5a6ab87..9071575 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
 MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
 
 /* User-friendly representation of an enum */
-const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
+const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
 {
switch (status) {
-   case GUC_FIRMWARE_FAIL:
+   case 

Re: [Intel-gfx] [RFC 1/4] x86/platform/intel/iosf_mbi: Add a mutex for punit access

[Ville Syrjälä]

On Fri, Jan 13, 2017 at 05:06:52PM +0100, Hans de Goede wrote:
> Hi,
> 
> On 01/13/2017 10:26 AM, Ville Syrjälä wrote:
> > On Mon, Jan 02, 2017 at 03:21:13PM +0100, Hans de Goede wrote:
> >> Hi,
> >>
> >> On 02-01-17 15:12, Ville Syrjälä wrote:
> >>> On Sun, Jan 01, 2017 at 09:14:00PM +0100, Hans de Goede wrote:
>  The punit on baytrail / cherrytrail systems is not only accessed through
>  the iosf_mbi functions, but also by the i915 code. Add a mutex to protect
>  the punit against simultaneous accesses and 2 functions to lock / unlock
>  this mutex.
> >>>
> >>> I'm not sure which part of punit you're actually trying to protect
> >>> here. Some specific registers?
> >>
> >> The theory I'm going by is that for certain actions / certain requests
> >> we send to the punit, the punit needs to access the (axp288) pmic, to
> >> change (or enable / disable) certain voltages.
> >
> > At least for cpu/display/gt voltages that shouldn't really be the case.
> > The vcc/vnn/vgg rails are controlled via svid, not i2c.
> 
> Are you sure? The ax288 pmic does not have a svid interface, only
> an i2c interface, and AFAICT its buck DCDC converters are used to
> feed all of these.

Yes, looks like you're right. I guess someone didn't want to spend three
pins for svid.

> 
> > It also feels quite hand wavy since the punit could do whatever at
> > any time AFAIK. Eg. if there's some thermal event or something the
> > punit might kick into action. So trying to protect this from the OS
> > side might not be able to avoid these problems entirely. It feels like
> > there really should be some kind of shared hardware/firmware mutex
> > with the punit to arbitrate access to the i2c bus.
> 
> Right, and there is such a mutex (which only gets used on systems
> with an axp288 pmic...) and we are taking this mutex before starting
> an i2c transaction on the pmic i2c bus. But this does not seem to be
> enough. It seems the the punit does not check the mutex before
> certain OS / host triggered actions. I guess it expects the host to
> do this itself.
> 
> Please see my new (non RFC) version of this series I've posted.
> 
> There are at least 2 problems when relying solely on the punit
> pmic i2c bus sempaphore:
> 
> 1) CPU C1 <-> C6 transations happening while the pmic i2c bus
> is being accessed by the host cause the system to hang
> 2) i915 (runtime) suspend resume fails every other attempt
> with timeouts when trying to get a forcewake lock inn i915,
> often followed by a system freeze shortly after this.

Hmm. But forcewake works at other times? That seems quite strange.
Runtime suspend itself shouldn't really do much, and if we're still
poking at the the hw then we haven't really even suspended anything
yet, so having failing forcewake doesn't sounds at all good.

-- 
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Re: [Intel-gfx] [RFC 1/4] x86/platform/intel/iosf_mbi: Add a mutex for punit access

[Hans de Goede]

Hi,

On 01/13/2017 10:26 AM, Ville Syrjälä wrote:

On Mon, Jan 02, 2017 at 03:21:13PM +0100, Hans de Goede wrote:

Hi,

On 02-01-17 15:12, Ville Syrjälä wrote:

On Sun, Jan 01, 2017 at 09:14:00PM +0100, Hans de Goede wrote:

The punit on baytrail / cherrytrail systems is not only accessed through
the iosf_mbi functions, but also by the i915 code. Add a mutex to protect
the punit against simultaneous accesses and 2 functions to lock / unlock
this mutex.


I'm not sure which part of punit you're actually trying to protect
here. Some specific registers?


The theory I'm going by is that for certain actions / certain requests
we send to the punit, the punit needs to access the (axp288) pmic, to
change (or enable / disable) certain voltages.


At least for cpu/display/gt voltages that shouldn't really be the case.
The vcc/vnn/vgg rails are controlled via svid, not i2c.


Are you sure? The ax288 pmic does not have a svid interface, only
an i2c interface, and AFAICT its buck DCDC converters are used to
feed all of these.


It also feels quite hand wavy since the punit could do whatever at
any time AFAIK. Eg. if there's some thermal event or something the
punit might kick into action. So trying to protect this from the OS
side might not be able to avoid these problems entirely. It feels like
there really should be some kind of shared hardware/firmware mutex
with the punit to arbitrate access to the i2c bus.


Right, and there is such a mutex (which only gets used on systems
with an axp288 pmic...) and we are taking this mutex before starting
an i2c transaction on the pmic i2c bus. But this does not seem to be
enough. It seems the the punit does not check the mutex before
certain OS / host triggered actions. I guess it expects the host to
do this itself.

Please see my new (non RFC) version of this series I've posted.

There are at least 2 problems when relying solely on the punit
pmic i2c bus sempaphore:

1) CPU C1 <-> C6 transations happening while the pmic i2c bus
is being accessed by the host cause the system to hang
2) i915 (runtime) suspend resume fails every other attempt
with timeouts when trying to get a forcewake lock inn i915,
often followed by a system freeze shortly after this.

My non RFC version of this patch-set fixes both.

So summarizing yes you are right that there should be some
hardware mutex (there is, and we are already taking it), but
unfortunately that does not seem to be enough, when explicitly
requesting some power state transation, while another driver
is acccessing the pmic i2c bus bad things happen. Adding
some exclusion mechanism here seems to be necessary.

Note that the i2c acccess vs i915 forcewake issues was
first reported by an user who was trying my patches for
fixing pmic i2c access on cht (fixing the semaphore code on
cht) and then noticed a problem with the i915 driver as soon
as the pmic i2c bus was used. He has also confirmed that the
new non RFC version of my patches fix this.

Regards,

Hans


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[Intel-gfx] State of development of X11 driver

[Michael Cronenworth]

Hello,

As you may or may not be aware many distributions are switching from the 
xf86-video-intel driver to the modesetting driver (with Glamor acceleration). 
Debian, Arch, and now Fedora are unhappy that there has not been a stable release of 
the driver in years.


- Have any of the distributions reached out to you in regards to this situation?
- What is the state of the X11 intel driver? Alive? Dead?

Thanks,
Michael
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Re: [Intel-gfx] [PATCH 10/14] drm/i915: Add MIPI_IO WA

[Ville Syrjälä]

On Fri, Jan 13, 2017 at 05:03:33PM +0200, Imre Deak wrote:
> On pe, 2017-01-13 at 09:55 +0200, Jani Nikula wrote:
> > On Thu, 12 Jan 2017, Mika Kahola  wrote:
> > > This is definitely needed to pass igt test on bxt
> > > 
> > > 'gem_exec_suspend --run-subtest basic-S3'
> > > 
> > > Tested-by: Mika Kahola 
> > > 
> > > On Mon, 2017-01-09 at 14:46 +0530, Vidya Srinivas wrote:
> > > > From: Uma Shankar 
> > > > 
> > > > Enable MIPI IO WA for BXT DSI as per bspec.
> > > > 
> > > > Signed-off-by: Uma Shankar 
> > > > ---
> > > >  drivers/gpu/drm/i915/i915_reg.h  | 3 +++
> > > >  drivers/gpu/drm/i915/intel_dsi.c | 9 +
> > > >  2 files changed, 12 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 71b978a..b9d7e98 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -8301,6 +8301,9 @@ enum {
> > > >  #define _BXT_MIPIC_PORT_CTRL   0x6B8C0
> > > >  #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc,
> > > > _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
> > > >  
> > > > +#define BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR  _MMIO(0
> > > > x138090)
> > 
> > Observe that this register is already defined as BXT_P_CR_GT_DISP_PWRON,
> > and already used in intel_dpio_phy.c. It seems to me changing the bits
> > in this register should be hooked at the dpio level.
> > 
> > Imre?
> 
> At least the RMW access for this register would need locking against a
> concurrent access via the DDI encoder enable/disable code?

Full modesets should be serialized by connection_mutex, or perhaps by
some other thing with async modesets. Although I have a feeling that if
we're doing async modeset commits without locks half the driveer is
going to be on fire. Not sure what people are doing/have planned there.

> 
> We should also make sure the IO is turned off during booting/resuming
> if DSI won't be used (and so the DSI disable hook won't be called), see
> the BSpec "Broxton Sequences to Initialize Display". We could do this
> by enabling/disabling the IO via the power well code which would solve
> the locking issue too. This would mean using POWER_DOMAIN_PORT_DSI, or
> adding a new power domain if diverging from the BSpec sequence is a
> problem (would be worth checking with HW people, since AFAICS we've
> been doing this so far).
> 
> Btw, what about the 0x160020, 0x160054 regs? According to BSpec we need
> to program these too in the same sequence.
> 
> --Imre
> 
> > > > +#define  MIPIO_RST_CTRL(1 <<
> > > > 2)
> > > > +
> > > >  #define  DPI_ENABLE(1 << 31)
> > > > /* A + C */
> > > >  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
> > > >  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK  (0xf << 27)
> > > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> > > > b/drivers/gpu/drm/i915/intel_dsi.c
> > > > index a4bda92..9252490 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > > > @@ -366,6 +366,11 @@ static void bxt_dsi_device_ready(struct
> > > > intel_encoder *encoder)
> > > >  
> > > >     DRM_DEBUG_KMS("\n");
> > > >  
> > > > +   /* Add MIPI IO reset programming for modeset */
> > > > +   val = I915_READ(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR);
> > > > +   I915_WRITE(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR,
> > > > +   val | MIPIO_RST_CTRL);
> > > > +
> > > Should we move this WA to intel_dsi_pre_enable() as the counterpart of
> > > this WA is defined intel_dsi_post_disable()?
> > 
> > As I said, this should probably be managed in intel_dpio_phy.c.
> > 
> > And if not, this is BXT specific, and this hunk runs it on everything
> > else too.
> > 
> > BR,
> > Jani.
> > 
> > 
> > > 
> > > >     /* Enable MIPI PHY transparent latch */
> > > >     for_each_dsi_port(port, intel_dsi->ports) {
> > > >     val = I915_READ(BXT_MIPI_PORT_CTRL(port));
> > > > @@ -757,6 +762,10 @@ static void intel_dsi_post_disable(struct
> > > > intel_encoder *encoder,
> > > >     drm_panel_power_off(intel_dsi->panel);
> > > >     msleep(intel_dsi->panel_off_delay);
> > > >  
> > > > +   val = I915_READ(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR);
> > > > +   I915_WRITE(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR,
> > > > +   val & ~MIPIO_RST_CTRL);
> > > > +
> > > >     intel_disable_dsi_pll(encoder);
> > > >  
> > > >     /* Panel Disable over CRC PMIC */
> > 

-- 
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Re: [Intel-gfx] [PATCH 10/14] drm/i915: Add MIPI_IO WA

[Imre Deak]

On pe, 2017-01-13 at 09:55 +0200, Jani Nikula wrote:
> On Thu, 12 Jan 2017, Mika Kahola  wrote:
> > This is definitely needed to pass igt test on bxt
> > 
> > 'gem_exec_suspend --run-subtest basic-S3'
> > 
> > Tested-by: Mika Kahola 
> > 
> > On Mon, 2017-01-09 at 14:46 +0530, Vidya Srinivas wrote:
> > > From: Uma Shankar 
> > > 
> > > Enable MIPI IO WA for BXT DSI as per bspec.
> > > 
> > > Signed-off-by: Uma Shankar 
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h  | 3 +++
> > >  drivers/gpu/drm/i915/intel_dsi.c | 9 +
> > >  2 files changed, 12 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 71b978a..b9d7e98 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -8301,6 +8301,9 @@ enum {
> > >  #define _BXT_MIPIC_PORT_CTRL 0x6B8C0
> > >  #define BXT_MIPI_PORT_CTRL(tc)   _MMIO_MIPI(tc,
> > > _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
> > >  
> > > +#define BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR_MMIO(0
> > > x138090)
> 
> Observe that this register is already defined as BXT_P_CR_GT_DISP_PWRON,
> and already used in intel_dpio_phy.c. It seems to me changing the bits
> in this register should be hooked at the dpio level.
> 
> Imre?

At least the RMW access for this register would need locking against a
concurrent access via the DDI encoder enable/disable code?

We should also make sure the IO is turned off during booting/resuming
if DSI won't be used (and so the DSI disable hook won't be called), see
the BSpec "Broxton Sequences to Initialize Display". We could do this
by enabling/disabling the IO via the power well code which would solve
the locking issue too. This would mean using POWER_DOMAIN_PORT_DSI, or
adding a new power domain if diverging from the BSpec sequence is a
problem (would be worth checking with HW people, since AFAICS we've
been doing this so far).

Btw, what about the 0x160020, 0x160054 regs? According to BSpec we need
to program these too in the same sequence.

--Imre

> > > +#define  MIPIO_RST_CTRL  (1 <<
> > > 2)
> > > +
> > >  #define  DPI_ENABLE  (1 << 31)
> > > /* A + C */
> > >  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT   27
> > >  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK(0xf << 27)
> > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> > > b/drivers/gpu/drm/i915/intel_dsi.c
> > > index a4bda92..9252490 100644
> > > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > > @@ -366,6 +366,11 @@ static void bxt_dsi_device_ready(struct
> > > intel_encoder *encoder)
> > >  
> > >   DRM_DEBUG_KMS("\n");
> > >  
> > > + /* Add MIPI IO reset programming for modeset */
> > > + val = I915_READ(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR);
> > > + I915_WRITE(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR,
> > > + val | MIPIO_RST_CTRL);
> > > +
> > Should we move this WA to intel_dsi_pre_enable() as the counterpart of
> > this WA is defined intel_dsi_post_disable()?
> 
> As I said, this should probably be managed in intel_dpio_phy.c.
> 
> And if not, this is BXT specific, and this hunk runs it on everything
> else too.
> 
> BR,
> Jani.
> 
> 
> > 
> > >   /* Enable MIPI PHY transparent latch */
> > >   for_each_dsi_port(port, intel_dsi->ports) {
> > >   val = I915_READ(BXT_MIPI_PORT_CTRL(port));
> > > @@ -757,6 +762,10 @@ static void intel_dsi_post_disable(struct
> > > intel_encoder *encoder,
> > >   drm_panel_power_off(intel_dsi->panel);
> > >   msleep(intel_dsi->panel_off_delay);
> > >  
> > > + val = I915_READ(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR);
> > > + I915_WRITE(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR,
> > > + val & ~MIPIO_RST_CTRL);
> > > +
> > >   intel_disable_dsi_pll(encoder);
> > >  
> > >   /* Panel Disable over CRC PMIC */
> 
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Re: [Intel-gfx] GPU hang with kernel 4.10rc3

[Juergen Gross]

On 12/01/17 10:21, Chris Wilson wrote:
> On Thu, Jan 12, 2017 at 07:03:25AM +0100, Juergen Gross wrote:
>> On 11/01/17 18:08, Chris Wilson wrote:
>>> On Wed, Jan 11, 2017 at 05:33:34PM +0100, Juergen Gross wrote:
 With kernel 4.10rc3 running as Xen dm0 I get at each boot:

 [   49.213697] [drm] GPU HANG: ecode 7:0:0x3d1d3d3d, in gnome-shell
 [1431], reason: Hang on render ring, action: reset
 [   49.213699] [drm] GPU hangs can indicate a bug anywhere in the entire
 gfx stack, including userspace.
 [   49.213700] [drm] Please file a _new_ bug report on
 bugs.freedesktop.org against DRI -> DRM/Intel
 [   49.213700] [drm] drm/i915 developers can then reassign to the right
 component if it's not a kernel issue.
 [   49.213700] [drm] The gpu crash dump is required to analyze gpu
 hangs, so please always attach it.
 [   49.213701] [drm] GPU crash dump saved to /sys/class/drm/card0/error
 [   49.213755] drm/i915: Resetting chip after gpu hang
 [   60.213769] drm/i915: Resetting chip after gpu hang
 [   71.189737] drm/i915: Resetting chip after gpu hang
 [   82.165747] drm/i915: Resetting chip after gpu hang
 [   93.205727] drm/i915: Resetting chip after gpu hang

 The dump is attached.
>>>
>>> That's a nasty one. The first couple of pages of the batchbuffer appear
>>> to be overwritten. (Full of 0xc2c2c2c2, i.e. probably pixel data.) That
>>> may be a concurrent write by either the GPU or CPU, or we may have
>>> incorrected mapped a set of pages. That it doesn't recovered suggests
>>> that the corruption occurs frequently, probably on every request/batch.
>>
>> I hoped someone would have an idea already.
> 
> Sorry, first report of something like this in a long time (that I can
> remember at least). And the problem is that it can be anything from a
> coherency to a concurrency issue, so no one patch springs to mind.
> Thankfully it appears to be kernel related.
> -Chris
> 

Bisecting took longer than I thought, but I had to cherry pick some
patches and rebase one of them multiple times...

Finally I found the commit to blame: 920cf4194954ec ("drm/i915:
Introduce an internal allocator for disposable private objects")

In case you need me to produce some more data or test a patch
feel free to reach out.


Juergen
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[Intel-gfx] [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general

[Anusha Srivatsa]

Rename some of the GuC fw loading code to make them more general. We
will utilise them for HuC loading as well.
 s/intel_guc_fw/intel_uc_fw/g
 s/GUC_FIRMWARE/INTEL_UC_FIRMWARE/g

Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
same purpose.

v2: rebased on top of nightly.
reapplied the search/replace as upstream code as changed.
v3: removed G from messages in shared fw fetch function.
v4: rebased.Updated dev to dev_priv in intel_guc_setup(), guc_fw_getch()
and intel_guc_init().
v5: rebased. Remove uint32_t fw_type to patch 2. Add INTEL_ prefix for
fields in enum intel_uc_fw_status. Remove uc_dev field since its never
used.Rename uc_fw to just fw and guc_fw to fw to avoid redundency.
v6: rebased. Remove sections of code that were commented and no longer
required.
v7: rebased. Remove uc_fw_ prefix from path and obj fields
in intel_uc_fw struct as suggested by Michal.
v8: rebased. Add declaration of intel_guc_wopcm_size() in
this patch instead of patch 3.

Cc: Michal Wajdeczko 
Cc: Arkadiusz Hiler 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Alex Dai 
Signed-off-by: Peter Antoine 
Reviewed-by: Arkadiusz Hiler 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_debugfs.c|  12 +--
 drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
 drivers/gpu/drm/i915/intel_guc_loader.c| 156 ++---
 drivers/gpu/drm/i915/intel_uc.h|  37 +++
 4 files changed, 105 insertions(+), 104 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9d7b5a8..19fe38e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2328,7 +2328,7 @@ static int i915_llc(struct seq_file *m, void *data)
 static int i915_guc_load_status_info(struct seq_file *m, void *data)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct intel_guc_fw *guc_fw = _priv->guc.guc_fw;
+   struct intel_uc_fw *guc_fw = _priv->guc.fw;
u32 tmp, i;
 
if (!HAS_GUC_UCODE(dev_priv))
@@ -2336,15 +2336,15 @@ static int i915_guc_load_status_info(struct seq_file 
*m, void *data)
 
seq_printf(m, "GuC firmware status:\n");
seq_printf(m, "\tpath: %s\n",
-   guc_fw->guc_fw_path);
+   guc_fw->path);
seq_printf(m, "\tfetch: %s\n",
-   intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+   intel_uc_fw_status_repr(guc_fw->fetch_status));
seq_printf(m, "\tload: %s\n",
-   intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+   intel_uc_fw_status_repr(guc_fw->load_status));
seq_printf(m, "\tversion wanted: %d.%d\n",
-   guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+   guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
seq_printf(m, "\tversion found: %d.%d\n",
-   guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
+   guc_fw->major_ver_found, guc_fw->minor_ver_found);
seq_printf(m, "\theader: offset is %d; size = %d\n",
guc_fw->header_offset, guc_fw->header_size);
seq_printf(m, "\tuCode: offset is %d; size = %d\n",
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 710fbb9..f0eb62d 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1484,7 +1484,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
struct i915_gem_context *ctx;
u32 data[3];
 
-   if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
gen9_disable_guc_interrupts(dev_priv);
@@ -1511,7 +1511,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
struct i915_gem_context *ctx;
u32 data[3];
 
-   if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
if (i915.guc_log_level >= 0)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 5a6ab87..9071575 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
 MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
 
 /* User-friendly representation of an enum */
-const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
+const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
 {
switch (status) {
-   case GUC_FIRMWARE_FAIL:
+   case 

[Intel-gfx] [PATCH 0/8] HuC Loading Patches

[Anusha Srivatsa]

The patches add HuC loading support. The driver builds a frame level
workload which is stored in the graphics memory. This workload is presented
to HuC for processing. The driver, therefore should first determine if the
HuC is enabled and also read the huC athentication status bit to determine
if HuC was successfully loaded. The GuC is required to authenticate the HuC.
The userspace patches that check for a fully loaded HuC firmware and use it
can be found at:

https://lists.freedesktop.org/archives/libva/2016-September/004554.html
https://lists.freedesktop.org/archives/libva/2016-September/004555.html

More information regarding the HuC, batch commands that configure the
HuC etc can be found at-
https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol02a-commandreference-instructions-huc.pdf
https://www.x.org/docs/intel/CHV/intel-gfx-prm-osrc-chv-bsw-vol10-hevc.pdf

v2: rebased. Changed the code following the review comments.
v3: rebased. Organize code. Move contents of intel_huc.h to intel_uc.h.
Update function intel_huc_load(),intel_huc_init() and intel_uc_fw_fetch()
to accept dev_priv instead of dev.
v4: rebased. Remove intel_is_huc_valid() since it is called onoly once.
Refactor the code to reduce redundency. Remove fiels like uc_dev which
are no longer used.
v5: rebased. Beautify the code- remove comments that no longer hold
good, add newlines etc.
v6: rebased. Remove further redundency. Correct comments. Replace wait_for
with intel_wait_for_register() for optimisation purpose.Make fw_type an enum.
v7: rebased. Rename intel_huc_loader() to intel_huc(). Move intel_guc_auth_huc()
from intel_uc.c to intel_huc.c. Add return values to DRM_ERRORs.

Anusha Srivatsa (8):
  drm/i915/guc: Make the GuC fw loading helper functions general
  drm/i915/huc: Unified css_header struct for GuC and HuC
  drm/i915/huc: Add HuC fw loading support
  drm/i915/huc: Add BXT HuC Loading Support
  drm/i915/HuC: Add KBL huC loading Support
  drm/i915/huc: Add debugfs for HuC loading status check
  drm/i915/huc: Support HuC authentication
  drm/i915/get_params: Add HuC status to getparams

 drivers/gpu/drm/i915/Makefile  |   1 +
 drivers/gpu/drm/i915/i915_debugfs.c|  43 +++-
 drivers/gpu/drm/i915/i915_drv.c|  10 +
 drivers/gpu/drm/i915/i915_drv.h|   2 +
 drivers/gpu/drm/i915/i915_guc_reg.h|   6 +
 drivers/gpu/drm/i915/i915_guc_submission.c |   4 +-
 drivers/gpu/drm/i915/intel_guc_fwif.h  |  24 +-
 drivers/gpu/drm/i915/intel_guc_loader.c| 196 +
 drivers/gpu/drm/i915/intel_huc.c   | 342 +
 drivers/gpu/drm/i915/intel_uc.h|  60 +++--
 include/uapi/drm/i915_drm.h|   1 +
 11 files changed, 569 insertions(+), 120 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_huc.c

-- 
2.7.4

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Re: [Intel-gfx] [PATCH 35/37] drm/i915: Live testing for context execution

[Joonas Lahtinen]

On ke, 2017-01-11 at 21:09 +, Chris Wilson wrote:
> Check we can create and execution within a context.
> 
> Signed-off-by: Chris Wilson 



> +static struct i915_vma *
> +gpu_fill_pages(struct i915_vma *vma,
> +    unsigned long first_page,
> +    unsigned int offset_in_page,
> +    unsigned long count,
> +    u32 value)
> +{
> + struct drm_i915_gem_object *obj;
> + const int gen = INTEL_GEN(vma->vm->i915);
> + unsigned long sz = (4*count + 1)*sizeof(u32);
> + u64 offset;
> + u32 *cmd;
> + int err;
> +
> + GEM_BUG_ON(offset_in_page >= PAGE_SIZE);

offset_in_page is a function too...



For future synchronization purposes, maybe document where the below was
cloned from?

> + offset = PAGE_SIZE * first_page + offset_in_page;
> + offset += vma->node.start;
> + for (sz = 0; sz < count; sz++) {
> + if (gen >= 8) {
> + *cmd++ = MI_STORE_DWORD_IMM_GEN4;
> + *cmd++ = lower_32_bits(offset);
> + *cmd++ = upper_32_bits(offset);
> + *cmd++ = value;
> + } else if (gen >= 6) {
> + *cmd++ = MI_STORE_DWORD_IMM_GEN4;
> + *cmd++ = 0;
> + *cmd++ = offset;

GEM_BUG_ON on overflows and so on. In the following branches too. And
maybe be explicit and "= lower_32_bits(offset);"?

> + *cmd++ = value;
> + } else if (gen >= 4) {
> + *cmd++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
> + *cmd++ = 0;
> + *cmd++ = offset;
> + *cmd++ = value;
> + } else {
> + *cmd++ = MI_STORE_DWORD_IMM | 1 << 22;
> + *cmd++ = offset;
> + *cmd++ = value;
> + }
> + offset += PAGE_SIZE;
> + }



> 
> +static int gpu_fill(struct drm_i915_gem_object *obj,
> + struct i915_gem_context *ctx)
> +{
> + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> + const unsigned long npages = obj->base.size >> PAGE_SHIFT;
> + struct i915_address_space *vm = ctx->ppgtt ? >ppgtt->base : 
> >ggtt.base;

vm = &(ctx->ppgtt ?: >ggtt)->base? Or does GCC bork up.

Long line anyway.

> + struct intel_engine_cs *engine = i915->engine[RCS];

rcs_fill as function name (rcs_fill_pages too)?

> + err = i915_gem_object_set_to_gtt_domain(obj, false);

Isn't the object most definitely going to be written by GPU?

> +
> + err = i915_vma_pin(vma, 0, 0, PIN_USER);
> + if (err)
> + return err;
> +
> + GEM_BUG_ON(!IS_ALIGNED(npages, 1024));

Ok, #define time 1024 is a very magicy.

> + for (page = 0; page < npages; page += 1024) {
> + unsigned int v = page / 1024;
> + struct drm_i915_gem_request *rq;
> + struct i915_vma *batch;
> +
> + batch = gpu_fill_pages(vma, page, v*sizeof(u32), 1024, v);
> + if (IS_ERR(batch)) {

err = PTR_ERR(batch);
goto out_unpin;

> + i915_vma_unpin(vma);
> + return PTR_ERR(batch);
> + }
> +
> + rq = i915_gem_request_alloc(engine, ctx);
> + if (IS_ERR(rq)) {
> + i915_vma_unpin(batch);
> + i915_vma_unpin(vma);
> + return PTR_ERR(rq);

goto out_unpin:

> + }
> +
> + i915_switch_context(rq);

GEM_BUG_ON(rq->engine != engine) to help readability.

This all makes me think how strange our internal API actually is.

> +
> + ww_mutex_lock(>resv->lock, NULL);
> + reservation_object_add_excl_fence(obj->resv, >fence);

Wasn't there a patch not to mess with the reservation internals (aka,
wrap it?)

> + ww_mutex_unlock(>resv->lock);
> +
> + __i915_add_request(rq, true);
> + }

I imagine this work submission helper might come in handy as a separate
thing?

> +static int cpu_fill(struct drm_i915_gem_object *obj, u32 value)
> +{
> + const bool has_llc = HAS_LLC(to_i915(obj->base.dev));

I'm not sure what's the benefit compared to having 'i915' here and
HAS_LLC(i915) later. Except making cocci script more complex when we
i915->has_llc.

> + unsigned int n, m;
> + unsigned int need_flush;
> + int err;
> +
> + err = i915_gem_obj_prepare_shmem_write(obj, _flush);

I wonder why we've not changed to bool.

> + if (err)
> > +   return err;
> +
> > +   for (n = 0; n < 1024; n++) {
> > +   u32 *map;
> +
> > +   map = kmap_atomic(i915_gem_object_get_page(obj, n));
> > +   for (m = 0; m < 1024; m++)
> > +   map[m] = value;
> > +   if (!has_llc)
> > +   drm_clflush_virt_range(map, PAGE_SIZE);
> > +   kunmap_atomic(map);
> > +   }
> +
> > +   i915_gem_obj_finish_shmem_access(obj);
> > +   

Re: [Intel-gfx] [PATCH 19/37] drm/i915: Test coherency of and barriers between cache domains

[Chris Wilson]

On Fri, Jan 13, 2017 at 11:44:23AM +, Matthew Auld wrote:
> On 11 January 2017 at 21:09, Chris Wilson  wrote:
> > Write into an object using WB, WC, GTT, and GPU paths and make sure that
> > our internal API is sufficient to ensure coherent reads and writes.
> >
> > Signed-off-by: Chris Wilson 
> > ---
> >  drivers/gpu/drm/i915/i915_gem.c|   1 +
> >  .../gpu/drm/i915/selftests/i915_gem_coherency.c| 355 
> > +
> >  .../gpu/drm/i915/selftests/i915_live_selftests.h   |   1 +
> >  3 files changed, 357 insertions(+)
> >  create mode 100644 drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c 
> > b/drivers/gpu/drm/i915/i915_gem.c
> > index 4a52c5872898..242d894b356e 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -4899,4 +4899,5 @@ i915_gem_object_get_dma_address(struct 
> > drm_i915_gem_object *obj,
> >  #include "selftests/mock_gem_device.c"
> >  #include "selftests/huge_gem_object.c"
> >  #include "selftests/i915_gem_object.c"
> > +#include "selftests/i915_gem_coherency.c"
> >  #endif
> > diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c 
> > b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
> > new file mode 100644
> > index ..3e57b7a3c73f
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
> > @@ -0,0 +1,355 @@
> > +/*
> > + * Copyright © 2017 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the 
> > "Software"),
> > + * to deal in the Software without restriction, including without 
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including the 
> > next
> > + * paragraph) shall be included in all copies or substantial portions of 
> > the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 
> > OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 
> > OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> > DEALINGS
> > + * IN THE SOFTWARE.
> > + *
> > + */
> > +
> > +#include 
> > +
> > +#include "i915_selftest.h"
> > +#include "i915_random.h"
> > +
> > +static int cpu_set(struct drm_i915_gem_object *obj,
> > +  unsigned long offset,
> > +  u32 v)
> > +{
> > +   unsigned int needs_clflush;
> > +   struct page *page;
> > +   typeof(v) *map;
> Are you expecting typeof v to change, so less churn ?

A few times in writing. Mainly my intent was to document that map is the
same type as v to avoid any implicit conversion.

> > +   mutex_lock(>drm.struct_mutex);
> > +   for (over = igt_coherency_mode; over->name; over++) {
> > +   if (!over->set)
> > +   continue;
> > +
> > +   for (write = igt_coherency_mode; write->name; write++) {
> > +   if (!write->set)
> > +   continue;
> > +
> > +   for (read = igt_coherency_mode; read->name; read++) 
> > {
> > +   if (!read->get)
> > +   continue;
> > +
> > +   for_each_prime_number_from(count, 1, 
> > ncachelines) {
> > +   obj = 
> > i915_gem_object_create_internal(i915, PAGE_SIZE);
> > +   if (IS_ERR(obj))
> This looks a little nasty, err may be uninitialised, and even worse it
> looks like the if (obj) check will pass.

I forgot about err being unset. I did mean that if we ran out of memory
here, we just give up. That's probably a bit silly, reporting ENOMEM as
an indication that we didn't actually run all phases and so didn't
complete the test is sensible. It was from the time before it looped
over all combinations of modes, thinking that they would be seperate
tests and this was just a memory exhaustion stopping a repeated test.
-Chris

-- 
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Re: [Intel-gfx] [PATCH 34/37] drm/i915: Test creation of partial VMA

[Joonas Lahtinen]

On ke, 2017-01-11 at 21:09 +, Chris Wilson wrote:
> Mock testing to ensure we can create and lookup partial VMA.
> 
> Signed-off-by: Chris Wilson 



> +static int igt_vma_partial(void *arg)
> +{
> + struct drm_i915_private *i915 = arg;
> + const unsigned int npages = 1021; /* prime! */

Yes, but why this prime?



> + for (loop = 0; loop <= 1; loop++) { /* exercise both create/lookup */

create_not_lookup, no need for comments

> + unsigned int count, nvma;
> +
> + nvma = loop;

nvma = create_not_lookup ? 0 : 1; would make this less cryptic to read.
Compiler shall optimize then.

> + for_each_prime_number_from(sz, 1, npages) {
> + for_each_prime_number_from(offset, 0, npages - sz) {
> + struct i915_ggtt_view view;
> +
> + view.type = I915_GGTT_VIEW_PARTIAL;
> + view.partial.offset_size =
> + offset << INTEL_PARTIAL_SIZE_BITS | (sz 
> - 1);

Could initialize in named manner when declaring?

> +
> + if (sz == npages)
> + view.type = I915_GGTT_VIEW_NORMAL;
> +
> + vma = i915_gem_obj_lookup_or_create_vma(obj, 
> >ggtt.base, );
> + if (IS_ERR(vma)) {
> + err = PTR_ERR(vma);
> + goto err_object;
> + }
> +
> + if (!i915_vma_is_ggtt(vma)) {
> + pr_err("VMA is not in the GGTT!\n");
> + err = -EINVAL;
> + goto err_object;
> + }
> +
> + err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
> + if (err)
> + goto err_object;
> +
> + if (vma->size != sz*PAGE_SIZE) {

Why do you delay this check after pinning?

> + if (view.type != I915_GGTT_VIEW_NORMAL) {
> + if (memcmp(>ggtt_view, , 
> sizeof(view))) {
> + pr_err("VMA mismatch upon 
> creation!\n");

Maybe here.

> + err = -EINVAL;
> + goto err_object;
> + }
> +
> + if (vma->pages == obj->mm.pages) {
> + pr_err("VMA using unrotated 
> object pages!\n");

At least here speak of "partial VMA", not rotated/regular VMA.

> + i915_vma_unpin(vma);
> + nvma++;

num_vma would not be that much worse to type?



From here;

> + if (vma->size != obj->base.size) {
> + pr_err("VMA is wrong size, expected %lu, found %llu\n",
> +    sz*PAGE_SIZE, vma->size);
> + err = -EINVAL;
> + goto err_object;
> + }
> +
> + if (vma->node.size < vma->size) {
> + pr_err("VMA binding too small, expected %llu, found 
> %llu\n",
> +    vma->size, vma->node.size);
> + err = -EINVAL;
> + goto err_object;
> + }
> +
> + if (vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) {
> + pr_err("Not the normal ggtt view! Found %d\n",
> +    vma->ggtt_view.type);
> + err = -EINVAL;
> + goto err_object;
> + }
> +
> + if (vma->pages != obj->mm.pages) {
> + pr_err("VMA not using object pages!\n");
> + err = -EINVAL;
> + goto err_object;
> + }

One big helper function?

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 32/37] drm/i915: Exercise i915_vma_pin/i915_vma_insert

[Chris Wilson]

On Fri, Jan 13, 2017 at 02:49:49PM +0200, Joonas Lahtinen wrote:
> On ke, 2017-01-11 at 21:09 +, Chris Wilson wrote:
> > High-level testing of the struct drm_mm by verifying our handling of
> > weird requests to i915_vma_pin.
> > 
> > Signed-off-by: Chris Wilson 
> 
> 
> 
> > +static int igt_vma_pin1(void *arg)
> > +{
> > +   struct drm_i915_private *i915 = arg;
> > +   const struct pin_mode modes[] = {
> > +   [0] = { 0, PIN_GLOBAL, assert_pin_valid },
> 
> Now that pin_mode is introduced far, use named initializers (especially
> when the array starts with plenty of zeros in the first column). Or at
> the least, make a comment /* size, flags, assert_func */
> 
> 
> 
> > +
> > +   [24] = { 8192, PIN_GLOBAL | PIN_OFFSET_BIAS | 
> > (i915->ggtt.mappable_end - 4096), assert_pin_valid },
> > +
> > +#if !IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
> 
> Better drop the unnecessarily verbose [NN] =, if an another #if section
> is added, it'll be bad. And no real benefit either, inserting a test in
> the middle will be bad too, it's not like we never forget something
> from first iteration.

It was providing some information in the error report, and I was too
lazy to include the appropriate string. Why do you never let me be lazy!
-Chris

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove unused function intel_ddi_get_link_dpll()

[Patchwork]

== Series Details ==

Series: drm/i915: Remove unused function intel_ddi_get_link_dpll()
URL   : https://patchwork.freedesktop.org/series/17963/
State : success

== Summary ==

Series 17963v1 drm/i915: Remove unused function intel_ddi_get_link_dpll()
https://patchwork.freedesktop.org/api/1.0/series/17963/revisions/1/mbox/


fi-bdw-5557u total:246  pass:232  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050 total:246  pass:207  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:246  pass:224  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-t5700 total:82   pass:69   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:246  pass:219  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-ivb-3520m total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770  total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6260u total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hqtotal:246  pass:226  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k total:246  pass:222  dwarn:3   dfail:0   fail:0   skip:21 
fi-skl-6770hqtotal:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2520m total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-snb-2600  total:246  pass:214  dwarn:0   dfail:0   fail:0   skip:32 

ae1fc35150f6aaadf190a8a881adc9aeb78fd7c9 drm-tip: 2017y-01m-13d-00h-42m-24s UTC 
integration manifest
4bccfcb drm/i915: Remove unused function intel_ddi_get_link_dpll()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3510/
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Re: [Intel-gfx] [PATCH 31/37] drm/i915: Test creation of VMA

[Chris Wilson]

On Fri, Jan 13, 2017 at 02:28:54PM +0200, Joonas Lahtinen wrote:
> On ke, 2017-01-11 at 21:09 +, Chris Wilson wrote:
> > Simple test to exercise creation and lookup of VMA within an object.
> > 
> > Signed-off-by: Chris Wilson 
> 
> 
> 
> > +static int vma_create(struct drm_i915_private *i915,
> > +     struct list_head *objects,
> > +     struct list_head *contexts)
> 
> create_vmas?
> 
> 
> 
> > +static int igt_vma_create(void *arg)
> > +{
> > +   I915_SELFTEST_TIMEOUT(end_time);
> > +   LIST_HEAD(objects);
> > +   LIST_HEAD(contexts);
> 
> Looks aesthetically dispelasing ~ messy, LIST_HEADs could go just
> before "int err" as they're not that special?
> 
> > +   struct drm_i915_private *i915 = arg;
> > +   struct drm_i915_gem_object *obj, *on;
> > +   struct i915_gem_context *ctx, *cn;
> > +   unsigned long num_obj, num_ctx;
> > +   unsigned long no, nc;
> > +   int err;
> > +
> > +   no = 0;
> > +   for_each_prime_number(num_obj, 8192) {
> 
> max_prime

s/8192/ULONG_MAX/ are you serious! ;)

> > +   for (; no < num_obj; no++) {
> > +   obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
> > +   if (IS_ERR(obj))
> > +   goto err;
> > +
> > +   list_add(>batch_pool_link, );
> 
> grumble...

Just put on the rose tinted glasses.
 
> > +   }
> > +
> > +   list_for_each_entry_safe(ctx, cn, , link)
> > +   mock_context_close(ctx);
> 
> I'm unsure why exactly here? On the first round it's empty.

Just the order in which I wrote the test and there was no reason to move
it...

> > +
> > +   nc = 0;
> > +   for_each_prime_number(num_ctx, 8192) {
> > +   cond_resched();
> > +   if (signal_pending(current)) {
> > +   err = -EINTR;
> > +   goto err;
> > +   }
> 
> Again something that could be made into a helper maybe, and then used
> in many points? if (igt_exit_point_or_so) return/goto...

> > +   if (time_after(jiffies, end_time)) {
> > +   pr_warn("%s timed out: after %lu objects\n", __func__, 
> > no);
> > +   break;
> > +   }
> 
> Helper too, because it's not important for the testing itself.

Already igt_timeout(timeout, fmt, ...)

I've been contemplating putting the cond_resched/interruptible check
here. The complaint above is good enough justification.

> 
> 
> > +int i915_vma_mock_selftests(void)
> > +{
> > +   static const struct i915_subtest tests[] = {
> > +   SUBTEST(igt_vma_create),
> > +   };
> > +   struct drm_i915_private *i915;
> > +   int err;
> > +
> > +   i915 = mock_gem_device();
> > +   if (!i915)
> > +   return -ENOMEM;
> > +
> > +   mutex_lock(>drm.struct_mutex);
> > +   err = i915_subtests(tests, i915);
> > +   mutex_unlock(>drm.struct_mutex);
> > +
> 
> I'm unclear if i915 should be released, I feel like it should. If not,
> consider renaming mock_gem_device into getterish (but not gibberish).

It was a mistake, i.e. I forgot drm_dev_unref(>drm) here.
-Chris

-- 
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Re: [Intel-gfx] [PATCH 32/37] drm/i915: Exercise i915_vma_pin/i915_vma_insert

[Joonas Lahtinen]

On ke, 2017-01-11 at 21:09 +, Chris Wilson wrote:
> High-level testing of the struct drm_mm by verifying our handling of
> weird requests to i915_vma_pin.
> 
> Signed-off-by: Chris Wilson 



> +static int igt_vma_pin1(void *arg)
> +{
> + struct drm_i915_private *i915 = arg;
> + const struct pin_mode modes[] = {
> + [0] = { 0, PIN_GLOBAL, assert_pin_valid },

Now that pin_mode is introduced far, use named initializers (especially
when the array starts with plenty of zeros in the first column). Or at
the least, make a comment /* size, flags, assert_func */



> +
> + [24] = { 8192, PIN_GLOBAL | PIN_OFFSET_BIAS | 
> (i915->ggtt.mappable_end - 4096), assert_pin_valid },
> +
> +#if !IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)

Better drop the unnecessarily verbose [NN] =, if an another #if section
is added, it'll be bad. And no real benefit either, inserting a test in
the middle will be bad too, it's not like we never forget something
from first iteration.

> + /* Misusing BIAS is a programming error (it is not controllable
> +  * from userspace) so when debugging is enabled, it explodes.
> +  * However, the tests are still quite interesting for checking
> +  * variable start, end and size.
> +  */

Are they ever run? I'd imagine not in the CI at least. Should not hurt
with explanation.

With the array sanitized;

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
-- 
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Re: [Intel-gfx] [PATCH 31/37] drm/i915: Test creation of VMA

[Joonas Lahtinen]

On ke, 2017-01-11 at 21:09 +, Chris Wilson wrote:
> Simple test to exercise creation and lookup of VMA within an object.
> 
> Signed-off-by: Chris Wilson 



> +static int vma_create(struct drm_i915_private *i915,
> +   struct list_head *objects,
> +   struct list_head *contexts)

create_vmas?



> +static int igt_vma_create(void *arg)
> +{
> + I915_SELFTEST_TIMEOUT(end_time);
> + LIST_HEAD(objects);
> + LIST_HEAD(contexts);

Looks aesthetically dispelasing ~ messy, LIST_HEADs could go just
before "int err" as they're not that special?

> + struct drm_i915_private *i915 = arg;
> + struct drm_i915_gem_object *obj, *on;
> + struct i915_gem_context *ctx, *cn;
> + unsigned long num_obj, num_ctx;
> + unsigned long no, nc;
> + int err;
> +
> + no = 0;
> + for_each_prime_number(num_obj, 8192) {

max_prime

> + for (; no < num_obj; no++) {
> + obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
> + if (IS_ERR(obj))
> + goto err;
> +
> + list_add(>batch_pool_link, );

grumble...

> + }
> +
> + list_for_each_entry_safe(ctx, cn, , link)
> + mock_context_close(ctx);

I'm unsure why exactly here? On the first round it's empty.

> +
> + nc = 0;
> + for_each_prime_number(num_ctx, 8192) {
> + cond_resched();
> + if (signal_pending(current)) {
> + err = -EINTR;
> + goto err;
> + }

Again something that could be made into a helper maybe, and then used
in many points? if (igt_exit_point_or_so) return/goto...

> + if (time_after(jiffies, end_time)) {
> + pr_warn("%s timed out: after %lu objects\n", __func__, 
> no);
> + break;
> + }

Helper too, because it's not important for the testing itself.



> +int i915_vma_mock_selftests(void)
> +{
> + static const struct i915_subtest tests[] = {
> + SUBTEST(igt_vma_create),
> + };
> + struct drm_i915_private *i915;
> + int err;
> +
> + i915 = mock_gem_device();
> + if (!i915)
> + return -ENOMEM;
> +
> + mutex_lock(>drm.struct_mutex);
> + err = i915_subtests(tests, i915);
> + mutex_unlock(>drm.struct_mutex);
> +

I'm unclear if i915 should be released, I feel like it should. If not,
consider renaming mock_gem_device into getterish (but not gibberish).

> + return err;
> +}
> +
-- 
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Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH] drm/i915/huc: Support HuC authentication

[Arkadiusz Hiler]

On Thu, Jan 12, 2017 at 08:51:22AM -0800, Anusha Srivatsa wrote:
> From: Peter Antoine 
> 
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
> 
> v2: rebased on top of drm-intel-nightly.
> changed name format and upped version 1.7.
> v3: rebased on top of drm-intel-nightly.
> v4: changed wait_for_automic to wait_for
> v5: rebased.
> v7: rebased.
> v8: rebased.
> v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
> and place the prototype in intel_guc.h,correct the comments.
> v10: rebased.
> v11: rebased.
> v12: rebased on top of drm-tip
> v13: rebased. Moved intel_guc_auth_huc from i915_guc_submission.c
> to intel_uc.c.Update dev to dev_priv in intel_guc_auth_huc().
> Renamed HOST2GUC_ACTION_AUTHENTICATE_HUC TO INTEL_GUC_ACTION_
> AUTHENTICATE_HUC
> v14: rebased.
> v15: rebased. Add newline on DRM_ERRORs that already dont have one.
> v16: rebased. Replace wait_for with intel_wait_for_register() since
> the latter employs sleep optimisations for quick responses- as pointed
> out by Chris Wilson.
> v17: rebased. Cleanup the intel_guc_auth_huc() by removing checks
> already performed in earlier functions. Make comments more descriptive.
> v18: rebased. Changed the bias for pinning the HuC object.Add return
> values with errors.
> 
> Cc: Chris Wilson 
> Cc: Arkadiusz Hiler 
> Cc: Michal Wajdeczko 
> Tested-by: Xiang Haihao 
> Signed-off-by: Anusha Srivatsa 
> Signed-off-by: Alex Dai 
> Signed-off-by: Peter Antoine 
> ---
>  drivers/gpu/drm/i915/intel_guc_fwif.h   |  1 +
>  drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
>  drivers/gpu/drm/i915/intel_uc.c | 55 
> -
>  drivers/gpu/drm/i915/intel_uc.h |  1 +
>  4 files changed, 58 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
> b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index ed1ab40..25691f0 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -505,6 +505,7 @@ enum intel_guc_action {
>   INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
>   INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
>   INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
> + INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
>   INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
>   INTEL_GUC_ACTION_LIMIT
>  };
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
> b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 861c157..c618d11 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -530,6 +530,8 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
>   intel_uc_fw_status_repr(guc_fw->fetch_status),
>   intel_uc_fw_status_repr(guc_fw->load_status));
>  
> + intel_guc_auth_huc(dev_priv);
> +
>   if (i915.enable_guc_submission) {
>   if (i915.guc_log_level >= 0)
>   gen9_enable_guc_interrupts(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index c6be352..8f95441 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -46,7 +46,6 @@ static bool intel_guc_recv(struct intel_guc *guc, u32 
> *status)
>  int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
>  {
>   struct drm_i915_private *dev_priv = guc_to_i915(guc);
> - u32 status;

Why have you removed this variable? It won't even compile.

Cheers,
Arek

>   int i;
>   int ret;
>  
> @@ -140,3 +139,57 @@ int intel_guc_log_control(struct intel_guc *guc, u32 
> control_val)
>  
>   return intel_guc_send(guc, action, ARRAY_SIZE(action));
>  }
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[Intel-gfx] [PATCH] drm/i915: Remove unused function intel_ddi_get_link_dpll()

[Ander Conselvan de Oliveira]

The function intel_ddi_get_link_dpll() was added in f169660ed4e5
("drm/i915/dp: Add a standalone function to obtain shared dpll for
HSW/BDW/SKL/BXT") to "allow for the implementation of a platform
neutral upfront link training function", but such implementation
never landed.

So remove that function and clean up the exported shared DPLL interface.

Fixes: f169660ed4e5 ("drm/i915/dp: Add a standalone function to obtain
shared dpll for HSW/BDW/SKL/BXT")
Cc: Durgadoss R 
Cc: Manasi Navare 
Cc: Jim Bride 
Cc: Rodrigo Vivi 
Cc: Daniel Vetter 
Cc: Jani Nikula 
Cc: intel-gfx@lists.freedesktop.org
Signed-off-by: Ander Conselvan de Oliveira 


--

I omitted "Cc:  # v4.9+" from dim fixes output,
since this just deletes dead code.
---
 drivers/gpu/drm/i915/intel_ddi.c  | 39 --
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 52 ++-
 drivers/gpu/drm/i915/intel_dpll_mgr.h | 16 ---
 3 files changed, 8 insertions(+), 99 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 66b367d..3eba5bf 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2126,45 +2126,6 @@ intel_ddi_init_hdmi_connector(struct intel_digital_port 
*intel_dig_port)
return connector;
 }
 
-struct intel_shared_dpll *
-intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int clock)
-{
-   struct intel_connector *connector = intel_dp->attached_connector;
-   struct intel_encoder *encoder = connector->encoder;
-   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-   struct intel_shared_dpll *pll = NULL;
-   struct intel_shared_dpll_state tmp_pll_state;
-   enum intel_dpll_id dpll_id;
-
-   if (IS_GEN9_LP(dev_priv)) {
-   dpll_id =  (enum intel_dpll_id)dig_port->port;
-   /*
-* Select the required PLL. This works for platforms where
-* there is no shared DPLL.
-*/
-   pll = _priv->shared_dplls[dpll_id];
-   if (WARN_ON(pll->active_mask)) {
-
-   DRM_ERROR("Shared DPLL in use. active_mask:%x\n",
- pll->active_mask);
-   return NULL;
-   }
-   tmp_pll_state = pll->state;
-   if (!bxt_ddi_dp_set_dpll_hw_state(clock,
- >state.hw_state)) {
-   DRM_ERROR("Could not setup DPLL\n");
-   pll->state = tmp_pll_state;
-   return NULL;
-   }
-   } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
-   pll = skl_find_link_pll(dev_priv, clock);
-   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-   pll = hsw_ddi_dp_get_dpll(encoder, clock);
-   }
-   return pll;
-}
-
 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 {
struct intel_digital_port *intel_dig_port;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index c92a255..4388c21 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -42,44 +42,6 @@
  * commit phase.
  */
 
-struct intel_shared_dpll *
-skl_find_link_pll(struct drm_i915_private *dev_priv, int clock)
-{
-   struct intel_shared_dpll *pll = NULL;
-   struct intel_dpll_hw_state dpll_hw_state;
-   enum intel_dpll_id i;
-   bool found = false;
-
-   if (!skl_ddi_dp_set_dpll_hw_state(clock, _hw_state))
-   return pll;
-
-   for (i = DPLL_ID_SKL_DPLL1; i <= DPLL_ID_SKL_DPLL3; i++) {
-   pll = _priv->shared_dplls[i];
-
-   /* Only want to check enabled timings first */
-   if (pll->state.crtc_mask == 0)
-   continue;
-
-   if (memcmp(_hw_state, >state.hw_state,
-  sizeof(pll->state.hw_state)) == 0) {
-   found = true;
-   break;
-   }
-   }
-
-   /* Ok no matching timings, maybe there's a free one? */
-   for (i = DPLL_ID_SKL_DPLL1;
-((found == false) && (i <= DPLL_ID_SKL_DPLL3)); i++) {
-   pll = _priv->shared_dplls[i];
-   if (pll->state.crtc_mask == 0) {
-   pll->state.hw_state = dpll_hw_state;
-   break;
-   }
-   }
-
-   return pll;
-}
-
 static void
 intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
  struct intel_shared_dpll_state *shared_dpll)
@@ -811,8 +773,8 

Re: [Intel-gfx] [RFC 1/4] x86/platform/intel/iosf_mbi: Add a mutex for punit access

[Ville Syrjälä]

On Fri, Jan 13, 2017 at 01:12:15PM +0200, Jarkko Nikula wrote:
> On 01/13/2017 12:51 PM, Ville Syrjälä wrote:
> > On Fri, Jan 13, 2017 at 12:34:54PM +0200, Jarkko Nikula wrote:
> >> On 01/13/2017 11:26 AM, Ville Syrjälä wrote:
> >>> It also feels quite hand wavy since the punit could do whatever at
> >>> any time AFAIK. Eg. if there's some thermal event or something the
> >>> punit might kick into action. So trying to protect this from the OS
> >>> side might not be able to avoid these problems entirely. It feels like
> >>> there really should be some kind of shared hardware/firmware mutex
> >>> with the punit to arbitrate access to the i2c bus.
> >>>
> >> There is an HW semaphore for I2C access. It is implemented in
> >> drivers/i2c/busses/i2c-designware-baytrail.c and another set from Hans
> >> is adding support for Cherrytrail into it.
> >
> > Then why do we need anything else?
> >
>  From this patch: "The punit on baytrail / cherrytrail systems is not 
> only accessed through the iosf_mbi functions, but also by the i915 code."

I don't see how that's relevant at all. Multiple things accessing the
punit concurrently should be perfectly fine as long as they don't frob
the same registers.

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 19/37] drm/i915: Test coherency of and barriers between cache domains

[Matthew Auld]

On 11 January 2017 at 21:09, Chris Wilson  wrote:
> Write into an object using WB, WC, GTT, and GPU paths and make sure that
> our internal API is sufficient to ensure coherent reads and writes.
>
> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/i915_gem.c|   1 +
>  .../gpu/drm/i915/selftests/i915_gem_coherency.c| 355 
> +
>  .../gpu/drm/i915/selftests/i915_live_selftests.h   |   1 +
>  3 files changed, 357 insertions(+)
>  create mode 100644 drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 4a52c5872898..242d894b356e 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4899,4 +4899,5 @@ i915_gem_object_get_dma_address(struct 
> drm_i915_gem_object *obj,
>  #include "selftests/mock_gem_device.c"
>  #include "selftests/huge_gem_object.c"
>  #include "selftests/i915_gem_object.c"
> +#include "selftests/i915_gem_coherency.c"
>  #endif
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c 
> b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
> new file mode 100644
> index ..3e57b7a3c73f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
> @@ -0,0 +1,355 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include 
> +
> +#include "i915_selftest.h"
> +#include "i915_random.h"
> +
> +static int cpu_set(struct drm_i915_gem_object *obj,
> +  unsigned long offset,
> +  u32 v)
> +{
> +   unsigned int needs_clflush;
> +   struct page *page;
> +   typeof(v) *map;
Are you expecting typeof v to change, so less churn ?

> +   int err;
> +
> +   err = i915_gem_obj_prepare_shmem_write(obj, _clflush);
> +   if (err)
> +   return err;
> +
> +   page = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
> +   map = kmap_atomic(page);
> +   if (needs_clflush & CLFLUSH_BEFORE)
> +   clflush(map+offset_in_page(offset) / sizeof(*map));
> +   map[offset_in_page(offset) / sizeof(*map)] = v;
> +   if (needs_clflush & CLFLUSH_AFTER)
> +   clflush(map+offset_in_page(offset) / sizeof(*map));
> +   kunmap_atomic(map);
> +
> +   i915_gem_obj_finish_shmem_access(obj);
> +   return 0;
> +}
> +
> +static int cpu_get(struct drm_i915_gem_object *obj,
> +  unsigned long offset,
> +  u32 *v)
> +{
> +   unsigned int needs_clflush;
> +   struct page *page;
> +   typeof(v) map;
> +   int err;
> +
> +   err = i915_gem_obj_prepare_shmem_read(obj, _clflush);
> +   if (err)
> +   return err;
> +
> +   page = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
> +   map = kmap_atomic(page);
> +   if (needs_clflush & CLFLUSH_BEFORE)
> +   clflush(map+offset_in_page(offset) / sizeof(*map));
> +   *v = map[offset_in_page(offset) / sizeof(*map)];
> +   kunmap_atomic(map);
> +
> +   i915_gem_obj_finish_shmem_access(obj);
> +   return 0;
> +}
> +
> +static int gtt_set(struct drm_i915_gem_object *obj,
> +  unsigned long offset,
> +  u32 v)
> +{
> +   struct i915_vma *vma;
> +   typeof(v) *map;
> +   int err;
> +
> +   err = i915_gem_object_set_to_gtt_domain(obj, true);
> +   if (err)
> +   return err;
> +
> +   vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
> +   if (IS_ERR(vma))
> +   return PTR_ERR(vma);
> +
> +   map = i915_vma_pin_iomap(vma);
> +   i915_vma_unpin(vma);
> +   if (IS_ERR(map))
> +   return PTR_ERR(map);
> +
> +   map[offset / 

Re: [Intel-gfx] Anonymoose ggtt_view_params

[Chris Wilson]

On Fri, Jan 13, 2017 at 11:23:47AM +, Tvrtko Ursulin wrote:
> 
> On 13/01/2017 11:11, Chris Wilson wrote:
> >On Fri, Jan 13, 2017 at 10:59:46AM +, Tvrtko Ursulin wrote:
> >>
> >>On 13/01/2017 10:33, Chris Wilson wrote:
> >>>Ok, ok, this cover note only exists to continue the run on joke of my
> >>>mispellings!
> >>>
> >>>Everything but
> >>>[5/7] drm/i915: Convert i915_ggtt_view to use an anonymous union
> >>>has a r-b, so this is a good time to complain if this is too much of a
> >>>hack.
> >>
> >>If you could polish your clouded crystal ball to see if more view
> >>types might be coming, which then might have a colliding parameters
> >>size and foil the whole idea.
> >>
> >>I do think it is a little bit of hack with a questionable benefit.
> >>And I think I asked a few times if you really see a performance
> >>difference for a few bytes smaller memcmp? Presumably it would be
> >>some test case with a huge number of partial views which could
> >>theoretically maybe show something?
> >
> >It was the doubling code size of i915_vma_compare() that struck me as
> >objectionable.
> 
> Why does this series shrink i915_vma_compare? Was it getting inlined
> in your build? For me it doesn't.

It's inlined for me. From my build, we only maintain the size of the
i915_vma_lookup. Hmm, this might also explain why changing the return of
i915_vma_compare() had significance for your build and not mine. Weird
gcc is weird.
-Chris

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Re: [Intel-gfx] [PATCH v3 5/7] drm/i915: Convert i915_ggtt_view to use an anonymous union

[Joonas Lahtinen]

On pe, 2017-01-13 at 10:33 +, Chris Wilson wrote:
> Reading the ggtt_views is much more pleasant without the extra
> characters from specifying the union (i.e. ggtt_view.partial rather than
> ggtt_view.params.partial). To make this work inside i915_vma_compare()
> with only a single memcmp requires us to ensure that there are no
> uninitialised bytes within each branch of the union (we make sure the
> structs are packed) and we need to store the size of each branch.
> 
> v4: Rewrite changelog and add comments explaining the assert.
> 
> Signed-off-by: Chris Wilson 
> Cc: Daniel Vetter 

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/7] drm/i915: Name the anonymous structs inside i915_ggtt_view

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/7] drm/i915: Name the anonymous structs 
inside i915_ggtt_view
URL   : https://patchwork.freedesktop.org/series/17960/
State : success

== Summary ==

Series 17960v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/17960/revisions/1/mbox/


fi-bdw-5557u total:246  pass:232  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050 total:246  pass:207  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:246  pass:224  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-t5700 total:82   pass:69   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:246  pass:219  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-ivb-3520m total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770  total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6260u total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hqtotal:246  pass:226  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k total:246  pass:222  dwarn:3   dfail:0   fail:0   skip:21 
fi-skl-6770hqtotal:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2520m total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-snb-2600  total:246  pass:214  dwarn:0   dfail:0   fail:0   skip:32 

ae1fc35150f6aaadf190a8a881adc9aeb78fd7c9 drm-tip: 2017y-01m-13d-00h-42m-24s UTC 
integration manifest
dc1bbb4 drm/i915: Eliminate superfluous i915_ggtt_view_normal
35dc25c drm/i915: Eliminate superfluous i915_ggtt_view_rotated
096579b drm/i915: Convert i915_ggtt_view to use an anonymous union
85ed27f drm/i915: Stop clearing i915_ggtt_view
d1c89f0 drm/i915: Compact memcmp in i915_vma_compare()
fde4b74 drm/i915: Mark the ggtt_view structs as packed
cbb3967 drm/i915: Name the anonymous structs inside i915_ggtt_view

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3509/
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Re: [Intel-gfx] Anonymoose ggtt_view_params

[Tvrtko Ursulin]

On 13/01/2017 11:11, Chris Wilson wrote:

On Fri, Jan 13, 2017 at 10:59:46AM +, Tvrtko Ursulin wrote:


On 13/01/2017 10:33, Chris Wilson wrote:

Ok, ok, this cover note only exists to continue the run on joke of my
mispellings!

Everything but
[5/7] drm/i915: Convert i915_ggtt_view to use an anonymous union
has a r-b, so this is a good time to complain if this is too much of a
hack.


If you could polish your clouded crystal ball to see if more view
types might be coming, which then might have a colliding parameters
size and foil the whole idea.

I do think it is a little bit of hack with a questionable benefit.
And I think I asked a few times if you really see a performance
difference for a few bytes smaller memcmp? Presumably it would be
some test case with a huge number of partial views which could
theoretically maybe show something?


It was the doubling code size of i915_vma_compare() that struck me as
objectionable.


Why does this series shrink i915_vma_compare? Was it getting inlined in 
your build? For me it doesn't.



Downside is if we need to revert it would be relatively "churny".


We just split the type into two fields, the enum and size.


Yes realized that a bit later.

Regards,

Tvrtko


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Re: [Intel-gfx] [PATCH 10/14] drm/i915: Add MIPI_IO WA

[Ander Conselvan De Oliveira]

On Fri, 2017-01-13 at 09:55 +0200, Jani Nikula wrote:
> On Thu, 12 Jan 2017, Mika Kahola  wrote:
> > 
> > This is definitely needed to pass igt test on bxt
> > 
> > 'gem_exec_suspend --run-subtest basic-S3'
> > 
> > Tested-by: Mika Kahola 
> > 
> > On Mon, 2017-01-09 at 14:46 +0530, Vidya Srinivas wrote:
> > > 
> > > From: Uma Shankar 
> > > 
> > > Enable MIPI IO WA for BXT DSI as per bspec.
> > > 
> > > Signed-off-by: Uma Shankar 
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h  | 3 +++
> > >  drivers/gpu/drm/i915/intel_dsi.c | 9 +
> > >  2 files changed, 12 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 71b978a..b9d7e98 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -8301,6 +8301,9 @@ enum {
> > >  #define _BXT_MIPIC_PORT_CTRL 0x6B8C0
> > >  #define BXT_MIPI_PORT_CTRL(tc)   _MMIO_MIPI(tc,
> > > _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
> > >  
> > > +#define BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR_MMIO(0
> > > x138090)
> Observe that this register is already defined as BXT_P_CR_GT_DISP_PWRON,
> and already used in intel_dpio_phy.c. It seems to me changing the bits
> in this register should be hooked at the dpio level.

AFAIK this is an uncore register and not exactly part of DPIO. The DPIO phy bits
are power requests that go to the P-Unit, so somewhat similar to power well
enabling. The DSI usage seems orthogonal to the DPIO phys, so I don't think it
makes a lot of sense to do it in intel_dpio_phy.c.

Ander


> 
> Imre?
> 
> > 
> > > 
> > > +#define  MIPIO_RST_CTRL  (1 <<
> > > 2)
> > > +
> > >  #define  DPI_ENABLE  (1 << 31)
> > > /* A + C */
> > >  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT   27
> > >  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK(0xf << 27)
> > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> > > b/drivers/gpu/drm/i915/intel_dsi.c
> > > index a4bda92..9252490 100644
> > > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > > @@ -366,6 +366,11 @@ static void bxt_dsi_device_ready(struct
> > > intel_encoder *encoder)
> > >  
> > >   DRM_DEBUG_KMS("\n");
> > >  
> > > + /* Add MIPI IO reset programming for modeset */
> > > + val = I915_READ(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR);
> > > + I915_WRITE(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR,
> > > + val | MIPIO_RST_CTRL);
> > > +
> > Should we move this WA to intel_dsi_pre_enable() as the counterpart of
> > this WA is defined intel_dsi_post_disable()?
> As I said, this should probably be managed in intel_dpio_phy.c.
> 
> And if not, this is BXT specific, and this hunk runs it on everything
> else too.
> 
> BR,
> Jani.
> 
> 
> > 
> > 
> > > 
> > >   /* Enable MIPI PHY transparent latch */
> > >   for_each_dsi_port(port, intel_dsi->ports) {
> > >   val = I915_READ(BXT_MIPI_PORT_CTRL(port));
> > > @@ -757,6 +762,10 @@ static void intel_dsi_post_disable(struct
> > > intel_encoder *encoder,
> > >   drm_panel_power_off(intel_dsi->panel);
> > >   msleep(intel_dsi->panel_off_delay);
> > >  
> > > + val = I915_READ(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR);
> > > + I915_WRITE(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR,
> > > + val & ~MIPIO_RST_CTRL);
> > > +
> > >   intel_disable_dsi_pll(encoder);
> > >  
> > >   /* Panel Disable over CRC PMIC */
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Re: [Intel-gfx] [PATCH v3 5/7] drm/i915: Convert i915_ggtt_view to use an anonymous union

[Tvrtko Ursulin]

On 13/01/2017 10:33, Chris Wilson wrote:

Reading the ggtt_views is much more pleasant without the extra
characters from specifying the union (i.e. ggtt_view.partial rather than
ggtt_view.params.partial). To make this work inside i915_vma_compare()
with only a single memcmp requires us to ensure that there are no
uninitialised bytes within each branch of the union (we make sure the
structs are packed) and we need to store the size of each branch.

v4: Rewrite changelog and add comments explaining the assert.

Signed-off-by: Chris Wilson 
Cc: Daniel Vetter 
---
 drivers/gpu/drm/i915/i915_debugfs.c  | 20 ++--
 drivers/gpu/drm/i915/i915_gem.c  |  8 
 drivers/gpu/drm/i915/i915_gem_gtt.c  |  9 -
 drivers/gpu/drm/i915/i915_gem_gtt.h  |  2 +-
 drivers/gpu/drm/i915/i915_vma.c  |  9 -
 drivers/gpu/drm/i915/i915_vma.h  |  9 -
 drivers/gpu/drm/i915/intel_display.c |  2 +-
 7 files changed, 32 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index e367f06f5883..da13c4c3aa6b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -167,20 +167,20 @@ describe_obj(struct seq_file *m, struct 
drm_i915_gem_object *obj)

case I915_GGTT_VIEW_PARTIAL:
seq_printf(m, ", partial [%08llx+%x]",
-  vma->ggtt_view.params.partial.offset 
<< PAGE_SHIFT,
-  vma->ggtt_view.params.partial.size 
<< PAGE_SHIFT);
+  vma->ggtt_view.partial.offset << 
PAGE_SHIFT,
+  vma->ggtt_view.partial.size << 
PAGE_SHIFT);
break;

case I915_GGTT_VIEW_ROTATED:
seq_printf(m, ", rotated [(%ux%u, stride=%u, 
offset=%u), (%ux%u, stride=%u, offset=%u)]",
-  
vma->ggtt_view.params.rotated.plane[0].width,
-  
vma->ggtt_view.params.rotated.plane[0].height,
-  
vma->ggtt_view.params.rotated.plane[0].stride,
-  
vma->ggtt_view.params.rotated.plane[0].offset,
-  
vma->ggtt_view.params.rotated.plane[1].width,
-  
vma->ggtt_view.params.rotated.plane[1].height,
-  
vma->ggtt_view.params.rotated.plane[1].stride,
-  
vma->ggtt_view.params.rotated.plane[1].offset);
+  
vma->ggtt_view.rotated.plane[0].width,
+  
vma->ggtt_view.rotated.plane[0].height,
+  
vma->ggtt_view.rotated.plane[0].stride,
+  
vma->ggtt_view.rotated.plane[0].offset,
+  
vma->ggtt_view.rotated.plane[1].width,
+  
vma->ggtt_view.rotated.plane[1].height,
+  
vma->ggtt_view.rotated.plane[1].stride,
+  
vma->ggtt_view.rotated.plane[1].offset);
break;

default:
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f034d8d2dd4c..d8622fd23f5d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1760,10 +1760,10 @@ compute_partial_view(struct drm_i915_gem_object *obj,
chunk = roundup(chunk, tile_row_pages(obj));

view.type = I915_GGTT_VIEW_PARTIAL;
-   view.params.partial.offset = rounddown(page_offset, chunk);
-   view.params.partial.size =
+   view.partial.offset = rounddown(page_offset, chunk);
+   view.partial.size =
min_t(unsigned int, chunk,
- (obj->base.size >> PAGE_SHIFT) - 
view.params.partial.offset);
+ (obj->base.size >> PAGE_SHIFT) - view.partial.offset);

/* If the partial covers the entire object, just create a normal VMA. */
if (chunk >= obj->base.size >> PAGE_SHIFT)
@@ -1879,7 +1879,7 @@ int i915_gem_fault(struct vm_area_struct *area, struct 
vm_fault *vmf)

/* Finally, remap it using the new GTT offset */
ret = remap_io_mapping(area,
-  area->vm_start + (vma->ggtt_view.params.partial.offset 
<< PAGE_SHIFT),
+  area->vm_start + (vma->ggtt_view.partial.offset 
<< PAGE_SHIFT),
   (ggtt->mappable_base + vma->node.start) >> 
PAGE_SHIFT,
   min_t(u64, vma->size, area->vm_end - 
area->vm_start),
  

Re: [Intel-gfx] [RFC 1/4] x86/platform/intel/iosf_mbi: Add a mutex for punit access

[Jarkko Nikula]

On 01/13/2017 12:51 PM, Ville Syrjälä wrote:

On Fri, Jan 13, 2017 at 12:34:54PM +0200, Jarkko Nikula wrote:

On 01/13/2017 11:26 AM, Ville Syrjälä wrote:

It also feels quite hand wavy since the punit could do whatever at
any time AFAIK. Eg. if there's some thermal event or something the
punit might kick into action. So trying to protect this from the OS
side might not be able to avoid these problems entirely. It feels like
there really should be some kind of shared hardware/firmware mutex
with the punit to arbitrate access to the i2c bus.


There is an HW semaphore for I2C access. It is implemented in
drivers/i2c/busses/i2c-designware-baytrail.c and another set from Hans
is adding support for Cherrytrail into it.


Then why do we need anything else?

From this patch: "The punit on baytrail / cherrytrail systems is not 
only accessed through the iosf_mbi functions, but also by the i915 code."


--
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Re: [Intel-gfx] Anonymoose ggtt_view_params

[Chris Wilson]

On Fri, Jan 13, 2017 at 10:59:46AM +, Tvrtko Ursulin wrote:
> 
> On 13/01/2017 10:33, Chris Wilson wrote:
> >Ok, ok, this cover note only exists to continue the run on joke of my
> >mispellings!
> >
> >Everything but
> >[5/7] drm/i915: Convert i915_ggtt_view to use an anonymous union
> >has a r-b, so this is a good time to complain if this is too much of a
> >hack.
> 
> If you could polish your clouded crystal ball to see if more view
> types might be coming, which then might have a colliding parameters
> size and foil the whole idea.
> 
> I do think it is a little bit of hack with a questionable benefit.
> And I think I asked a few times if you really see a performance
> difference for a few bytes smaller memcmp? Presumably it would be
> some test case with a huge number of partial views which could
> theoretically maybe show something?

It was the doubling code size of i915_vma_compare() that struck me as
objectionable.

> Downside is if we need to revert it would be relatively "churny".

We just split the type into two fields, the enum and size.
-Chris

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Re: [Intel-gfx] Anonymoose ggtt_view_params

[Tvrtko Ursulin]

On 13/01/2017 10:33, Chris Wilson wrote:

Ok, ok, this cover note only exists to continue the run on joke of my
mispellings!

Everything but
[5/7] drm/i915: Convert i915_ggtt_view to use an anonymous union
has a r-b, so this is a good time to complain if this is too much of a
hack.


If you could polish your clouded crystal ball to see if more view types 
might be coming, which then might have a colliding parameters size and 
foil the whole idea.


I do think it is a little bit of hack with a questionable benefit. And I 
think I asked a few times if you really see a performance difference for 
a few bytes smaller memcmp? Presumably it would be some test case with a 
huge number of partial views which could theoretically maybe show something?


Downside is if we need to revert it would be relatively "churny".

Regards,

Tvrtko
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Re: [Intel-gfx] [RFC 1/4] x86/platform/intel/iosf_mbi: Add a mutex for punit access

[Ville Syrjälä]

On Fri, Jan 13, 2017 at 12:34:54PM +0200, Jarkko Nikula wrote:
> On 01/13/2017 11:26 AM, Ville Syrjälä wrote:
> > It also feels quite hand wavy since the punit could do whatever at
> > any time AFAIK. Eg. if there's some thermal event or something the
> > punit might kick into action. So trying to protect this from the OS
> > side might not be able to avoid these problems entirely. It feels like
> > there really should be some kind of shared hardware/firmware mutex
> > with the punit to arbitrate access to the i2c bus.
> >
> There is an HW semaphore for I2C access. It is implemented in 
> drivers/i2c/busses/i2c-designware-baytrail.c and another set from Hans 
> is adding support for Cherrytrail into it.

Then why do we need anything else?

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 02/37] drm/i915: Provide a hook for selftests

[Tvrtko Ursulin]

On 13/01/2017 10:22, Chris Wilson wrote:

On Fri, Jan 13, 2017 at 10:12:16AM +, Tvrtko Ursulin wrote:


On 13/01/2017 08:31, Chris Wilson wrote:

On Wed, Jan 11, 2017 at 09:09:02PM +, Chris Wilson wrote:

Some pieces of code are independent of hardware but are very tricky to
exercise through the normal userspace ABI or via debugfs hooks. Being
able to create mock unit tests and execute them through CI is vital.
Start by adding a central point where we can execute unit tests and
a parameter to enable them. This is disabled by default as the
expectation is that these tests will occasionally explode.

To facilitate integration with igt, any parameter beginning with
i915.igt__ is interpreted as a subtest executable independently via
igt/drv_selftest.

Two classes of selftests are recognised: mock unit tests and integration
tests. Mock unit tests are run as soon as the module is loaded, before
the device is probed. At that point there is no driver instantiated and
all hw interactions must be "mocked". This is very useful for writing
universal tests to exercise code not typically run on a broad range of
architectures. Alternatively, you can hook into the live selftests and
run when the device has been instantiated - hw interactions are real.


One problem I'm running into is that i915_selftest_ is a long prefix,
especially when we get to something like i915_selftest_timeout(jiffies,
   "format",
   args);

I'm tempted by /i915_selftest_/igt_/. Thoughts?


Like an overall rename presumably and not just this helper? I thinks
that's fine.


I think .../drm/i915/selftests/ is ok (and so i915_selftest.h), I was
thinking of all the helpers like igt_timeout(), igt_subtests()

Hmm. Otoh, if i915_selftest.h talks all about igt_foo that seems wrong.
.../drm/i915/igt/ ?  Then we'd have #include "igt/i915_gem_object.c"
Not sure if that is as clear as #include "selftests/i915_gem_object.c"

So just the helpers, imo, should be igt_foo(). And maybe split
i915_selftest.h between the test boilerplate and the igt helpers.


Just the helpers sounds fine. i915_selftest.h is small enough I think to 
keep everything in there.


Regards,

Tvrtko
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Re: [Intel-gfx] [RFC 1/4] x86/platform/intel/iosf_mbi: Add a mutex for punit access

[Jarkko Nikula]

On 01/13/2017 11:26 AM, Ville Syrjälä wrote:

It also feels quite hand wavy since the punit could do whatever at
any time AFAIK. Eg. if there's some thermal event or something the
punit might kick into action. So trying to protect this from the OS
side might not be able to avoid these problems entirely. It feels like
there really should be some kind of shared hardware/firmware mutex
with the punit to arbitrate access to the i2c bus.

There is an HW semaphore for I2C access. It is implemented in 
drivers/i2c/busses/i2c-designware-baytrail.c and another set from Hans 
is adding support for Cherrytrail into it.


--
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[Intel-gfx] [PATCH v3 7/7] drm/i915: Eliminate superfluous i915_ggtt_view_normal

[Chris Wilson]

Since commit 058d88c4330f ("drm/i915: Track pinned VMA"), there is only
one user of i915_ggtt_view_normal rodate. Just treat NULL as no special
view in pin_to_display() like everywhere else.

Signed-off-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem.c  | 2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c  | 4 
 drivers/gpu/drm/i915/i915_gem_gtt.h  | 2 --
 drivers/gpu/drm/i915/intel_overlay.c | 3 +--
 4 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d8622fd23f5d..d4c59b53532e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3436,7 +3436,7 @@ i915_gem_object_pin_to_display_plane(struct 
drm_i915_gem_object *obj,
 * try to preserve the existing ABI).
 */
vma = ERR_PTR(-ENOSPC);
-   if (view->type == I915_GGTT_VIEW_NORMAL)
+   if (!view || view->type == I915_GGTT_VIEW_NORMAL)
vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
   PIN_MAPPABLE | PIN_NONBLOCK);
if (IS_ERR(vma)) {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 46e04676e011..d7f2aa82d810 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -103,10 +103,6 @@
 static int
 i915_get_ggtt_vma_pages(struct i915_vma *vma);
 
-const struct i915_ggtt_view i915_ggtt_view_normal = {
-   .type = I915_GGTT_VIEW_NORMAL,
-};
-
 static void gen6_ggtt_invalidate(struct drm_i915_private *dev_priv)
 {
/* Note that as an uncached mmio write, this should flush the
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 2a8b25742d72..4b351a2d812b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -182,8 +182,6 @@ struct i915_ggtt_view {
};
 };
 
-extern const struct i915_ggtt_view i915_ggtt_view_normal;
-
 enum i915_cache_level;
 
 struct i915_vma;
diff --git a/drivers/gpu/drm/i915/intel_overlay.c 
b/drivers/gpu/drm/i915/intel_overlay.c
index 4473a611c664..0608fad7f593 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -811,8 +811,7 @@ static int intel_overlay_do_put_image(struct intel_overlay 
*overlay,
if (ret != 0)
return ret;
 
-   vma = i915_gem_object_pin_to_display_plane(new_bo, 0,
-  _ggtt_view_normal);
+   vma = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL);
if (IS_ERR(vma))
return PTR_ERR(vma);
 
-- 
2.11.0

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[Intel-gfx] [PATCH v3 6/7] drm/i915: Eliminate superfluous i915_ggtt_view_rotated

[Chris Wilson]

It is only being used to clear a struct and set the type, after which it
is overwritten. Since we no longer check the unset bits of the union,
skipping the clear is permissible.

Signed-off-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c  | 3 ---
 drivers/gpu/drm/i915/i915_gem_gtt.h  | 1 -
 drivers/gpu/drm/i915/intel_display.c | 5 ++---
 3 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 06cfd6951a5e..46e04676e011 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -106,9 +106,6 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma);
 const struct i915_ggtt_view i915_ggtt_view_normal = {
.type = I915_GGTT_VIEW_NORMAL,
 };
-const struct i915_ggtt_view i915_ggtt_view_rotated = {
-   .type = I915_GGTT_VIEW_ROTATED,
-};
 
 static void gen6_ggtt_invalidate(struct drm_i915_private *dev_priv)
 {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 560fd8ddaf2c..2a8b25742d72 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -183,7 +183,6 @@ struct i915_ggtt_view {
 };
 
 extern const struct i915_ggtt_view i915_ggtt_view_normal;
-extern const struct i915_ggtt_view i915_ggtt_view_rotated;
 
 enum i915_cache_level;
 
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index f4be20f0198a..f523256ef77c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2137,11 +2137,10 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
const struct drm_framebuffer *fb,
unsigned int rotation)
 {
+   view->type = I915_GGTT_VIEW_NORMAL;
if (drm_rotation_90_or_270(rotation)) {
-   *view = i915_ggtt_view_rotated;
+   view->type = I915_GGTT_VIEW_ROTATED;
view->rotated = to_intel_framebuffer(fb)->rot_info;
-   } else {
-   *view = i915_ggtt_view_normal;
}
 }
 
-- 
2.11.0

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[Intel-gfx] [PATCH v3 5/7] drm/i915: Convert i915_ggtt_view to use an anonymous union

[Chris Wilson]

Reading the ggtt_views is much more pleasant without the extra
characters from specifying the union (i.e. ggtt_view.partial rather than
ggtt_view.params.partial). To make this work inside i915_vma_compare()
with only a single memcmp requires us to ensure that there are no
uninitialised bytes within each branch of the union (we make sure the
structs are packed) and we need to store the size of each branch.

v4: Rewrite changelog and add comments explaining the assert.

Signed-off-by: Chris Wilson 
Cc: Daniel Vetter 
---
 drivers/gpu/drm/i915/i915_debugfs.c  | 20 ++--
 drivers/gpu/drm/i915/i915_gem.c  |  8 
 drivers/gpu/drm/i915/i915_gem_gtt.c  |  9 -
 drivers/gpu/drm/i915/i915_gem_gtt.h  |  2 +-
 drivers/gpu/drm/i915/i915_vma.c  |  9 -
 drivers/gpu/drm/i915/i915_vma.h  |  9 -
 drivers/gpu/drm/i915/intel_display.c |  2 +-
 7 files changed, 32 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index e367f06f5883..da13c4c3aa6b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -167,20 +167,20 @@ describe_obj(struct seq_file *m, struct 
drm_i915_gem_object *obj)
 
case I915_GGTT_VIEW_PARTIAL:
seq_printf(m, ", partial [%08llx+%x]",
-  vma->ggtt_view.params.partial.offset 
<< PAGE_SHIFT,
-  vma->ggtt_view.params.partial.size 
<< PAGE_SHIFT);
+  vma->ggtt_view.partial.offset << 
PAGE_SHIFT,
+  vma->ggtt_view.partial.size << 
PAGE_SHIFT);
break;
 
case I915_GGTT_VIEW_ROTATED:
seq_printf(m, ", rotated [(%ux%u, stride=%u, 
offset=%u), (%ux%u, stride=%u, offset=%u)]",
-  
vma->ggtt_view.params.rotated.plane[0].width,
-  
vma->ggtt_view.params.rotated.plane[0].height,
-  
vma->ggtt_view.params.rotated.plane[0].stride,
-  
vma->ggtt_view.params.rotated.plane[0].offset,
-  
vma->ggtt_view.params.rotated.plane[1].width,
-  
vma->ggtt_view.params.rotated.plane[1].height,
-  
vma->ggtt_view.params.rotated.plane[1].stride,
-  
vma->ggtt_view.params.rotated.plane[1].offset);
+  
vma->ggtt_view.rotated.plane[0].width,
+  
vma->ggtt_view.rotated.plane[0].height,
+  
vma->ggtt_view.rotated.plane[0].stride,
+  
vma->ggtt_view.rotated.plane[0].offset,
+  
vma->ggtt_view.rotated.plane[1].width,
+  
vma->ggtt_view.rotated.plane[1].height,
+  
vma->ggtt_view.rotated.plane[1].stride,
+  
vma->ggtt_view.rotated.plane[1].offset);
break;
 
default:
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f034d8d2dd4c..d8622fd23f5d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1760,10 +1760,10 @@ compute_partial_view(struct drm_i915_gem_object *obj,
chunk = roundup(chunk, tile_row_pages(obj));
 
view.type = I915_GGTT_VIEW_PARTIAL;
-   view.params.partial.offset = rounddown(page_offset, chunk);
-   view.params.partial.size =
+   view.partial.offset = rounddown(page_offset, chunk);
+   view.partial.size =
min_t(unsigned int, chunk,
- (obj->base.size >> PAGE_SHIFT) - 
view.params.partial.offset);
+ (obj->base.size >> PAGE_SHIFT) - view.partial.offset);
 
/* If the partial covers the entire object, just create a normal VMA. */
if (chunk >= obj->base.size >> PAGE_SHIFT)
@@ -1879,7 +1879,7 @@ int i915_gem_fault(struct vm_area_struct *area, struct 
vm_fault *vmf)
 
/* Finally, remap it using the new GTT offset */
ret = remap_io_mapping(area,
-  area->vm_start + 
(vma->ggtt_view.params.partial.offset << PAGE_SHIFT),
+  area->vm_start + (vma->ggtt_view.partial.offset 
<< PAGE_SHIFT),
   (ggtt->mappable_base + vma->node.start) >> 
PAGE_SHIFT,
   min_t(u64, vma->size, area->vm_end - 
area->vm_start),
   >mappable);
diff