[Intel-gfx] [PATCH] drm/i915: Use copy_from_user() in fence copying

There's no good reason to separate the access_ok() from the copy, especially since the access_ok() size is hard-coded instead of using sizeof(). Instead, just use copy_from_user() directly. Fixes: cf6e7bac6357 ("drm/i915: Add support for drm syncobjs") Cc: Jason Ekstrand Cc: Chris Wilson Signed-

[Intel-gfx] [PULL] drm-misc-fixes

Hi Dave, drm-misc-fixes-2017-12-06: Just the connector_iter corner-case regression fix. Enjoy your time off next week! Cheers, Daniel The following changes since commit ae64f9bd1d3621b5e60d7363bc20afb46aede215: Linux 4.15-rc2 (2017-12-03 11:01:47 -0500) are available in the Git repository

[Intel-gfx] [PATCH] Revert "drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk"

From: Radhakrishna Sripada This reverts commit 8f067837c4b713ce2e69be95af7b2a5eb3bd7de8. HSD says "WA withdrawn. It was causing corruption with some images. WA is not strictly necessary since this bug just causes loss of FBC compression with some sizes and images, but doesn't break anything." F

[Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk" (rev2)

== Series Details == Series: Revert "drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk" (rev2) URL : https://patchwork.freedesktop.org/series/33969/ State : failure == Summary == Applying: Revert "drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk" error: Failed to merge in the changes.

[Intel-gfx] [PATCH 2/5] drm/vblank: Restoring vblank counts after device runtime PM events.

The HW frame counter can get reset when devices enters low power states and this messes up any following vblank count updates. So, compute the missed vblank interrupts for that low power state duration using time stamps. This is similar to _crtc_vblank_on() except that it doesn't enable vblank inte

[Intel-gfx] [PATCH 5/5] drm/i915: Use the vblank power domain disallow or disable DC states.

Disable DC states before enabling vblank interrupts and conversely enable DC states after disabling. Since the frame counter may have got reset between disabling and enabling, use drm_crtc_vblank_restore() to compute the missed vblanks. Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 3/5] drm/i915: Use an atomic_t array to track power domain use count.

Convert the power_domains->domain_use_count array that tracks per-domain use count to atomic_t type. This is needed to be able to read/write the use counts outside of the power domain mutex. Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i

[Intel-gfx] [PATCH 1/5] drm/vblank: Do not update vblank counts if vblanks are already disabled.

Updating the vblank counts requires register reads and these reads may not return meaningful values after the vblank interrupts are disabled as the device may go to low power state. An additional change would be to allow the driver to save the vblank counts before entering a low power state, but th

[Intel-gfx] [PATCH 4/5] drm/i915: Introduce a non-blocking power domain for vblank interrupts

When DC states are enabled and PSR is active, the hardware enters DC5/DC6 states resulting in frame counter resets. The frame counter resets mess up the vblank counting logic. So in order to disable DC states when vblank interrupts are required and to disallow DC states when vblanks interrupts are

[Intel-gfx] [RFC i-g-t 1/5] igt_dummyload: Wrap function parameters into struct

The intent of this patch is to clean-up the interface of the spinning batch workload by grouping the parameters used to spawn it into a struct. Cc: Chris Wilson Signed-off-by: Antonio Argenziano --- lib/igt_dummyload.c | 19 +++ lib/igt_dummyload.h | 16 -

[Intel-gfx] [RFC i-g-t 4/5] igt_dummyload: Add preemptible parameter to spin batch

This patch adds a parameter that allows to make the spinning batch pre-emptible by adding an arbitration point to the spinning loop. Cc: Chris Wilson Signed-off-by: Antonio Argenziano --- lib/igt_dummyload.c | 4 ++-- lib/igt_dummyload.h | 1 + lib/igt_gt.c | 3 ++-

[Intel-gfx] [RFC i-g-t 5/5] igt_hang_ctx: Add preemptible parameter

This patch adds a parameter to make the hanging context pre-emptible. Cc: Chris Wilson Signed-off-by: Antonio Argenziano --- lib/igt_gt.c| 4 ++-- lib/igt_gt.h| 1 + tests/drv_hangman.c | 2 +- tests/gem_reset_stats.c | 2 +- tests/gem_softpin.c | 2 +- 5 files c

[Intel-gfx] [RFC i-g-t 2/5] igt_hang_ctx: Wrap parameters into struct

This patch wraps the parameters for the function used to hang a context (igt_hang_ctx) into a struct to cleanup the interface and make it easier to add more parameters. Cc: Chris Wilson Signed-off-by: Antonio Argenziano --- lib/igt_dummyload.c | 25 - lib/igt_gt.c

[Intel-gfx] [RFC i-g-t 3/5] lib/igt_hang_ctx: Use dummyload batch to hang ctx.

To hang a context we were effectively reimplementing a spinning batch and never stopping it. This patch reuses the recursive batch from igt_dummyload to hang a context. Cc: Chris Wilson Signed-off-by: Antonio Argenziano --- lib/igt_dummyload.c | 4 +++- lib/igt_dummyload.h | 2 ++ lib/igt_gt.

[Intel-gfx] [PATCH i-g-t 1/4] lib: copy intel_aub.h from libdrm

No functionality related to aub is provided by libdrm aside from intel_aub.h which somewhat defines the file format. Move the header into this project to ease aub-related development. Signed-off-by: Scott D Phillips --- lib/Makefile.am | 1 - lib/{stubs/drm => }/intel_aub.h | 0

[Intel-gfx] [PATCH i-g-t 3/4] lib/intel_aub: Add new MEM_TRACE commands

The memtrace aub commands are similar to the existing ones, but different. Notably memtrace has commands for register write and poll. Signed-off-by: Scott D Phillips --- lib/intel_aub.h | 26 ++ 1 file changed, 26 insertions(+) diff --git a/lib/intel_aub.h b/lib/intel_au

[Intel-gfx] [PATCH i-g-t v2 4/4] tools/intel_aubdump: Add ability to simulate execlist submission

Newer devices do not have the legacy ring buffer submission model, so aub files generated using that model cannot be handled by some internal tools. The execlist submission modeled by this change is pretty simplistic, using GGTT only and synchronizing after every batch. v2: - Move addr_bits init i

[Intel-gfx] [PATCH igt] igt/perf_pmu: Tweak wait_for_rc6, yet again

Still CI remains obstinate that RC6 is not smoothly incrementing during the sample period. Tweak the wait_for_rc6() to first wait for the initial Evaluation Interval before polling. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- tests/perf_pmu.c | 15 +++ tests/pm_rc6_re

[Intel-gfx] [PATCH i-g-t 2/4] tools/intel_aubdump: Set addr_bits before write_header

write_header() uses addr_bits, so do the initialization earlier. Also set the gen to a non-zero value in case of unknown device, for use by a later patch. Signed-off-by: Scott D Phillips Reviewed-by: Jordan Justen --- tools/aubdump.c | 14 +- 1 file changed, 9 insertions(+), 5 delet

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/vblank: Do not update vblank counts if vblanks are already disabled.

== Series Details == Series: series starting with [1/5] drm/vblank: Do not update vblank counts if vblanks are already disabled. URL : https://patchwork.freedesktop.org/series/34996/ State : failure == Summary == Series 34996v1 series starting with [1/5] drm/vblank: Do not update vblank coun

Re: [Intel-gfx] [RFC i-g-t 4/5] igt_dummyload: Add preemptible parameter to spin batch

Quoting Antonio Argenziano (2017-12-06 23:03:45) > void emit_recursive_batch(igt_spin_t *spin, int fd, igt_spin_opt_t opts); > diff --git a/lib/igt_gt.c b/lib/igt_gt.c > index 9ec3b0f6..48d40e61 100644 > --- a/lib/igt_gt.c > +++ b/lib/igt_gt.c > @@ -293,7 +293,8 @@ igt_hang_t igt_hang_ctx(int fd,

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [RFC,1/5] igt_dummyload: Wrap function parameters into struct

== Series Details == Series: series starting with [RFC,1/5] igt_dummyload: Wrap function parameters into struct URL : https://patchwork.freedesktop.org/series/34997/ State : success == Summary == IGT patchset tested on top of latest successful build 1db12466cb5ad8483cd469753d2e312a62d717b7 me

[Intel-gfx] ✓ Fi.CI.BAT: success for igt/perf_pmu: Tweak wait_for_rc6, yet again

== Series Details == Series: igt/perf_pmu: Tweak wait_for_rc6, yet again URL : https://patchwork.freedesktop.org/series/34998/ State : success == Summary == IGT patchset tested on top of latest successful build 1db12466cb5ad8483cd469753d2e312a62d717b7 meson: build a full dependency for lib_ig

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Introduce a non-blocking power domain for vblank interrupts

On Wed, Dec 06, 2017 at 10:47:40PM +, Dhinakaran Pandiyan wrote: > When DC states are enabled and PSR is active, the hardware enters DC5/DC6 > states resulting in frame counter resets. The frame counter resets mess > up the vblank counting logic. So in order to disable DC states when > vblank i

[Intel-gfx] [PATCH v4 1/9] drm: Fix link-status kerneldoc line lengths

I'm adding some stuff below it and it's killing my editor's vibe. Changes in v2: - Added to the series Changes in v3: - None Changes in v4: - None Cc: Manasi Navare Acked-by: Daniel Vetter Signed-off-by: Sean Paul --- drivers/gpu/drm/drm_connector.c | 9 + 1 file changed, 5 insertions

[Intel-gfx] [PATCH v4 0/9] drm/i915: Implement HDCP

Welcome to version 4 of the patchset. I think we're nearing the finish line (hopefully) now. This set addresses the review feedback from v3. I applied some R-b's from v3 review, and converted others to Cc since other changes were made to the patch, and I didn't want to speak for reviewers. Thanks

[Intel-gfx] [PATCH v4 2/9] drm/i915: Add more control to wait_for routines

This patch adds a little more control to a couple wait_for routines such that we can avoid open-coding read/wait/timeout patterns which: - need the value of the register after the wait_for - run arbitrary operation for the read portion This patch also chooses the correct sleep function (based on

[Intel-gfx] [PATCH v4 3/9] drm: Add Content Protection property

This patch adds a new optional connector property to allow userspace to enable protection over the content it is displaying. This will typically be implemented by the driver using HDCP. The property is a tri-state with the following values: - OFF: Self explanatory, no content protection - DESIRED:

[Intel-gfx] [PATCH v4 7/9] drm/i915: Add function to output Aksv over GMBUS

Once the Aksv is available in the PCH, we need to get it on the wire to the receiver via DDC. The hardware doesn't allow us to read the value directly, so we need to tell GMBUS to source the Aksv internally and send it to the right offset on the receiver. The way we do this is to initiate an index

[Intel-gfx] [PATCH v4 8/9] drm/i915: Implement HDCP for HDMI

This patch adds HDCP support for HDMI connectors by implementing the intel_hdcp_shim. Nothing too special, just a bunch of DDC reads/writes. Changes in v2: - Rebased on drm-intel-next Changes in v3: - Initialize new worker Changes in v4: - Remove SKL_ prefix from most register names (Daniel) - Wr

[Intel-gfx] [PATCH v4 4/9] drm: Add some HDCP related #defines

In preparation for implementing HDCP in i915, add some HDCP related register offsets and defines. The dpcd register offsets will go in drm_dp_helper.h whereas the ddc offsets along with generic HDCP stuff will get stuffed in drm_hdcp.h, which is new. Changes in v2: - drm_hdcp.h gets MIT license (D

[Intel-gfx] [PATCH v4 9/9] drm/i915: Implement HDCP for DisplayPort

This patch adds HDCP support for DisplayPort connectors by implementing the intel_hdcp_shim. Most of this is straightforward read/write from/to DPCD registers. One thing worth pointing out is the Aksv output bit. It wasn't easily separable like it's HDMI counterpart, so it's crammed in with the re

[Intel-gfx] [PATCH v4 5/9] drm/i915: Add HDCP framework + base implementation

This patch adds the framework required to add HDCP support to intel connectors. It implements Aksv loading from fuse, and parts 1/2/3 of the HDCP authentication scheme. Note that without shim implementations, this does not actually implement HDCP. That will come in subsequent patches. Changes in

[Intel-gfx] [PATCH v4 6/9] drm/i915: Make use of indexed write GMBUS feature

This patch enables the indexed write feature of the GMBUS to concatenate 2 consecutive messages into one. The criteria for an indexed write is that both messages are writes, the first is length == 1, and the second is length > 0. The first message is sent out by the GMBUS as the slave command, and

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] lib: copy intel_aub.h from libdrm

== Series Details == Series: series starting with [1/4] lib: copy intel_aub.h from libdrm URL : https://patchwork.freedesktop.org/series/34999/ State : success == Summary == IGT patchset tested on top of latest successful build 1db12466cb5ad8483cd469753d2e312a62d717b7 meson: build a full depen

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Implement HDCP (rev4)

== Series Details == Series: drm/i915: Implement HDCP (rev4) URL : https://patchwork.freedesktop.org/series/34671/ State : failure == Summary == Applying: drm: Fix link-status kerneldoc line lengths error: Failed to merge in the changes. Using index info to reconstruct a base tree... M d

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Implement HDCP (rev4)

On Wed, Dec 6, 2017 at 7:08 PM, Patchwork wrote: > == Series Details == > > Series: drm/i915: Implement HDCP (rev4) > URL : https://patchwork.freedesktop.org/series/34671/ > State : failure > Ah, son of a beesting! I'll rebase on -tip and resend once people have time to provide feedback. Sean

[Intel-gfx] [PATCH v2 2/2] kms_content_protection: Add Content Protection test

Pretty simple test: - initializes the output - clears the content protection property - verifies that it clears - sets the content protection property to desired - verifies that it transitions to enabled Does this for both legacy and atomic. Changes in v2: - Don't check for i915 gen - Skip test i

[Intel-gfx] [PATCH v2 1/2] CONTRIBUTING: Fix spelling mistake and line length

Noticed while I was reading it. Makes for a good first contribution, I guess. Changes in v2: - None Reviewed-by: Petri Latvala Signed-off-by: Sean Paul --- CONTRIBUTING | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/CONTRIBUTING b/CONTRIBUTING index 561c5dd8..ca2ed

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [RFC,1/5] igt_dummyload: Wrap function parameters into struct

== Series Details == Series: series starting with [RFC,1/5] igt_dummyload: Wrap function parameters into struct URL : https://patchwork.freedesktop.org/series/34997/ State : failure == Summary == Test kms_flip: Subgroup wf_vblank: pass -> DMESG-WARN (shard-hsw)

Re: [Intel-gfx] [RFC 0/4] GPU/CPU timestamps correlation for relating OA samples with system events

On Wed, Nov 15, 2017 at 12:13 PM, Sagar Arun Kamble < sagar.a.kam...@intel.com> wrote: > We can compute system time corresponding to GPU timestamp by taking a > reference point (CPU monotonic time, GPU timestamp) and then adding > delta time computed using timecounter/cyclecounter support in kerne

Re: [Intel-gfx] [PATCH v3 04/11] drm/exynos: Use drm_fb_helper_lastclose() and _poll_changed()

2017년 12월 06일 03:24에 Noralf Trønnes 이(가) 쓴 글: > This driver can use drm_fb_helper_lastclose() as its .lastclose callback. > It can also use drm_fb_helper_output_poll_changed() as its > .output_poll_changed callback. > > Cc: Inki Dae > Cc: Joonyoung Shim > Cc: Seung-Woo Kim > Cc: Kyungmin Park

Re: [Intel-gfx] [RFC 0/4] GPU/CPU timestamps correlation for relating OA samples with system events

On Thu, Dec 7, 2017 at 12:48 AM, Robert Bragg wrote: > > at least from what I wrote back then it looks like I was seeing a drift of > a few milliseconds per second on SKL. I vaguely recall it being much worse > given the frequency constants we had for Haswell. > Sorry I didn't actually re-read m

[Intel-gfx] ✓ Fi.CI.IGT: success for igt/perf_pmu: Tweak wait_for_rc6, yet again

== Series Details == Series: igt/perf_pmu: Tweak wait_for_rc6, yet again URL : https://patchwork.freedesktop.org/series/34998/ State : success == Summary == Test kms_cursor_crc: Subgroup cursor-64x64-suspend: pass -> SKIP (shard-snb) fdo#102365 Test pm_rpm:

[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/4] lib: copy intel_aub.h from libdrm

== Series Details == Series: series starting with [1/4] lib: copy intel_aub.h from libdrm URL : https://patchwork.freedesktop.org/series/34999/ State : warning == Summary == Test pm_rc6_residency: Subgroup rc6-accuracy: pass -> SKIP (shard-snb) Test gem_soft

[Intel-gfx] [PATCH 0/3] mmio save restore refine in vgpu switch

Merge switch_mmio_to_vgpu and switch_mmio_to_host, use delta update for mocs save restore, deal host mocs value as fixed, it won't be changed after initialization. These can save vgpu switch time to reduce CPU utilization and improve GPU performance in GVT-g with multi-VMs. Weinan Li (3): drm/i9

[Intel-gfx] [PATCH 1/3] drm/i915/gvt: optimize for vGPU mmio switch

now mmio switch between vGPUs need to switch to host first then to expected vGPU, it waste one time mmio save/restore. r/w mmio usually is time-consuming, and there are so many mocs registers need to save/restore during vGPU switch. Combine the switch_to_host and switch_to_vgpu can reduce 1 time mm

[Intel-gfx] [PATCH 3/3] drm/i915/gvt: load host render mocs once in mocs switch

Load host render mocs registers once for delta update of mocs switch, it reduces mmio read times obviously, then brings performance improvement during multi-vms switch. Signed-off-by: Weinan Li --- drivers/gpu/drm/i915/gvt/render.c | 51 --- 1 file changed, 42

[Intel-gfx] [PATCH 2/3] drm/i915/gvt: refine mocs save restore policy

Save and restore the mocs regs of one VM in GVT-g burning too much CPU utilization. Add LRI command scan to monitor the change of mocs registers, save the state in vreg, and use delta update policy to restore them. It can obviously reduce the MMIO r/w count, and improve the performance of context s

[Intel-gfx] ✗ Fi.CI.BAT: failure for mmio save restore refine in vgpu switch

== Series Details == Series: mmio save restore refine in vgpu switch URL : https://patchwork.freedesktop.org/series/35011/ State : failure == Summary == CHK include/config/kernel.release CHK include/generated/uapi/linux/version.h CHK include/generated/utsrelease.h CHK i

Re: [Intel-gfx] [PATCH v4 9/9] drm/i915: Implement HDCP for DisplayPort

Thanks for handling the reauth req from downstream. you might want to fix the missed single occurance of "//" On Thursday 07 December 2017 05:30 AM, Sean Paul wrote: This patch adds HDCP support for DisplayPort connectors by implementing the intel_hdcp_shim. Most of this is straightforward re

Re: [Intel-gfx] [PATCH v4 8/9] drm/i915: Implement HDCP for HDMI

On Thursday 07 December 2017 05:30 AM, Sean Paul wrote: This patch adds HDCP support for HDMI connectors by implementing the intel_hdcp_shim. Nothing too special, just a bunch of DDC reads/writes. Changes in v2: - Rebased on drm-intel-next Changes in v3: - Initialize new worker Changes in v4:

[Intel-gfx] [PATCH i-g-t] overlay: fix debugfs path when debugfs mounted on path '/debug'

From: Changbin Du It mistakenly set debugfs root path to "/debug/dri", so correct it. Signed-off-by: Changbin Du --- overlay/debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/overlay/debugfs.c b/overlay/debugfs.c index 9f3e5cc..5516949 100644 --- a/overlay/debugfs.c

Re: [Intel-gfx] [PATCH v4 4/9] drm: Add some HDCP related #defines

Looks Good to me. Reviewed-by: Ramalingam C -Ram On Thursday 07 December 2017 05:30 AM, Sean Paul wrote: In preparation for implementing HDCP in i915, add some HDCP related register offsets and defines. The dpcd register offsets will go in drm_dp_helper.h whereas the ddc offsets along with ge

Re: [Intel-gfx] [PATCH v4 5/9] drm/i915: Add HDCP framework + base implementation

As v3 implementation removes the mode set from the path of HDCP state change, IMO that would have been preferred until we have the ville's changes mentioned by daniel. Now once again modeset is brought back :( And have we already thought about holding the modeset lock for 5+ Sec for HDCP a

Re: [Intel-gfx] [PATCH v4 0/9] drm/i915: Implement HDCP

Sean, Could you please share the level of functional testing is done on this code? like with Receiver/Repeaters and port type tested (DP/HDMI/DP over USB TypeC ?) Whether Compliance test is attempted on this code? Thanks -Ram On Thursday 07 December 2017 05:30 AM, Sean Paul wrote: Welcome

[Intel-gfx] ✓ Fi.CI.BAT: success for overlay: fix debugfs path when debugfs mounted on path '/debug'

== Series Details == Series: overlay: fix debugfs path when debugfs mounted on path '/debug' URL : https://patchwork.freedesktop.org/series/35012/ State : success == Summary == IGT patchset tested on top of latest successful build 1db12466cb5ad8483cd469753d2e312a62d717b7 meson: build a full de

[Intel-gfx] [lkp-robot] [lib/rbtree, drm/mm] 3e6e51217d: WARNING:at_lib/stackdepot.c:#depot_save_stack

FYI, we noticed the following commit (built with gcc-7): commit: 3e6e51217dd14dcda10d4bc9a38b1440e2d42c14 ("lib/rbtree,drm/mm: Add rbtree_replace_node_cached()") git://anongit.freedesktop.org/drm-intel topic/core-for-CI in testcase: trinity with following parameters: runtime: 300s tes

<    1   2