[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/1] tools: Update .gitignore

== Series Details == Series: series starting with [1/1] tools: Update .gitignore URL : https://patchwork.freedesktop.org/series/36322/ State : failure == Summary == IGT patchset tested on top of latest successful build d37369c7146a2ceb332592297d311d501c1c748e Revert "build: make meson more

Re: [Intel-gfx] [RFC v2 6/8] drm: Handle fbdev emulation in core

Den 11.01.2018 08.45, skrev Daniel Vetter: On Wed, Jan 10, 2018 at 06:02:38PM +0100, Noralf Trønnes wrote: Den 09.01.2018 11.38, skrev Daniel Vetter: On Wed, Jan 03, 2018 at 11:21:08PM +0100, Noralf Trønnes wrote: Prepare for generic fbdev emulation by letting DRM core work directly with the

Re: [Intel-gfx] [PATCH 06/11] drm/i915/cnl: Add right GMBUS pin number for HDMI on Port F.

Em Sex, 2017-12-22 às 15:18 -0800, Rodrigo Vivi escreveu: > On CNP Pin 3 is for misc of Port F usage depending on the > configuration. For CNL that uses Port F, pin 3 is the one. > > v2: Make it more generic and update commit message. Reviewed-by: Paulo Zanoni > >

Re: [Intel-gfx] [PATCH 6/6] drm/i915: expose rcs topology through query uAPI

On 18/12/2017 15:35, Lionel Landwerlin wrote: With the introduction of asymetric slices in CNL, we cannot rely on asymmetric the previous SUBSLICE_MASK getparam to tell userspace what subslices are available. Here we introduce a more detailed way of querying the Gen's GPU topology that

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/2] tests/perf_pmu: Verify busyness when PMU is enabled after engine got busy (rev3)

== Series Details == Series: series starting with [v2,1/2] tests/perf_pmu: Verify busyness when PMU is enabled after engine got busy (rev3) URL : https://patchwork.freedesktop.org/series/36201/ State : failure == Summary == IGT patchset tested on top of latest successful build

[Intel-gfx] ✗ Fi.CI.BAT: failure for build: make meson more official

== Series Details == Series: build: make meson more official URL : https://patchwork.freedesktop.org/series/36320/ State : failure == Summary == Applying: build: make meson more official Using index info to reconstruct a base tree... M CONTRIBUTING M NEWS M README M

[Intel-gfx] [PATCH] drm/i915/pmu: Initialise our dynamic sysfs attributes for use with lockdep

As we kmalloc our dynamic sysfs attributes, we have to give them an external static lock_class_key for them to use with lockdep. Fixes: 109ec558370f ("drm/i915/pmu: Only enumerate available counters in sysfs") Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin

Re: [Intel-gfx] [PATCH] drm/i915/pmu: Initialise our dynamic sysfs attributes for use with lockdep

On 11/01/2018 14:04, Chris Wilson wrote: As we kmalloc our dynamic sysfs attributes, we have to give them an external static lock_class_key for them to use with lockdep. Fixes: 109ec558370f ("drm/i915/pmu: Only enumerate available counters in sysfs") Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH 02/11] drm/i915/cnl: Add Port F definition.

Em Sex, 2017-12-22 às 15:18 -0800, Rodrigo Vivi escreveu: > Some Cannonlake SKUs will come with a full split between > port A and port E. This will be called port F although it > is not a 6th port, but only a split. I think that a small comment explaining that port F support is still not complete

Re: [Intel-gfx] [PATCH v2] x86/gpu: add CFL to early quirks

On 15.12.2017 23:19, Rodrigo Vivi wrote: > On Fri, Dec 15, 2017 at 04:39:25PM +, Ingo Molnar wrote: >> >> * Lucas De Marchi wrote: >> >>> CFL was missing from intel_early_ids[]. The PCI ID needs to be there to >>> allow the memory region to be stolen, otherwise we

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Reinitialize sink scrambling/TMDS clock ratio on HPD

Regards Shashank On 1/10/2018 9:53 PM, Ville Syrjälä wrote: On Wed, Jan 10, 2018 at 10:07:43AM +0530, Sharma, Shashank wrote: Regards Shashank On 1/9/2018 11:31 PM, Ville Syrjälä wrote: On Thu, Dec 28, 2017 at 08:32:05PM +0530, Sharma, Shashank wrote: On 12/22/2017 11:58 PM, Ville

Re: [Intel-gfx] [PATCH i-g-t] build: make meson more official

On Thu, Jan 11, 2018 at 09:51:40AM +0100, Daniel Vetter wrote: > I also noticed that meson.sh doesn't set the prefix for patch > submission. Fix that (even thought hopefully real soon igt will move > to its own list). > > Cc: Petri Latvala > Cc: Arkadiusz Hiler

Re: [Intel-gfx] [PATCH 1/6] drm/i915: store all subslice masks

On 18/12/2017 15:35, Lionel Landwerlin wrote: Up to now, subslice mask was assumed to be uniform across slices. But starting with Cannonlake, slices can be asymetric (for example slice0 asymmetric, thanks auto spell checker. :) has different number of subslices as slice1+). This change

[Intel-gfx] [PATCH i-g-t 1/2] test/gem_ctx_param - Use the last I915_CONTEXT_PARAM+1 for invalid tests

The invalid-param-[get|set] exploits the last I915_CONTEXT_PARAM + 1, to check for ABI extentsions. However, the last param was set to I915_CONTEXT_PARAM_BANNABLE, so when I915_CONTEXT_PARAM_PRIORITY was added to the next enum, the test started failing. Bugzilla:

Re: [Intel-gfx] [PATCH i-g-t 1/2] test/gem_ctx_param - Use the last I915_CONTEXT_PARAM+1 for invalid tests

> -Original Message- > From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com] > Sent: Thursday, January 11, 2018 1:46 PM > To: Lofstedt, Marta ; intel- > g...@lists.freedesktop.org > Cc: Chris Wilson > Subject: Re: [Intel-gfx]

Re: [Intel-gfx] [PATCH 2/6] drm/i915/debugfs: reuse max slice/subslices already stored in sseu

On 18/12/2017 15:35, Lionel Landwerlin wrote: Now that we have that information in topology fields, let's just reused it. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_debugfs.c | 26 ++ 1 file changed, 10

Re: [Intel-gfx] [PATCH i-g-t] build: make meson more official

On Thu, Jan 11, 2018 at 9:58 AM, Petri Latvala wrote: > On Thu, Jan 11, 2018 at 09:51:40AM +0100, Daniel Vetter wrote: >> I also noticed that meson.sh doesn't set the prefix for patch >> submission. Fix that (even thought hopefully real soon igt will move >> to its own

Re: [Intel-gfx] [PATCH 3/6] drm/i915/debugfs: add rcs topology entry

On 18/12/2017 15:35, Lionel Landwerlin wrote: While the end goal is to make this information available to userspace through a new ioctl, there is no reason we can't display it in a human readable fashion through debugfs. slice0 (subslice_mask=0x7): I'd add a subslice count while at it, since

Re: [Intel-gfx] [PATCH i-g-t 1/2] test/gem_ctx_param - Use the last I915_CONTEXT_PARAM+1 for invalid tests

On 11/01/2018 11:38, Marta Lofstedt wrote: The invalid-param-[get|set] exploits the last I915_CONTEXT_PARAM + 1, to check for ABI extentsions. However, the last param was set to I915_CONTEXT_PARAM_BANNABLE, so when I915_CONTEXT_PARAM_PRIORITY was added to the next enum, the test started

Re: [Intel-gfx] [PATCH 5/6] drm/i915: add query uAPI

On 18/12/2017 15:35, Lionel Landwerlin wrote: There are a number of information that are readable from hardware registers and that we would like to make accessible to userspace. One particular example is the topology of the execution units (how are execution units grouped in subslices and

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Apply headless DMC workaround for CNL

== Series Details == Series: drm/i915: Apply headless DMC workaround for CNL URL : https://patchwork.freedesktop.org/series/36317/ State : success == Summary == Series 36317v1 drm/i915: Apply headless DMC workaround for CNL

Re: [Intel-gfx] [PATCH] drm/i915/scheduler: Assert that we do not have a dep cycle back to request

On Fri, Jan 05, 2018 at 02:13:22PM +, Chris Wilson wrote: > When reprioritising a request, we build a list of its dependencies in > topological order. This should leave our origin request as the first > element in our list, if it moves we have a dependency cycle and severe > breakage. Assert

[Intel-gfx] [PATCH] drm/i915: Apply headless DMC workaround for CNL

From: Tvrtko Ursulin With firmware 1.07 having fixed the state corruption issue, we can enable the headless GT performance workaround for CNL as well. (Equivalent to b68763741aa2 ("drm/i915: Restore GT performance in headless mode with DMC loaded") on other affected

Re: [Intel-gfx] [PATCH 05/27] drm/i915/icl: Show interrupt registers in debugfs

On 10/01/2018 18:49, Paulo Zanoni wrote: Em Qua, 2018-01-10 às 09:02 +, Tvrtko Ursulin escreveu: On 09/01/2018 23:23, Paulo Zanoni wrote: From: Tvrtko Ursulin v2: Update for POR changes. (Daniele Ceraolo Spurio) Signed-off-by: Tvrtko Ursulin

Re: [Intel-gfx] [PATCH i-g-t v2] include inttypes.h for PRI defines

On Wed, Jan 10, 2018 at 05:12:15PM -0500, Mike Frysinger wrote: > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96620 > Signed-off-by: Mike Frysinger Reviewed-by: Petri Latvala # for file in $(git grep -l 'PRI[diuoxX]'); do grep -q inttypes

[Intel-gfx] [PATCH i-g-t 1/1] tools: Update .gitignore

Fixes: 834321a5d76a ("tools: Cannonlake port clock programming") Signed-off-by: Petri Latvala Cc: Mika Kahola --- tools/.gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/.gitignore b/tools/.gitignore index 2e16cb26..2de665a3

Re: [Intel-gfx] [PATCH i-g-t 1/1] tools: Update .gitignore

On Thu, 2018-01-11 at 11:27 +0200, Petri Latvala wrote: > Fixes: 834321a5d76a ("tools: Cannonlake port clock programming") Reviewed-by: Mika Kahola > Signed-off-by: Petri Latvala > Cc: Mika Kahola > --- >  tools/.gitignore

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Ignore TMDS clock limit for DP++ when EDID override is set (rev2)

== Series Details == Series: drm/i915: Ignore TMDS clock limit for DP++ when EDID override is set (rev2) URL : https://patchwork.freedesktop.org/series/35338/ State : failure == Summary == Warning: bzip CI_DRM_3609/shard-glkb6/results32.json.bz2 wasn't in correct JSON format Test

[Intel-gfx] [PATCH i-g-t v2 1/2] tests/perf_pmu: Verify busyness when PMU is enabled after engine got busy

From: Tvrtko Ursulin Make sure busyness is correctly reported when PMU is enabled after the engine is already busy with a single long batch. v2: * Make the sleep unconditional and use scientific notiation for large constants. (Chris Wilson) Signed-off-by: Tvrtko

[Intel-gfx] [PATCH i-g-t v2 2/2] tests/perf_pmu: Exercise busy stats and lite-restore

From: Tvrtko Ursulin While developing a fix for an accounting hole in busy stats we realized lite-restore is a potential edge case which would be interesting to check is properly handled. It is unfortnately quite timing sensitive to hit lite-restore in the fashion test

[Intel-gfx] [PATCH i-g-t] build: make meson more official

I also noticed that meson.sh doesn't set the prefix for patch submission. Fix that (even thought hopefully real soon igt will move to its own list). Cc: Petri Latvala Cc: Arkadiusz Hiler Signed-off-by: Daniel Vetter

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Only enumerate available counters in sysfs (rev3)

== Series Details == Series: drm/i915/pmu: Only enumerate available counters in sysfs (rev3) URL : https://patchwork.freedesktop.org/series/35689/ State : success == Summary == Series 35689v3 drm/i915/pmu: Only enumerate available counters in sysfs

Re: [Intel-gfx] [PATCH] drm/i915/guc: Redefine guc_log_level modparam values

On Thu, 11 Jan 2018 06:52:18 +0100, Sagar Arun Kamble wrote: On 1/10/2018 9:35 PM, Michal Wajdeczko wrote: We used value -1 to indicate "disabled" and values 0..3 to indicate "enabled", but most of our other modparams are using -1 for "auto" mode and 0 for

[Intel-gfx] [PATCH v3] drm/i915/pmu: Only enumerate available counters in sysfs

From: Tvrtko Ursulin Switch over to dynamically creating device attributes, which are in turn used by the perf core to expose available counters in sysfs. This way we do not expose counters which are not avaiable on the current platform, and are so more consistent

Re: [Intel-gfx] [PATCH i-g-t] overlay: Update .gitignore

On Tue, Jan 09, 2018 at 11:19:53PM -0500, Rhys Kidd wrote: > Fixes: 865a47ca ("overlay: parse tracepoints from sysfs to figure out fields' > location") > Signed-off-by: Rhys Kidd Reviewed-by: Petri Latvala And merged, thanks. > --- >

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Ignore TMDS clock limit for DP++ when EDID override is set (rev2)

On Thu, Jan 11, 2018 at 09:54:02AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915: Ignore TMDS clock limit for DP++ when EDID override is set > (rev2) > URL : https://patchwork.freedesktop.org/series/35338/ > State : failure > > == Summary == > > Warning: bzip

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Apply headless DMC workaround for CNL

On 11/01/2018 08:45, Patchwork wrote: == Series Details == Series: drm/i915: Apply headless DMC workaround for CNL URL : https://patchwork.freedesktop.org/series/36317/ State : success == Summary == Series 36317v1 drm/i915: Apply headless DMC workaround for CNL

Re: [Intel-gfx] [PATCH i-g-t v13] tests/kms_frontbuffer_tracking: Including DRRS test coverage

On Wed, Jan 10, 2018 at 08:17:00PM +0530, Lohith BS wrote: > Dynamic Refresh Rate Switch(DRRS) is used to switch the panel's > refresh rate to the lowest vrefresh supported by panel, when frame is > not flipped for more than a Sec. > > In kernel, DRRS uses the front buffer tracking

Re: [Intel-gfx] [PATCH] drm/i915: Apply headless DMC workaround for CNL

On Thu, Jan 11, 2018 at 08:24:17AM +, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > With firmware 1.07 having fixed the state corruption issue, we can enable > the headless GT performance workaround for CNL as well. (Equivalent to > b68763741aa2 ("drm/i915:

Re: [Intel-gfx] [PATCH] drm/i915/guc: Redefine guc_log_level modparam values

On 1/11/2018 2:54 PM, Michal Wajdeczko wrote: On Thu, 11 Jan 2018 06:52:18 +0100, Sagar Arun Kamble wrote: On 1/10/2018 9:35 PM, Michal Wajdeczko wrote: We used value -1 to indicate "disabled" and values 0..3 to indicate "enabled", but most of our other

Re: [Intel-gfx] [PATCH 14/15] drm/i915: Add NV12 as supported format for sprite plane

> -Original Message- > From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com] > Sent: Tuesday, January 9, 2018 3:32 PM > To: Srinivas, Vidya ; intel- > g...@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 14/15] drm/i915: Add NV12 as

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Only enumerate available counters in sysfs (rev3)

On 11/01/2018 09:09, Patchwork wrote: == Series Details == Series: drm/i915/pmu: Only enumerate available counters in sysfs (rev3) URL : https://patchwork.freedesktop.org/series/35689/ State : success == Summary == Series 35689v3 drm/i915/pmu: Only enumerate available counters in sysfs

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Initialise our dynamic sysfs attributes for use with lockdep

== Series Details == Series: drm/i915/pmu: Initialise our dynamic sysfs attributes for use with lockdep URL : https://patchwork.freedesktop.org/series/36337/ State : success == Summary == Series 36337v1 drm/i915/pmu: Initialise our dynamic sysfs attributes for use with lockdep

[Intel-gfx] [PULL] drm-intel-fixes

Hi Dave - Hopefully final drm/i915 fixes for v4.15: - Fix a KASAN reported use after free - Whitelist a register to avoid hangs - GVT fixes BR, Jani. The following changes since commit b2cd1df66037e7c4697c7e40496bf7e4a5e16a2d: Linux 4.15-rc7 (2018-01-07 14:22:41 -0800) are available in the

Re: [Intel-gfx] [PATCH 1/6] drm/i915: store all subslice masks

On 11/01/2018 15:48, Lionel Landwerlin wrote: On 11/01/18 11:12, Tvrtko Ursulin wrote: On 18/12/2017 15:35, Lionel Landwerlin wrote: Up to now, subslice mask was assumed to be uniform across slices. But starting with Cannonlake, slices can be asymetric (for example slice0 asymmetric,

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Ignore TMDS clock limit for DP++ when EDID override is set (rev2)

HI, > -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf > Of Petri Latvala > Sent: torstai 11. tammikuuta 2018 12.02 > To: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Ignore TMDS clock > limit

Re: [Intel-gfx] [PATCH 2/6] drm/i915/debugfs: reuse max slice/subslices already stored in sseu

On 11/01/18 11:21, Tvrtko Ursulin wrote: On 18/12/2017 15:35, Lionel Landwerlin wrote: Now that we have that information in topology fields, let's just reused it. Signed-off-by: Lionel Landwerlin ---   drivers/gpu/drm/i915/i915_debugfs.c | 26

Re: [Intel-gfx] [PATCH 1/6] drm/i915: store all subslice masks

On 11/01/18 11:12, Tvrtko Ursulin wrote: */ +    eu_en = ~I915_READ(GEN8_EU_DISABLE0); +    for (ss = 0; ss < sseu->max_subslices; ss++) +    sseu->eu_mask[ss] = (eu_en >> (8 * ss)) & eu_mask; +    /* Slice1 */ +    sseu->eu_mask[sseu->max_subslices] = (eu_en >> 24) & eu_mask;

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Initialise our dynamic sysfs attributes for use with lockdep

Quoting Patchwork (2018-01-11 14:39:43) > == Series Details == > > Series: drm/i915/pmu: Initialise our dynamic sysfs attributes for use with > lockdep > URL : https://patchwork.freedesktop.org/series/36337/ > State : success > > == Logs == > > For more details see: >

Re: [Intel-gfx] [PATCH 1/6] drm/i915: store all subslice masks

On 11/01/18 11:12, Tvrtko Ursulin wrote: On 18/12/2017 15:35, Lionel Landwerlin wrote: Up to now, subslice mask was assumed to be uniform across slices. But starting with Cannonlake, slices can be asymetric (for example slice0 asymmetric, thanks auto spell checker. :) Done, thanks. has

[Intel-gfx] [PATCH v2 1/2] drm/i915/guc: Redefine guc_log_level modparam values

We used value -1 to indicate "disabled" and values 0..3 to indicate "enabled", but most of our other modparams are using -1 for "auto" mode and 0 for "disable". For consistency let's change our log level values to: -1: auto (depends on platform and Kconfig.debug settings) 0: disabled 1: enabled

[Intel-gfx] [PATCH v2 2/2] drm/i915/guc: Change values for i915_guc_log_control

Today we have format mismatch between read/write operations of i915_guc_log_control entry. For read we return (0, 1..4) that represents disable/verbosity levels, but for write we force user to follow internal structure format (0,1,9,11,13). Let's hide internals from the user and accept same values

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/pmu: Initialise our dynamic sysfs attributes for use with lockdep

== Series Details == Series: drm/i915/pmu: Initialise our dynamic sysfs attributes for use with lockdep URL : https://patchwork.freedesktop.org/series/36337/ State : failure == Summary == Test kms_plane_multiple: Subgroup atomic-pipe-a-tiling-none: pass -> SKIP

[Intel-gfx] 282dbf9b "drm/i915: Pass intel_plane and intel_crtc to plane hooks" breaks i945GM in 4.13 and above

Hello, I have an old Lenovo Thinkpad X60 laptop with a Core 2 Duo T7200 CPU and i945GM integrated graphics whose graphics broke when I tried to update the kernel to get the Meltdown fixes. GRUB2 shows a graphical boot menu, and Linux displays the Tux boot logos correctly at first. However,

Re: [Intel-gfx] [PATCH] drm/i915/pmu: Initialise our dynamic sysfs attributes for use with lockdep

Quoting Tvrtko Ursulin (2018-01-11 14:12:38) > You beat me to it, after I noticed the report on IRC and started > digging, just to find sysfs_attr_init, your fix arrived. Thanks! > > It looks like a standard way of silencing lockdep for this case, > although I am not sure what exactly is the

Re: [Intel-gfx] [PATCH 3/6] drm/i915/debugfs: add rcs topology entry

On 11/01/18 11:31, Tvrtko Ursulin wrote: On 18/12/2017 15:35, Lionel Landwerlin wrote: While the end goal is to make this information available to userspace through a new ioctl, there is no reason we can't display it in a human readable fashion through debugfs. slice0 (subslice_mask=0x7):

Re: [Intel-gfx] [PATCH 5/6] drm/i915: add query uAPI

Applied all of your comments here. On 11/01/18 12:19, Tvrtko Ursulin wrote: On 18/12/2017 15:35, Lionel Landwerlin wrote: There are a number of information that are readable from hardware registers and that we would like to make accessible to userspace. One particular example is the topology

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/guc: Redefine guc_log_level modparam values

== Series Details == Series: series starting with [v2,1/2] drm/i915/guc: Redefine guc_log_level modparam values URL : https://patchwork.freedesktop.org/series/36341/ State : success == Summary == Series 36341v1 series starting with [v2,1/2] drm/i915/guc: Redefine guc_log_level modparam

[Intel-gfx] [PATCH 2/2] HAX: drm/i915/uc: Enable GuC/HuC for CI

Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/i915_params.c | 2 +- drivers/gpu/drm/i915/i915_params.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index

[Intel-gfx] [PATCH 1/2] drm/i915/guc: Don't enable GuC when vGPU is active

In GVT-g, if GuC is to be used it is to be loaded by Host and not by VM/vGPU. Currently, GVT-g host is not supported with GuC submission. Also currently vGPU is to be not supported with GuC submission AFAIK. CI BAT highlighted GuC init issue on skl-gvtdvm due to lack of movntdqa needed for logging

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/guc: Don't enable GuC when vGPU is active

== Series Details == Series: series starting with [1/2] drm/i915/guc: Don't enable GuC when vGPU is active URL : https://patchwork.freedesktop.org/series/36343/ State : failure == Summary == Series 36343v1 series starting with [1/2] drm/i915/guc: Don't enable GuC when vGPU is active

[Intel-gfx] [PATCH 8/8] drm/i915/icp: Add the ID for ICL PCH - ICP

From: Anusha Srivatsa Add the PCI ID for the ICL PCH - ICP. v2: rebased. v3: rebased. v4: fix ICP name. v5: fix the ID mask (Fei Li). v6 (from Paulo): bikesheds. Cc: Li, Fei Reviewed-by: Paulo Zanoni Signed-off-by: Anusha

[Intel-gfx] [PATCH 1/8] drm/i915/cnl: Add Port F definition.

From: Rodrigo Vivi Some Cannonlake SKUs will come with a full split between port A and port E. This will be called port F although it is not a 6th port, but only a split. Note this patch alone is not sufficient for port F enabling, it's just the first step. v2: Fix size

[Intel-gfx] [PATCH 2/8] drm/i915/icl: Add initial Icelake definitions.

From: Rodrigo Vivi Icelake is an Intel® Processor containing an Intel® Graphics Controller. This is just an initial Icelake definition. PCI IDs, Icelake support and new features coming in following patches. v2: Add .ddb_size and .has_guc (Michal Wajdeczko). v3: Add the

[Intel-gfx] [PATCH 0/8] ICP initial support

Hi This series adds the initial support for ICP. No conflicts with the other series. Patches 1 and 2 are parts of other series that we've already been discussing on this mailing list, but I put them here so CI can do the right thing. I have just re-reviewed all of Anusha's patches and my

[Intel-gfx] [PATCH 3/8] drm/i915/icp: Introduce Ice Lake PCH

From: Anusha Srivatsa Add the enum additions to ICP PCH. v2 (from Paulo): don't set any platforms to it yet since ICP support is incomplete. v3 (from Rodrigo): Fix ICP name. Reviewed-by: Paulo Zanoni Signed-off-by: Anusha Srivatsa

[Intel-gfx] [PATCH 7/8] drm/i915/icp: add ICP gmbus and gpio support

From: Anusha Srivatsa In ICP, there are three TC ports and 3 DDI ports. v2: - Correct Pin mapping. v3: - Update pin mapping into per platform implementation rather than previous approach of port wise mapping. v4: - Update GMBUS_NUM_PINS (Paulo) v5: - rebase.

[Intel-gfx] [PATCH 6/8] drm/i915/icp: Add backlight Support for ICP

From: Anusha Srivatsa ICP has two backlight controllers - similar to previous platforms like BXT. v2: Remove the usage of ICP_SECOND_PPS_BACKLIGHT register.(Jani) Reuse BXT code since it is very similar.(Ville) v3 (from Paulo): Rebase. Cc: Jani Nikula

[Intel-gfx] [PATCH v2 2/6] drm/i915/debugfs: reuse max slice/subslices already stored in sseu

Now that we have that information in topology fields, let's just reused it. v2: Style tweaks (Tvrtko) Signed-off-by: Lionel Landwerlin Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_debugfs.c | 27 +++

[Intel-gfx] [PATCH v2 4/6] drm/i915: add rcs topology to error state

This might be useful information for developers looking at an error state. v2: Place topology towards the end of the error state (Chris) Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_gpu_error.c | 40 +++ 1 file

[Intel-gfx] [PATCH v2 1/6] drm/i915: store all subslice masks

Up to now, subslice mask was assumed to be uniform across slices. But starting with Cannonlake, slices can be asymmetric (for example slice0 has different number of subslices as slice1+). This change stores all subslices masks for all slices rather than having a single mask that applies to all

Re: [Intel-gfx] [PATCH 10/27] drm/i915/icl: Enhanced execution list support

On 09/01/18 15:28, Paulo Zanoni wrote: From: Thomas Daniel Supports two-element submission using the new enhanced execlist mechanism This could use a few lines to describe enhanced execlist. Something like: "Enhanced Execlists is an upgraded version of execlists

[Intel-gfx] [PATCH v2 3/6] drm/i915/debugfs: add rcs topology entry

While the end goal is to make this information available to userspace through a new ioctl, there is no reason we can't display it in a human readable fashion through debugfs. slice0: 3 subslice(s) (0x7): subslice0: 8 EUs (0xff) subslice1: 8 EUs (0xff) subslice2: 8 EUs

Re: [Intel-gfx] [PATCH v3] drm/i915/icl: Gen11 render context size

On Thu, Jan 11, 2018 at 06:23:20PM +, Oscar Mateo wrote: > From: Tvrtko Ursulin > > Gen11 removes the Resource Streamer, which frees up a big chunk of > the context image. BSpec indicates 12538 DWORDs (13 pages), plus > one page for PPHWSP. > > Please notice that,

[Intel-gfx] [PATCH v2 5/6] drm/i915: add query uAPI

There are a number of information that are readable from hardware registers and that we would like to make accessible to userspace. One particular example is the topology of the execution units (how are execution units grouped in subslices and slices and also which ones have been fused off for die

[Intel-gfx] [PATCH v2 6/6] drm/i915: expose rcs topology through query uAPI

With the introduction of asymmetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam to tell userspace what subslices are available. Here we introduce a more detailed way of querying the Gen's GPU topology that doesn't aggregate numbers. This is essential for monitoring parts

[Intel-gfx] [PATCH v2 0/6] drm/i915: expose RCS topology to userspace

Hi all, Tvrtko found a few bugs in the previous iteration of this series and also made quite a few recommendations on the stored internal state as well uapi, so here is an update. Details in the patches. Thanks a lot, Lionel Landwerlin (6): drm/i915: store all subslice masks

Re: [Intel-gfx] [PATCH 1/7] drm/i915: Disable preemption and sleeping while using the punit sideband

Quoting Ville Syrjälä (2018-01-11 20:10:45) > On Wed, Jan 10, 2018 at 12:55:05PM +, Chris Wilson wrote: > > While we talk to the punit over its sideband, we need to prevent the cpu > > from sleeping in order to prevent a potential machine hang. > > > > Note that by itself, it appears that

Re: [Intel-gfx] [PATCH 20/27] drm/i915/icl: Make use of the SW counter field in the new context descriptor

This could potentially be squashed with patch 15, as it doesn't make much sense to add a TODO there and solve it here. We might also want to update the comment above intel_lr_context_descriptor_update to remove the implication that SW context ID == ctx->hw_id (which is still technically true

Re: [Intel-gfx] [PATCH 14/27] drm/i915/icl: Set graphics mode register for gen11

On 09/01/18 15:28, Paulo Zanoni wrote: From: kgardine This patch clears a single bit. The bit is 0 by default but expected not to be set. Explicitly clearing the bit in this patch is intended to indicate some thinking has occurred, and that we want this bit cleared

Re: [Intel-gfx] [PATCH 6/8] drm/i915/icp: Add backlight Support for ICP

On Thu, Jan 11, 2018 at 09:48:57PM +, James Ausmus wrote: > On Thu, Jan 11, 2018 at 04:00:08PM -0200, Paulo Zanoni wrote: > > From: Anusha Srivatsa > > > > ICP has two backlight controllers - similar to previous platforms like > > BXT. > > > > v2: Remove the usage

Re: [Intel-gfx] [PATCH 1/7] drm/i915: Disable preemption and sleeping while using the punit sideband

Hi, On 11-01-18 22:42, Hans de Goede wrote: Hi, On 11-01-18 22:17, Ville Syrjälä wrote: On Thu, Jan 11, 2018 at 08:53:42PM +, Chris Wilson wrote: Quoting Ville Syrjälä (2018-01-11 20:10:45) On Wed, Jan 10, 2018 at 12:55:05PM +, Chris Wilson wrote: While we talk to the punit over

Re: [Intel-gfx] [PATCH 6/8] drm/i915/icp: Add backlight Support for ICP

On Thu, Jan 11, 2018 at 04:00:08PM -0200, Paulo Zanoni wrote: > From: Anusha Srivatsa > > ICP has two backlight controllers - similar to previous platforms like > BXT. > > v2: Remove the usage of ICP_SECOND_PPS_BACKLIGHT register.(Jani) > Reuse BXT code since it is

Re: [Intel-gfx] [PATCH 1/7] drm/i915: Disable preemption and sleeping while using the punit sideband

Hi, On 11-01-18 22:17, Ville Syrjälä wrote: On Thu, Jan 11, 2018 at 08:53:42PM +, Chris Wilson wrote: Quoting Ville Syrjälä (2018-01-11 20:10:45) On Wed, Jan 10, 2018 at 12:55:05PM +, Chris Wilson wrote: While we talk to the punit over its sideband, we need to prevent the cpu from

Re: [Intel-gfx] [PATCH 20/27] drm/i915/icl: Make use of the SW counter field in the new context descriptor

On 01/11/2018 01:10 PM, Daniele Ceraolo Spurio wrote: This could potentially be squashed with patch 15, as it doesn't make much sense to add a TODO there and solve it here. We might also want to update the comment above intel_lr_context_descriptor_update to remove the implication that SW

Re: [Intel-gfx] [PATCH v3] drm/i915/icl: Gen11 render context size

On 01/11/2018 11:40 AM, Rodrigo Vivi wrote: On Thu, Jan 11, 2018 at 06:23:20PM +, Oscar Mateo wrote: From: Tvrtko Ursulin Gen11 removes the Resource Streamer, which frees up a big chunk of the context image. BSpec indicates 12538 DWORDs (13 pages), plus one

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Return a default RCS context size

On 11/01/18 14:55, Oscar Mateo wrote: Instead of returning whatever size the latest GEN used. This is because context sizes for new GENs can go up or down, but the only safe thing to do for missing cases is to use the largest known one, whatever that is. Suggested-by: Rodrigo Vivi

Re: [Intel-gfx] [PATCH 20/27] drm/i915/icl: Make use of the SW counter field in the new context descriptor

On 11/01/18 14:37, Oscar Mateo wrote: On 01/11/2018 01:10 PM, Daniele Ceraolo Spurio wrote: This could potentially be squashed with patch 15, as it doesn't make much sense to add a TODO there and solve it here. We might also want to update the comment above

Re: [Intel-gfx] [PATCH 2/2 v4] drm/i915/icl: Gen11 render context size

On 11/01/18 14:55, Oscar Mateo wrote: From: Tvrtko Ursulin Gen11 removes the Resource Streamer, which frees up a big chunk of the context image. BSpec indicates 12538 DWORDs (13 pages), plus one page for PPHWSP. This is actually 12544 dwords according to the

[Intel-gfx] [PATCH 1/2] drm/i915: Return a default RCS context size

Instead of returning whatever size the latest GEN used. This is because context sizes for new GENs can go up or down, but the only safe thing to do for missing cases is to use the largest known one, whatever that is. Suggested-by: Rodrigo Vivi Signed-off-by: Oscar Mateo

[Intel-gfx] [PATCH 2/2 v4] drm/i915/icl: Gen11 render context size

From: Tvrtko Ursulin Gen11 removes the Resource Streamer, which frees up a big chunk of the context image. BSpec indicates 12538 DWORDs (13 pages), plus one page for PPHWSP. Please notice that, when looking at the BSpec context image table, the right filter has to be

[Intel-gfx] ✓ Fi.CI.BAT: success for ICP initial support

== Series Details == Series: ICP initial support URL : https://patchwork.freedesktop.org/series/36350/ State : success == Summary == Series 36350v1 ICP initial support https://patchwork.freedesktop.org/api/1.0/series/36350/revisions/1/mbox/ Test debugfs_test: Subgroup

Re: [Intel-gfx] [PATCH libdrm] intel: Add more Coffeelake PCI IDs

On Thu, Jan 11, 2018 at 06:20:53PM +, Anuj Phogat wrote: > Rodrigo, Can you push it upstream for me? I just pushed the libdrm. Do I also need to push the mesa one? Thanks, Rodrigo. > > Thanks > Anuj > > On Wed, Jan 10, 2018 at 4:50 PM, Rodrigo Vivi wrote: > > On

Re: [Intel-gfx] [PATCH libdrm] intel: Add more Coffeelake PCI IDs

On Thu, Jan 11, 2018 at 10:31 AM, Rodrigo Vivi wrote: > On Thu, Jan 11, 2018 at 06:20:53PM +, Anuj Phogat wrote: >> Rodrigo, Can you push it upstream for me? > > I just pushed the libdrm. > > Do I also need to push the mesa one? > No, I've pushed the mesa patch.

Re: [Intel-gfx] [PATCH 1/8] drm/i915/cnl: Add Port F definition.

On Thu, Jan 11, 2018 at 06:00:03PM +, Paulo Zanoni wrote: > From: Rodrigo Vivi > > Some Cannonlake SKUs will come with a full split between > port A and port E. This will be called port F although it > is not a 6th port, but only a split. > > Note this patch alone is

Re: [Intel-gfx] [PATCH i-g-t v13] tests/kms_frontbuffer_tracking: Including DRRS test coverage

On Thu, Jan 11, 2018 at 05:27:52AM +, Ramalingam C wrote: > > > On Wednesday 10 January 2018 11:45 PM, Rodrigo Vivi wrote: > > On Wed, Jan 10, 2018 at 02:47:00PM +, Lohith BS wrote: > > Dynamic Refresh Rate Switch(DRRS) is used to switch the panel's > refresh rate

Re: [Intel-gfx] [PATCH 10/27] drm/i915/icl: Enhanced execution list support

The review from Chris had ended up in my spam folder and I missed it, apologies for duplicating some of the comments. Daniele On 11/01/18 11:55, Daniele Ceraolo Spurio wrote: On 09/01/18 15:28, Paulo Zanoni wrote: From: Thomas Daniel Supports two-element

Re: [Intel-gfx] [PATCH 6/6] drm/i915: expose rcs topology through query uAPI

On 11/01/18 12:45, Tvrtko Ursulin wrote: On 18/12/2017 15:35, Lionel Landwerlin wrote: With the introduction of asymetric slices in CNL, we cannot rely on asymmetric Check ;) the previous SUBSLICE_MASK getparam to tell userspace what subslices are available. Here we introduce a more

[Intel-gfx] ✓ Fi.CI.IGT: success for ICP initial support

== Series Details == Series: ICP initial support URL : https://patchwork.freedesktop.org/series/36350/ State : success == Summary == Test kms_atomic_transition: Subgroup plane-all-modeset-transition-fencing: dmesg-warn -> PASS (shard-hsw) fdo#102614 +1 Test

Re: [Intel-gfx] [PATCH libdrm] intel: Add more Coffeelake PCI IDs

Rodrigo, Can you push it upstream for me? Thanks Anuj On Wed, Jan 10, 2018 at 4:50 PM, Rodrigo Vivi wrote: > On Wed, Jan 10, 2018 at 11:51:02PM +, Anuj Phogat wrote: >> Cc: Rodrigo Vivi >> Cc: Anusha Srivatsa >>

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