Quoting Michel Thierry (2018-01-23 00:41:07)
> On 1/22/2018 4:31 PM, Lucas De Marchi wrote:
> > So for this file what I understand is that it should be:
> >
> > // SPDX-License-Identifier: MIT
> > // Copyright (C) 2014-2018 Intel Corporation
>
> So be it.
Oh no, we don't do C++
Currently, we have a sporadic failure in the multidraw tests where it
sometimes fails to start FBC in a timely fashion (and at other times
works fine). Try to get a little more information as wait it is waiting
for by showing the fbc status at each stage.
Signed-off-by: Chris Wilson
On Mon, 22 Jan 2018, Imre Deak wrote:
> On Fri, Jan 19, 2018 at 05:45:16PM +0200, Imre Deak wrote:
>> On Thu, Oct 12, 2017 at 12:13:38PM -0700, Manasi Navare wrote:
>> > In case of eDP because the panel has a fixed mode, the link rate
>> > and lane count at which it is
Chris Wilson writes:
> Now that we can pass arbitrary commands into the base __wait_for()
> macro, we can reimplement the open-coded wait-for inside
> i915_gem_idle_work_handler() using the macro. This means that instead of
> using ktime, we now use jiffies, and benefit
On 1/22/2018 8:57 PM, Sagar Arun Kamble wrote:
On 1/22/2018 4:17 PM, Chris Wilson wrote:
Quoting Sagar Arun Kamble (2018-01-22 10:38:10)
On 1/22/2018 3:46 PM, Chris Wilson wrote:
Quoting Sagar Arun Kamble (2018-01-22 08:26:01)
+int intel_guc_log_relay_create(struct intel_guc *guc)
+{
+
On Tue, Jan 23, 2018 at 11:48:22AM +0200, Jani Nikula wrote:
> On Mon, 22 Jan 2018, Imre Deak wrote:
> > On Fri, Jan 19, 2018 at 05:45:16PM +0200, Imre Deak wrote:
> >> On Thu, Oct 12, 2017 at 12:13:38PM -0700, Manasi Navare wrote:
> >> > In case of eDP because the panel has
Quoting Patchwork (2018-01-22 21:26:48)
> == Series Details ==
>
> Series: series starting with [v2] drm/i915: Increase render/media power
> gating hysteresis for gen9+ (rev3)
> URL : https://patchwork.freedesktop.org/series/36842/
> State : success
>
> == Summary ==
>
> Warning: bzip
On Mon, 2018-01-22 at 17:33 +0530, Vidya Srinivas wrote:
> From: Mahesh Kumar
>
> Add support of recognizing DRM_FORMAT_NV12 from plane_format
> register value.
>
Reviewed-by: Mika Kahola
> Signed-off-by: Mahesh Kumar
On Tue, Jan 23, 2018 at 05:05:21PM -0200, Paulo Zanoni wrote:
> On ICL we have two sets of registers: one for port A and another for
> port B. The set of port A registers is the same as the CNL registers.
>
> Since the procmon table on ICL is the same we want to reuse the CNL
> function. To do
== Series Details ==
Series: drm/i915/execlists: Inhibit context save/restore for the fake preempt
context (rev2)
URL : https://patchwork.freedesktop.org/series/36984/
State : warning
== Summary ==
Test perf:
Subgroup oa-exponents:
pass -> FAIL (shard-apl)
== Series Details ==
Series: drm/i915: Move LRC register offsets to a header file (rev4)
URL : https://patchwork.freedesktop.org/series/36930/
State : success
== Summary ==
Test kms_flip:
Subgroup flip-vs-expired-vblank-interruptible:
fail -> PASS
== Series Details ==
Series: drm/i915/cnl: Fix aux selection for WA 1178
URL : https://patchwork.freedesktop.org/series/36997/
State : warning
== Summary ==
Test kms_flip:
Subgroup flip-vs-expired-vblank-interruptible:
fail -> PASS (shard-hsw) fdo#102887
== Series Details ==
Series: series starting with [1/2] drm/i915/lrc: Update reg_state macros to
pass checkpatch
URL : https://patchwork.freedesktop.org/series/37005/
State : success
== Summary ==
Series 37005v1 series starting with [1/2] drm/i915/lrc: Update reg_state macros
to pass
i915_guc_log_control is GuC interface and GuC APIs that are not user
facing should be named with "intel_guc" prefix hence we change name to
intel_guc_log_control. Also changed the parameter to intel_guc struct.
Suggested-by: Michal Wajdeczko
Signed-off-by: Sagar Arun
Comment DRM_ERROR_RATELIMIT outputs as log capturer won't be
running.
This reverts commit bd724318b682587ad2f989ab8e0f7b3d4486ced5.
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_guc_log.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git
This patch fixes lockdep issue due to circular locking dependency of
struct_mutex, i_mutex_key, mmap_sem, relay_channels_mutex.
For GuC log relay channel we create debugfs file that requires i_mutex_key
lock and we are doing that under struct_mutex. So we introduced newer
dependency as:
GuC log streaming needs interrupts enabled prior to GuC resume but
runtime pm interrupt setup was happening post GuC resume. Fix it.
While at it, fix the unwinding of steps in the runtime suspend path.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104695
Signed-off-by: Sagar Arun Kamble
== Series Details ==
Series: drm/i915: Use enum plane_id for frontbuffer tracking
URL : https://patchwork.freedesktop.org/series/36991/
State : failure
== Summary ==
Test kms_flip:
Subgroup 2x-wf_vblank-ts-check-interruptible:
pass -> FAIL (shard-hsw)
Disabling GuC interrupts involves access to GuC IRQ control registers
hence ensure device is RPM awake.
v2: Add comment about need to synchronize flush work and log runtime
destroy
v3: Moved patch earlier in the series and removed comment about future
work. (Tvrtko)
v4-v5: Rebase.
v6:
Newer platforms may have subtle offset changes, which will increase the
number of defines, so it is probably better to start moving them to its
own header file. Also move the macros used while setting the reg state.
v2: Rename to intel_lrc_reg.h, to be consistent with i915_reg.h and
Use consistent multi-line comment style as per guideline.
Suggested-by: Michal Wajdeczko
Signed-off-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc: Chris Wilson
---
On Tue, 2018-01-23 at 20:33 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Replace the ad-hoc plane indexing scheme used by the frontbuffer
> tracking with enum plane_id.
>
> The old video overlay not being part of the plane_id namespace
> will just be
On Tue, Jan 23, 2018 at 05:05:23PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar
>
> ICL has 2 slices of DBuf, enable both the slices during display init.
>
> Ideally we should only enable the second slice when needed in order to
> save power, but while we're not
== Series Details ==
Series: drm/i915/cnp: Ignore VBT request for know invalid DDC pin.
URL : https://patchwork.freedesktop.org/series/36988/
State : success
== Summary ==
Test kms_flip:
Subgroup 2x-plain-flip-fb-recreate:
fail -> PASS (shard-hsw)
The macros we use to init the reg_state had the following issues reported
by checkpatch --strict.
Macro argument reuse 'reg_state' - possible side-effects
Macro argument reuse 'pos' - possible side-effects
Macro argument reuse 'ppgtt' - possible side-effects
spaces preferred around that
On Tue, Jan 23, 2018 at 05:05:24PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar
>
> GEN9 onwards bypass path allocation of 4 blocks was needed, as per
> hardware design. ICL doesn't require bypass path allocation of 4 DDB
> blocks, handling the same in this patch.
>
On Tue, Jan 23, 2018 at 05:05:25PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar
>
> GEN9/10 had fixed DBuf block size of 512. Dbuf block size is not a
> fixed number anymore in GEN11, it varies according to bits per pixel
> and tiling. If 8bpp & Yf-tile surface, block
On 1/23/2018 1:04 PM, Chris Wilson wrote:
We only use the preempt context to inject an idle point into execlists.
We never need to reference its logical state, so tell the GPU never to
load it or save it.
v2: BIT(2) for save-inhibit.
N.B. Daniele mentioned this bit mbz for ICL, and has been
== Series Details ==
Series: series starting with [v3,1/6] drm/i915/guc: Grab RPM wakelock while
disabling GuC interrupts
URL : https://patchwork.freedesktop.org/series/37011/
State : success
== Summary ==
Series 37011v1 series starting with [v3,1/6] drm/i915/guc: Grab RPM wakelock
while
On 1/23/2018 9:05 AM, Chris Wilson wrote:
We only use the preempt context to inject an idle point into execlists.
We never need to reference its logical state, so tell the GPU never to
load it or save it.
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by:
On 23/01/18 10:53, Michel Thierry wrote:
On 1/23/2018 9:05 AM, Chris Wilson wrote:
We only use the preempt context to inject an idle point into execlists.
We never need to reference its logical state, so tell the GPU never to
load it or save it.
Suggested-by: Daniele Ceraolo Spurio
We only use the preempt context to inject an idle point into execlists.
We never need to reference its logical state, so tell the GPU never to
load it or save it.
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by: Chris Wilson
Cc:
Let's ignore VBT request if the pin is clearly wrong.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104139
Cc: Kai Heng Feng
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_bios.c | 11 ---
1 file changed, 8
== Series Details ==
Series: drm/i915: Use enum plane_id for frontbuffer tracking
URL : https://patchwork.freedesktop.org/series/36991/
State : success
== Summary ==
Series 36991v1 drm/i915: Use enum plane_id for frontbuffer tracking
Hi
Here's another ICL series. This one includes the very basic steps of display
initialization (although missing quite a few pieces) and some patches related to
planes (dbuf, mbus, bit field changes). Nothing special.
Again, as explained in the other series, the R-B tags in these patches were
This commit adds the basic CDCLK functions, but it's still missing
pieces of the display initialization sequence.
v2:
- Implement the voltage levels.
- Rebase.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h| 10 +-
From: Mahesh Kumar
GEN9 onwards bypass path allocation of 4 blocks was needed, as per
hardware design. ICL doesn't require bypass path allocation of 4 DDB
blocks, handling the same in this patch.
v2 (from Paulo):
- No need for a comment that says what the code already
== Series Details ==
Series: drm/i915/cnp: Ignore VBT request for know invalid DDC pin.
URL : https://patchwork.freedesktop.org/series/36988/
State : success
== Summary ==
Series 36988v1 drm/i915/cnp: Ignore VBT request for know invalid DDC pin.
From: Ville Syrjälä
Replace the ad-hoc plane indexing scheme used by the frontbuffer
tracking with enum plane_id.
The old video overlay not being part of the plane_id namespace
will just be given the high bit.
Signed-off-by: Ville Syrjälä
Newer platforms may have subtle offset changes, which will increase the
number of defines, so it is probably better to start moving them to its
own header file. Also move the macros used while setting the reg state.
v2: Rename to intel_lrc_reg.h, to be consistent with i915_reg.h and
== Series Details ==
Series: drm/i915/pmu: Fix sysfs exported counter config
URL : https://patchwork.freedesktop.org/series/36973/
State : success
== Summary ==
Test drv_suspend:
Subgroup fence-restore-untiled-hibernate:
fail -> SKIP (shard-snb) fdo#103375
On 21/01/18 12:20, Chris Wilson wrote:
Apply a random load to one or all engines in order to apply stress to
RPS as it tries to constantly adjust the GPU frequency to meet the
changing workload.
Signed-off-by: Chris Wilson
---
tests/Makefile.sources | 1 +
== Series Details ==
Series: ICL display initialization and some plane bits
URL : https://patchwork.freedesktop.org/series/36993/
State : failure
== Summary ==
Series 36993v1 ICL display initialization and some plane bits
On 2018-01-22 05:43 PM, Manasi Navare wrote:
> Existing helpers add support upto HBR2. This patch
> adds support for HBR3 rate (8.1 Gbps) introduced as
> part of DP 1.4 specification.
>
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> Cc:
From: Mahesh Kumar
ICL require DDB allocation of plane to be more than "minimum display
buffer needed" for each level in order to enable WM level.
This patch implements and consider the same while allocating DDB
and enabling WM.
Changes Since V1:
- rebase
Changes
From: Mahesh Kumar
GEN9/10 had fixed DBuf block size of 512. Dbuf block size is not a
fixed number anymore in GEN11, it varies according to bits per pixel
and tiling. If 8bpp & Yf-tile surface, block size = 256 else block
size = 512
This patch addresses the same.
v2
On ICL we have two sets of registers: one for port A and another for
port B. The set of port A registers is the same as the CNL registers.
Since the procmon table on ICL is the same we want to reuse the CNL
function. To do that we add a port argument and make CNL always call
the function passing
From: Mahesh Kumar
ICL has 2 slices of DBuf, enable both the slices during display init.
Ideally we should only enable the second slice when needed in order to
save power, but while we're not there yet, adopt the simpler solution
to keep us bug-free.
v2 (from Paulo):
From: Mahesh Kumar
Enable SAGV for ICL platform.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
From: Mahesh Kumar
Gen11/ICL onward ddb entry start/end mask is increased from 10 bits to
11 bits. This patch make changes to use proper mask for ICL+ during
hardware ddb value readout.
Signed-off-by: Mahesh Kumar
---
From: James Ausmus
ICL+ adds changes the PLANE_CTL_FORMAT field from [27:24] to [27:23],
however, all existing PLANE_CTL_FORMAT_* definitions still map to the
correct values. Add an ICL_PLANE_CTL_FORMAT_MASK definition, and use
that for masking for the conversion to
From: Mahesh Kumar
ICL has two slices of DBuf, each slice of size 1024 blocks.
We should not always enable slice-2. It should be enabled only if
display total required BW is > 12GBps OR more than 1 pipes are enabled.
Changes since V1:
- typecast total_data_rate to u64
From: Mahesh Kumar
This patch introduce MBus control registers and their bit-fields
MBUS_ABOX_CTL
MBUS_BBOX_CTL
MBUS_DBOX_CTL
MBUS_UBOX_CTL
Changes Since V1:
- Use function like macros (Paulo)
- fix copy-paste error (Paulo)
Reviewed-by: Paulo Zanoni
From: Mahesh Kumar
We don't have planar pixel format support implemented for ICL yet.
ICL require 2 display planes to be allocated for Planar formats unlike
previous GEN. So ICL/GEN11 doesn't require to write Y-plane ddb data in
NV12_BUF_CFG register and
From: Mahesh Kumar
This patch adds support to start tracking status of DBUF slices.
This is foundation to introduce support for enabling/disabling second
DBUF slice dynamically for ICL.
Signed-off-by: Mahesh Kumar
---
This code is similar enough to the CNL code that I considered just
adding ICL support to the CNL function, but I think it's still
different enough, and having a function specific to ICL allows us to
more easily adapt code in case the spec changes more later.
We're still missing the power wells
From: Mahesh Kumar
This patch initializes MBus during display initialization.
Changes since V2 (from Paulo):
- Don't forget to remove the WARN_ON(1) call.
Changes since V1:
- Rebase to use function like Macros
Reviewed-by: Paulo Zanoni
From: Mahesh Kumar
This patch program default values of MBus credit during pipe enable.
Changes since V2:
- We don't need to do anything when disabling the pipe
Changes Since V1:
- Add WARN_ON (Paulo)
- Remove TODO comment
- Program 0 during pipe disable
- Rebase
It's 10us for gen 11.
Reviewed-by: Mahesh Kumar
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
== Series Details ==
Series: drm/i915/execlists: Inhibit context save/restore for the fake preempt
context
URL : https://patchwork.freedesktop.org/series/36984/
State : success
== Summary ==
Series 36984v1 drm/i915/execlists: Inhibit context save/restore for the fake
preempt context
Good question. We forgot that one. It's 0x162A90.
-Original Message-
From: Vivi, Rodrigo
Sent: Tuesday, 23 January, 2018 8:30 AM
To: Pandiyan, Dhinakaran
Cc: intel-gfx@lists.freedesktop.org; De Marchi, Lucas
; Runyan, Arthur J
== Series Details ==
Series: drm/i915: Move LRC register offsets to a header file (rev4)
URL : https://patchwork.freedesktop.org/series/36930/
State : success
== Summary ==
Series 36930v4 drm/i915: Move LRC register offsets to a header file
== Series Details ==
Series: ICL display initialization and some plane bits
URL : https://patchwork.freedesktop.org/series/36993/
State : failure
== Summary ==
Series 36993v1 ICL display initialization and some plane bits
Quoting Daniele Ceraolo Spurio (2018-01-23 19:37:30)
>
>
> On 23/01/18 10:53, Michel Thierry wrote:
> > On 1/23/2018 9:05 AM, Chris Wilson wrote:
> >> We only use the preempt context to inject an idle point into execlists.
> >> We never need to reference its logical state, so tell the GPU never
We only use the preempt context to inject an idle point into execlists.
We never need to reference its logical state, so tell the GPU never to
load it or save it.
v2: BIT(2) for save-inhibit.
N.B. Daniele mentioned this bit mbz for ICL, and has been moved into the
submission process rather than
Quoting Ville Syrjala (2018-01-23 18:33:43)
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index a92c748ca8ab..18ef0392362e 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -345,6 +345,8 @@
Quoting Antonio Argenziano (2018-01-23 19:03:48)
>
>
> On 21/01/18 12:20, Chris Wilson wrote:
> > Apply a random load to one or all engines in order to apply stress to
> > RPS as it tries to constantly adjust the GPU frequency to meet the
> > changing workload.
> >
> > Signed-off-by: Chris
Quoting Michel Thierry (2018-01-23 19:50:57)
> Newer platforms may have subtle offset changes, which will increase the
> number of defines, so it is probably better to start moving them to its
> own header file. Also move the macros used while setting the reg state.
>
> v2: Rename to
On Tue, Jan 23, 2018 at 02:43:22AM +, Pandiyan, Dhinakaran wrote:
>
>
>
> On Mon, 2018-01-22 at 15:59 -0800, Rodrigo Vivi wrote:
> > On some Cannonlake SKUs we have a dedicated Aux for port F,
> > that is only the full split between port A and port E.
> >
> > There is still no Aux E for
Quoting Ville Syrjala (2018-01-23 18:33:43)
> From: Ville Syrjälä
>
> Replace the ad-hoc plane indexing scheme used by the frontbuffer
> tracking with enum plane_id.
>
> The old video overlay not being part of the plane_id namespace
> will just be given the high
From: Tvrtko Ursulin
We need to generate the event config value using the uAPI class and not
the driver internal one.
Signed-off-by: Tvrtko Ursulin
Fixes: 109ec558370f ("drm/i915/pmu: Only enumerate available counters in sysfs")
Cc: Tvrtko
== Series Details ==
Series: drm/i915/pmu: Fix sysfs exported counter config
URL : https://patchwork.freedesktop.org/series/36973/
State : success
== Summary ==
Series 36973v1 drm/i915/pmu: Fix sysfs exported counter config
Quoting Sagar Arun Kamble (2018-01-23 15:42:18)
> Disabling GuC interrupts involves access to GuC IRQ control registers
> hence ensure device is RPM awake.
>
> v2: Add comment about need to synchronize flush work and log runtime
> destroy
>
> v3: Moved patch earlier in the series and removed
On Tue, Jan 23, 2018 at 02:53:55AM -0200, Pandiyan, Dhinakaran wrote:
>
> On Tue, 2018-01-23 at 02:43 +, Pandiyan, Dhinakaran wrote:
> >
> >
> > On Mon, 2018-01-22 at 15:59 -0800, Rodrigo Vivi wrote:
> > > On some Cannonlake SKUs we have a dedicated Aux for port F,
> > > that is only the
On 1/23/2018 9:36 PM, Michal Wajdeczko wrote:
On Tue, 23 Jan 2018 16:42:20 +0100, Sagar Arun Kamble
wrote:
Comment DRM_ERROR_RATELIMIT outputs as log capturer won't be
running.
This reverts commit bd724318b682587ad2f989ab8e0f7b3d4486ced5.
---
Quoting Michal Wajdeczko (2018-01-23 16:44:33)
> On Tue, 23 Jan 2018 16:42:17 +0100, Sagar Arun Kamble
> > @@ -605,7 +681,11 @@ int i915_guc_log_control(struct drm_i915_private
> > *dev_priv, u64 control_val)
> > }
> > /* GuC logging is currently the only user of
On Tue, 23 Jan 2018 17:06:16 +0100, Lucas De Marchi
wrote:
On Tue, Jan 23, 2018 at 08:48:01AM +, Chris Wilson wrote:
Quoting Michel Thierry (2018-01-23 00:41:07)
> On 1/22/2018 4:31 PM, Lucas De Marchi wrote:
> > So for this file what I understand is that it
On Tue, Jan 23, 2018 at 04:53:55AM +, Pandiyan, Dhinakaran wrote:
>
> On Tue, 2018-01-23 at 02:43 +, Pandiyan, Dhinakaran wrote:
> >
> >
> > On Mon, 2018-01-22 at 15:59 -0800, Rodrigo Vivi wrote:
> > > On some Cannonlake SKUs we have a dedicated Aux for port F,
> > > that is only the
Quoting Tvrtko Ursulin (2018-01-23 13:45:58)
> From: Tvrtko Ursulin
>
> We need to generate the event config value using the uAPI class and not
> the driver internal one.
>
> Signed-off-by: Tvrtko Ursulin
> Fixes: 109ec558370f ("drm/i915/pmu:
== Series Details ==
Series: series starting with [v2,1/4] drm/i915/guc: Fix lockdep due to log
relay channel handling under struct_mutex
URL : https://patchwork.freedesktop.org/series/36980/
State : warning
== Summary ==
Series 36980v1 series starting with [v2,1/4] drm/i915/guc: Fix lockdep
On Tue, 23 Jan 2018 16:42:17 +0100, Sagar Arun Kamble
wrote:
This patch fixes lockdep issue due to circular locking dependency of
struct_mutex, i_mutex_key, mmap_sem, relay_channels_mutex.
For GuC log relay channel we create debugfs file that requires
i_mutex_key
Quoting Sagar Arun Kamble (2018-01-23 15:42:17)
> static void *guc_get_write_buffer(struct intel_guc *guc)
> {
> - if (!guc->log.runtime.relay_chan)
> + if (!guc_log_has_relay(guc))
> return NULL;
>
> /* Just get the base address of a new sub buffer and copy
On Tue, 23 Jan 2018 16:42:20 +0100, Sagar Arun Kamble
wrote:
Comment DRM_ERROR_RATELIMIT outputs as log capturer won't be
running.
This reverts commit bd724318b682587ad2f989ab8e0f7b3d4486ced5.
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
On Tue, Jan 23, 2018 at 05:18:36PM +0100, Michal Wajdeczko wrote:
> On Tue, 23 Jan 2018 17:06:16 +0100, Lucas De Marchi
> wrote:
>
> > On Tue, Jan 23, 2018 at 08:48:01AM +, Chris Wilson wrote:
> > > Quoting Michel Thierry (2018-01-23 00:41:07)
> > > > On 1/22/2018
On Tue, Jan 23, 2018 at 03:03:28AM +, Pandiyan, Dhinakaran wrote:
>
>
>
> On Mon, 2018-01-22 at 15:48 -0800, Rodrigo Vivi wrote:
> > SKUs that lacks on the full port F split will just time out
> > when touching this power well bits, causing a noisy warn.
> >
> > v2: Suggested-by: Imre.
Quoting Lucas De Marchi (2018-01-23 16:06:16)
> On Tue, Jan 23, 2018 at 08:48:01AM +, Chris Wilson wrote:
> > Quoting Michel Thierry (2018-01-23 00:41:07)
> > > On 1/22/2018 4:31 PM, Lucas De Marchi wrote:
> > > > So for this file what I understand is that it should be:
> > > >
> > > >
Hi all,
I've been trying to expose some information to userspace about the fused
parts of the GPU.
This is the 4th attempt at getting this upstream, here are the previous
ones :
https://patchwork.freedesktop.org/patch/185959/
https://patchwork.freedesktop.org/series/33436/
This patch fixes lockdep issue due to circular locking dependency of
struct_mutex, i_mutex_key, mmap_sem, relay_channels_mutex.
For GuC log relay channel we create debugfs file that requires i_mutex_key
lock and we are doing that under struct_mutex. So we introduced newer
dependency as:
Comment DRM_ERROR_RATELIMIT outputs as log capturer won't be
running.
This reverts commit bd724318b682587ad2f989ab8e0f7b3d4486ced5.
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_guc_log.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git
GuC log streaming needs interrupts enabled prior to GuC resume but
runtime pm interrupt setup was happening post GuC resume. Fix it.
While at it, fix the unwinding of steps in the runtime suspend path.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104695
Signed-off-by: Sagar Arun Kamble
Disabling GuC interrupts involves access to GuC IRQ control registers
hence ensure device is RPM awake.
v2: Add comment about need to synchronize flush work and log runtime
destroy
v3: Moved patch earlier in the series and removed comment about future
work. (Tvrtko)
v4-v5: Rebase.
v6:
On Tue, Jan 23, 2018 at 08:48:01AM +, Chris Wilson wrote:
> Quoting Michel Thierry (2018-01-23 00:41:07)
> > On 1/22/2018 4:31 PM, Lucas De Marchi wrote:
> > > So for this file what I understand is that it should be:
> > >
> > > // SPDX-License-Identifier: MIT
> > > // Copyright
On Tue, Jan 23, 2018 at 03:12:52AM +, Pandiyan, Dhinakaran wrote:
>
>
>
> On Fri, 2018-01-19 at 16:05 -0800, Rodrigo Vivi wrote:
> > Now let's finish the Port-F support by adding the
> > proper port F detection, irq and power well support.
> >
> > v2: Rebase
> > v3: Use BIT_ULL
> > v4:
On Thu, Nov 23, 2017 at 09:04:47PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> This series first unifies all users of drm_atomic_helper_check_plane_state()
> to populate the clip rectangle with drm_mode_get_hv_timing(), and once
> everything is unified
== Series Details ==
Series: drm/i915/cnl: Fix aux selection for WA 1178
URL : https://patchwork.freedesktop.org/series/36997/
State : success
== Summary ==
Series 36997v1 drm/i915/cnl: Fix aux selection for WA 1178
https://patchwork.freedesktop.org/api/1.0/series/36997/revisions/1/mbox/
== Series Details ==
Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for
another SKU. (rev7)
URL : https://patchwork.freedesktop.org/series/36828/
State : failure
== Summary ==
Applying: drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
Applying: drm/i915/cnl:
On Tue, Jan 23, 2018 at 11:13:14PM +, Lucas De Marchi wrote:
> On Tue, Jan 23, 2018 at 01:52:45PM -0800, Rodrigo Vivi wrote:
> > Current code always select _CNL_AUX_ANAOVRD1_B
> > register regardless the pw in use.
> >
> > CNL_DISP_PW_AUX_B = 9
> > CNL_DISP_PW_AUX_C = 10
> > CNL_DISP_PW_AUX_D
On Tue, Jan 23, 2018 at 02:32:57PM -0800, Rodrigo Vivi wrote:
> On CNL SKUs that uses port F, max DP rate is 8.1G for all
> ports when we have the elevated voltage.
>
Just a nit here on the commit message. Would it make more sense
to mention the elevated voltage numerical value instead of just
== Series Details ==
Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for
another SKU. (rev8)
URL : https://patchwork.freedesktop.org/series/36828/
State : failure
== Summary ==
Applying: drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
Applying: drm/i915/cnl:
On Tue, Jan 23, 2018 at 01:57:13PM -0800, Rodrigo Vivi wrote:
> We also need to extend this WA to Aux F.
>
> Cc: Dhinakaran Pandiyan
> Cc: Lucas De Marchi
> Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De
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