[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence (rev2)

== Series Details == Series: drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence (rev2) URL : https://patchwork.freedesktop.org/series/37105/ State : success == Summary == Series 37105v2 drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/lrc: Remove superfluous WARN_ON

== Series Details == Series: drm/i915/lrc: Remove superfluous WARN_ON URL : https://patchwork.freedesktop.org/series/37165/ State : success == Summary == Series 37165v1 drm/i915/lrc: Remove superfluous WARN_ON https://patchwork.freedesktop.org/api/1.0/series/37165/revisions/1/mbox/ Test

[Intel-gfx] [PATCH] drm/i915/lrc: Remove superfluous WARN_ON

Remove the WARN_ON(ce->state) inside the static function only called when ce->state == NULL and downgrade the w/a batch setup warning into a developer only mode (GEM_WARN_ON). Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin ---

Re: [Intel-gfx] [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.

On Thu, 25 Jan 2018, Rodrigo Vivi wrote: > The only difference is that this SKUs has the full > Port A/E split named as Port F. > > But since SKUs differences don't matter on the platform > definition group and ids, let's merge all off them together. > > v2: Really include

Re: [Intel-gfx] [PATCH] drm/i915/lrc: Remove superfluous WARN_ON

On 26/01/2018 09:35, Chris Wilson wrote: Remove the WARN_ON(ce->state) inside the static function only called when ce->state == NULL and downgrade the w/a batch setup warning into a developer only mode (GEM_WARN_ON). Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin

Re: [Intel-gfx] [PATCH v6] drm/i915/icl: Enhanced execution list support

Quoting Daniele Ceraolo Spurio (2018-01-26 00:10:09) > > > On 24/01/18 09:46, Chris Wilson wrote: > > Quoting Daniele Ceraolo Spurio (2018-01-24 17:30:07) > >> From: Thomas Daniel > >> > >> Enhanced Execlists is an upgraded version of execlists which supports > >> up to

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence (rev2)

== Series Details == Series: drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence (rev2) URL : https://patchwork.freedesktop.org/series/37105/ State : success == Summary == Test perf: Subgroup polling: pass -> FAIL (shard-hsw)

[Intel-gfx] About client-controlled GPU workload preemption interface.

Hi: 　Recently, we're discussing about adding some interfaces to preempt and cancel the i915 request for GVT-g. After thinking and digging for a while, It looks like the requirement are quite generic. In a multi-buffered rendering window system, when some events happen, it will try to re-draw

Re: [Intel-gfx] [PATCH] drm/i915/breadcrumbs: Drop request reference for the signaler thread

Quoting Chris Wilson (2018-01-24 14:44:01) > Quoting Tvrtko Ursulin (2018-01-24 13:09:37) > > > > On 22/01/2018 15:41, Chris Wilson wrote: > > > If we remember to cancel the signaler on a request when retiring it > > > (after we know that the request has been signaled), we do not need to > > >

Re: [Intel-gfx] [PATCH 07/27] drm/i915/icl: Interrupt handling

On Fri, 19 Jan 2018, Chris Wilson wrote: > Quoting Paulo Zanoni (2018-01-19 18:10:51) >> Em Sex, 2018-01-19 às 17:30 +, Tvrtko Ursulin escreveu: >> > On 10/01/2018 10:16, Joonas Lahtinen wrote: >> > > If these are in a later patch, should be squashed here. >> > >> >

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/lrc: Remove superfluous WARN_ON

== Series Details == Series: drm/i915/lrc: Remove superfluous WARN_ON URL : https://patchwork.freedesktop.org/series/37165/ State : warning == Summary == Test perf: Subgroup oa-exponents: pass -> FAIL (shard-apl) fdo#102254 Test kms_setmode:

Re: [Intel-gfx] [PATCH 1/2] drm/dp: Add HBR3 support in existing DRM DP helpers

On Tue, 23 Jan 2018, Harry Wentland wrote: > On 2018-01-22 05:43 PM, Manasi Navare wrote: >> Existing helpers add support upto HBR2. This patch >> adds support for HBR3 rate (8.1 Gbps) introduced as >> part of DP 1.4 specification. >> >> Cc: Rodrigo Vivi

Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

Quoting Rafael Antognolli (2018-01-26 01:26:34) > Write a PIPE_CONTROL with CS stall followed by 14 dwords of 0 in the > indirect context wa bb. 14 MI_NOOPS following? That isn't what you wrote in the code, but the main thing you haven't explained is why. A normal batch will already have a flush

[Intel-gfx] [PATCH v2] drm/i915/lrc: Remove superfluous WARN_ON

Remove the WARN_ON(ce->state) inside the static function only called when ce->state == NULL and downgrade the w/a batch setup warning into a developer only mode (GEM_WARN_ON). v2: Move the deferred alloc guard into the callee, eliminating the need for the WARN_ON: add/remove: 0/0 grow/shrink: 0/1

Re: [Intel-gfx] [PATCH v2] drm/i915/lrc: Remove superfluous WARN_ON

On 26/01/2018 12:18, Chris Wilson wrote: Remove the WARN_ON(ce->state) inside the static function only called when ce->state == NULL and downgrade the w/a batch setup warning into a developer only mode (GEM_WARN_ON). v2: Move the deferred alloc guard into the callee, eliminating the need for

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/lrc: Remove superfluous WARN_ON (rev2)

== Series Details == Series: drm/i915/lrc: Remove superfluous WARN_ON (rev2) URL : https://patchwork.freedesktop.org/series/37165/ State : success == Summary == Series 37165v2 drm/i915/lrc: Remove superfluous WARN_ON https://patchwork.freedesktop.org/api/1.0/series/37165/revisions/2/mbox/

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/lrc: Remove superfluous WARN_ON (rev2)

Quoting Patchwork (2018-01-26 12:41:14) > == Series Details == > > Series: drm/i915/lrc: Remove superfluous WARN_ON (rev2) > URL : https://patchwork.freedesktop.org/series/37165/ > State : success > > == Summary == > > Series 37165v2 drm/i915/lrc: Remove superfluous WARN_ON >

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/lrc: Remove superfluous WARN_ON (rev2)

== Series Details == Series: drm/i915/lrc: Remove superfluous WARN_ON (rev2) URL : https://patchwork.freedesktop.org/series/37165/ State : failure == Summary == Test perf: Subgroup oa-exponents: pass -> FAIL (shard-apl) fdo#102254 Test gem_eio:

Re: [Intel-gfx] [PATCH] drm/i915/lrc: Remove superfluous WARN_ON

Quoting Tvrtko Ursulin (2018-01-26 11:49:01) > > On 26/01/2018 09:35, Chris Wilson wrote: > > Remove the WARN_ON(ce->state) inside the static function only called > > when ce->state == NULL and downgrade the w/a batch setup warning into a > > developer only mode (GEM_WARN_ON). > > > >

Re: [Intel-gfx] [PATCH 02/10] drm/i915/cnl: Add AUX-F support

On Thu, Jan 25, 2018 at 02:03:22PM -0800, Rodrigo Vivi wrote: > On some Cannonlake SKUs we have a dedicated Aux for port F, > that is only the full split between port A and port E. > > There is still no Aux E for Port E, as in previous platforms, > because port_E still means shared lanes with

Re: [Intel-gfx] [PATCH 09/10] drm/i915/cnl: Enable DDI-F on Cannonlake.

On Thu, Jan 25, 2018 at 02:03:29PM -0800, Rodrigo Vivi wrote: > Now let's finish the Port-F support by adding the > proper port F detection, irq and power well support. lgtm, Reviewed-by: David Weinehall > v2: Rebase > v3: Use BIT_ULL > v4: Cover missed case on

[Intel-gfx] [PATCH 1/2] drm/i915: reduce indent in pch detection

Save some horizontal space. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.c | 189 1 file changed, 96 insertions(+), 93 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c

[Intel-gfx] [PATCH 2/2] drm/i915: only assign dev_priv->pch_id on successful pch detection

Currently pch_id gets assigned also when there's no pch. It doesn't look like it makes a difference, but do the right thing anyway. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915: reduce indent in pch detection

== Series Details == Series: series starting with [1/2] drm/i915: reduce indent in pch detection URL : https://patchwork.freedesktop.org/series/37180/ State : warning == Summary == Series 37180v1 series starting with [1/2] drm/i915: reduce indent in pch detection

Re: [Intel-gfx] [RFC 3/6] drm/i915: Give our log messages our name

On Wed, 24 Jan 2018 17:18:18 +0100, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Define DRM_LOG_NAME to i915 so that the log messages we output change from: [drm] RC6 on to: [i915] RC6 on Signed-off-by: Tvrtko Ursulin

Re: [Intel-gfx] [PATCH 01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.

On Fri, Jan 26, 2018 at 10:12:00AM +, Jani Nikula wrote: > On Thu, 25 Jan 2018, Rodrigo Vivi wrote: > > The only difference is that this SKUs has the full > > Port A/E split named as Port F. > > > > But since SKUs differences don't matter on the platform > > definition

Re: [Intel-gfx] [PATCH libdrm] tests: Add drm_set_cgrp_param

On Fri, Jan 26, 2018 at 05:08:48PM +, Emil Velikov wrote: > On 22 January 2018 at 15:44, Matt Roper wrote: > > drm_set_cgrp_param is a simple tool to set DRM parameters associated with a > > cgroup. It is intended to be called at system initialization time (e.g.,

Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

On Fri, Jan 26, 2018 at 08:23:13AM +, Chris Wilson wrote: > Quoting Rafael Antognolli (2018-01-26 01:26:34) > > Write a PIPE_CONTROL with CS stall followed by 14 dwords of 0 in the > > indirect context wa bb. > > 14 MI_NOOPS following? That isn't what you wrote in the code, but the Agreed,

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev2)

== Series Details == Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev2) URL : https://patchwork.freedesktop.org/series/37134/ State : success == Summary == Series 37134v2 series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for

Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

On Fri, Jan 26, 2018 at 09:55:58AM -0800, Rafael Antognolli wrote: > On Fri, Jan 26, 2018 at 08:23:13AM +, Chris Wilson wrote: > > Quoting Rafael Antognolli (2018-01-26 01:26:34) > > > Write a PIPE_CONTROL with CS stall followed by 14 dwords of 0 in the > > > indirect context wa bb. > > > >

Re: [Intel-gfx] [PATCH libdrm] tests: Add drm_set_cgrp_param

On 26 January 2018 at 17:27, Matt Roper wrote: > On Fri, Jan 26, 2018 at 05:08:48PM +, Emil Velikov wrote: >> On 22 January 2018 at 15:44, Matt Roper wrote: >> > drm_set_cgrp_param is a simple tool to set DRM parameters associated with a

Re: [Intel-gfx] [PATCH] drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence v2

On Fri, Jan 26, 2018 at 08:52:07AM +0100, Hans de Goede wrote: > So far models of the Dell Venue 8 Pro, with a panel with MIPI panel > index = 3, one of which has been kindly provided to me by Jan Brummer, > where not working with the i915 driver, giving a black screen on the > first modeset. > >

Re: [Intel-gfx] [PATCH libdrm] tests: Add drm_set_cgrp_param

On 22 January 2018 at 15:44, Matt Roper wrote: > drm_set_cgrp_param is a simple tool to set DRM parameters associated with a > cgroup. It is intended to be called at system initialization time (e.g., from > a sysv-init script or systemd service) to configure graphics

Re: [Intel-gfx] [PATCH 2/2] drm/i915: only assign dev_priv->pch_id on successful pch detection

On Fri, Jan 26, 2018 at 04:48:05PM +0200, Jani Nikula wrote: > Currently pch_id gets assigned also when there's no pch. It doesn't look > like it makes a difference, but do the right thing anyway. Makes sense. Reviewed-by: David Weinehall > Signed-off-by: Jani

Re: [Intel-gfx] [PATCH v6] drm/i915/icl: Enhanced execution list support

On 26/01/18 00:47, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2018-01-26 00:10:09) On 24/01/18 09:46, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2018-01-24 17:30:07) From: Thomas Daniel Enhanced Execlists is an upgraded version of execlists

Re: [Intel-gfx] [PATCH igt 1/2] lib: Refactor igt_wait() to use library timers

On 25/01/18 13:28, Chris Wilson wrote: Use the timer routines for computing elapsed time from igt_core for smaller code. Signed-off-by: Chris Wilson --- lib/igt_aux.h | 25 +++-- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git

[Intel-gfx] [PATCH] drm/i915/cnl: Add AUX-F support

On some Cannonlake SKUs we have a dedicated Aux for port F, that is only the full split between port A and port E. There is still no Aux E for Port E, as in previous platforms, because port_E still means shared lanes with port A. v2: Rebase. v3: Add couple missed PORT_F cases on intel_dp. v4:

Re: [Intel-gfx] [PATCH 1/2] drm/i915: reduce indent in pch detection

On Fri, Jan 26, 2018 at 04:48:04PM +0200, Jani Nikula wrote: > Save some horizontal space. Yes, please! Reviewed-by: David Weinehall > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_drv.c | 189 >

[Intel-gfx] [PATCH] drm/i915: Remove Firmware URL.

The right place for the firmware is linux-firmware.git. We shouldn't advertise anywhere to users to start downloading firmware blobs manually. Also it seems that 01.org page is outdated and it doesn't contain DMC 1.27 for SKL, for instance. Probably other firmware releases are missing there,

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev2)

== Series Details == Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev2) URL : https://patchwork.freedesktop.org/series/37134/ State : failure == Summary == Warning: bzip CI_DRM_3686/shard-glkb6/results14.json.bz2 wasn't in correct JSON format

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Remove Firmware URL.

== Series Details == Series: drm/i915: Remove Firmware URL. URL : https://patchwork.freedesktop.org/series/37201/ State : failure == Summary == Series 37201v1 drm/i915: Remove Firmware URL. https://patchwork.freedesktop.org/api/1.0/series/37201/revisions/1/mbox/ Test debugfs_test:

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [v4,1/2] drm/i915/icl: new context descriptor support

== Series Details == Series: series starting with [v4,1/2] drm/i915/icl: new context descriptor support URL : https://patchwork.freedesktop.org/series/37204/ State : warning == Summary == Series 37204v1 series starting with [v4,1/2] drm/i915/icl: new context descriptor support

[Intel-gfx] [PATCH v7 2/2] drm/i915/icl: Enhanced execution list support

From: Thomas Daniel Enhanced Execlists is an upgraded version of execlists which supports up to 8 ports. The lrcs to be submitted are written to a submit queue (the ExecLists Submission Queue - ELSQ), which is then loaded on the HW. When writing to the ELSP register, the

[Intel-gfx] [PATCH v4 1/2] drm/i915/icl: new context descriptor support

From: "Ceraolo Spurio, Daniele" Starting from Gen11 the context descriptor format has been updated in the HW. The hw_id field has been considerably reduced in size and engine class and instance fields have been added. There is a slight name clashing issue

[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Add DPCD definitions for DP 1.4 FEC feature (rev3)

== Series Details == Series: drm: Add DPCD definitions for DP 1.4 FEC feature (rev3) URL : https://patchwork.freedesktop.org/series/34259/ State : success == Summary == Series 34259v3 drm: Add DPCD definitions for DP 1.4 FEC feature

Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

Quoting Rafael Antognolli (2018-01-26 17:58:29) > On Fri, Jan 26, 2018 at 09:55:58AM -0800, Rafael Antognolli wrote: > > On Fri, Jan 26, 2018 at 08:23:13AM +, Chris Wilson wrote: > > > Quoting Rafael Antognolli (2018-01-26 01:26:34) > > > > Write a PIPE_CONTROL with CS stall followed by 14

Re: [Intel-gfx] [PATCH 2/2] drm/i915: only assign dev_priv->pch_id on successful pch detection

Quoting David Weinehall (2018-01-26 15:53:53) > On Fri, Jan 26, 2018 at 04:48:05PM +0200, Jani Nikula wrote: > > Currently pch_id gets assigned also when there's no pch. It doesn't look > > like it makes a difference, but do the right thing anyway. > > Makes sense. > > Reviewed-by: David

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern (rev2)

== Series Details == Series: drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern (rev2) URL : https://patchwork.freedesktop.org/series/37148/ State : success == Summary == Series 37148v2 drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

Re: [Intel-gfx] [PATCH 09/10] drm/i915/cnl: Enable DDI-F on Cannonlake.

On Thu, 2018-01-25 at 14:03 -0800, Rodrigo Vivi wrote: > Now let's finish the Port-F support by adding the > proper port F detection, irq and power well support. > > v2: Rebase > v3: Use BIT_ULL > v4: Cover missed case on ddi init. > v5: Update commit message. > v6: Rebase on top of display

Re: [Intel-gfx] [PATCH igt 2/2] igt/kms_frontbuffer_tracking: Bump the wait time for FBC

Quoting Chris Wilson (2018-01-25 21:28:49) > It is taking longer than a couple of seconds for the FBC worker to be > executed after scheduling; and then will take a minimum of a vblank > interval for it activate. So wait longer to reduce the flip flops. > > Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add AUX-F support

On Fri, Jan 26, 2018 at 09:27:41PM +, Pandiyan, Dhinakaran wrote: > > On Fri, 2018-01-26 at 09:15 -0800, Rodrigo Vivi wrote: > > On some Cannonlake SKUs we have a dedicated Aux for port F, > > that is only the full split between port A and port E. > > > > There is still no Aux E for Port E,

[Intel-gfx] ✗ Fi.CI.IGT: failure for include: Move ascii85 functions from i915 to linux/ascii85.h

== Series Details == Series: include: Move ascii85 functions from i915 to linux/ascii85.h URL : https://patchwork.freedesktop.org/series/37211/ State : failure == Summary == Warning: bzip CI_DRM_3686/shard-glkb6/results14.json.bz2 wasn't in correct JSON format Test perf: Subgroup

Re: [Intel-gfx] [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values

On Fri, Jan 26, 2018 at 06:24:32PM -0200, Paulo Zanoni wrote: > Em Ter, 2018-01-23 às 16:32 -0800, James Ausmus escreveu: > > On Tue, Jan 23, 2018 at 05:05:21PM -0200, Paulo Zanoni wrote: > > > On ICL we have two sets of registers: one for port A and another > > > for > > > port B. The set of port

Re: [Intel-gfx] [PATCH v2] drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

Quoting Rafael Antognolli (2018-01-26 23:05:24) > This workaround should prevent a bug that can be hit on a context > restore. To avoid the issue, we must emit a PIPE_CONTROL with CS stall > (0x7a04 0x0010 0x 0x) followed by 12DW's of > NOOP(0x0) in the indirect context

Re: [Intel-gfx] [PATCH] include: Move ascii85 functions from i915 to linux/ascii85.h

Quoting Jordan Crouse (2018-01-26 20:59:22) > The i915 DRM driver very cleverly used ascii85 encoding for their > GPU state file. Move the encode functions to a general header file to > support other drivers that might be interested in the same > functionality. > > Signed-off-by: Jordan Crouse

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add AUX-F support

On Fri, 2018-01-26 at 09:15 -0800, Rodrigo Vivi wrote: > On some Cannonlake SKUs we have a dedicated Aux for port F, > that is only the full split between port A and port E. > > There is still no Aux E for Port E, as in previous platforms, > because port_E still means shared lanes with port A. >

Re: [Intel-gfx] [PATCH v7 2/2] drm/i915/icl: Enhanced execution list support

Quoting Daniele Ceraolo Spurio (2018-01-26 18:31:25) > From: Thomas Daniel > > Enhanced Execlists is an upgraded version of execlists which supports > up to 8 ports. The lrcs to be submitted are written to a submit queue > (the ExecLists Submission Queue - ELSQ), which

[Intel-gfx] [PATCH v2] drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

This workaround should prevent a bug that can be hit on a context restore. To avoid the issue, we must emit a PIPE_CONTROL with CS stall (0x7a04 0x0010 0x 0x) followed by 12DW's of NOOP(0x0) in the indirect context batch buffer, to ensure the engine is idle prior to

[Intel-gfx] ✓ Fi.CI.BAT: success for include: Move ascii85 functions from i915 to linux/ascii85.h

== Series Details == Series: include: Move ascii85 functions from i915 to linux/ascii85.h URL : https://patchwork.freedesktop.org/series/37211/ State : success == Summary == Series 37211v1 include: Move ascii85 functions from i915 to linux/ascii85.h

Re: [Intel-gfx] [PATCH] include: Move ascii85 functions from i915 to linux/ascii85.h

Quoting Jordan Crouse (2018-01-26 20:59:22) > The i915 DRM driver very cleverly used ascii85 encoding for their All gfx drivers must eventually become PostScript. > GPU state file. Move the encode functions to a general header file to > support other drivers that might be interested in the same

Re: [Intel-gfx] [PATCH 09/10] drm/i915/cnl: Enable DDI-F on Cannonlake.

On Fri, Jan 26, 2018 at 09:39:42PM +, Pandiyan, Dhinakaran wrote: > > On Thu, 2018-01-25 at 14:03 -0800, Rodrigo Vivi wrote: > > Now let's finish the Port-F support by adding the > > proper port F detection, irq and power well support. > > > > v2: Rebase > > v3: Use BIT_ULL > > v4: Cover

Re: [Intel-gfx] [PATCH v2] drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

On Fri, Jan 26, 2018 at 11:17:01PM +, Chris Wilson wrote: > Quoting Rafael Antognolli (2018-01-26 23:05:24) > > This workaround should prevent a bug that can be hit on a context > > restore. To avoid the issue, we must emit a PIPE_CONTROL with CS stall > > (0x7a04 0x0010 0x

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern (rev2)

== Series Details == Series: drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern (rev2) URL : https://patchwork.freedesktop.org/series/37148/ State : success == Summary == Warning: bzip CI_DRM_3686/shard-glkb6/results14.json.bz2 wasn't in correct JSON format Test kms_flip: Subgroup

Re: [Intel-gfx] [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values

Em Ter, 2018-01-23 às 16:32 -0800, James Ausmus escreveu: > On Tue, Jan 23, 2018 at 05:05:21PM -0200, Paulo Zanoni wrote: > > On ICL we have two sets of registers: one for port A and another > > for > > port B. The set of port A registers is the same as the CNL > > registers. > > > > Since the

Re: [Intel-gfx] [PATCH 04/17] drm/i915/icl: Enable both DBuf slices during init

Em Ter, 2018-01-23 às 16:49 -0800, James Ausmus escreveu: > On Tue, Jan 23, 2018 at 05:05:23PM -0200, Paulo Zanoni wrote: > > From: Mahesh Kumar > > > > ICL has 2 slices of DBuf, enable both the slices during display > > init. > > > > Ideally we should only enable the

Re: [Intel-gfx] [PATCH igt 1/2] lib: Refactor igt_wait() to use library timers

Quoting Antonio Argenziano (2018-01-26 16:50:15) > > > On 25/01/18 13:28, Chris Wilson wrote: > > Use the timer routines for computing elapsed time from igt_core for > > smaller code. > > > > Signed-off-by: Chris Wilson > > --- > > lib/igt_aux.h | 25

Re: [Intel-gfx] [PATCH v7 2/2] drm/i915/icl: Enhanced execution list support

@@ -870,7 +895,8 @@ static void execlists_submission_tasklet(unsigned long data) GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE); if (status & GEN8_CTX_STATUS_COMPLETE && - buf[2*head + 1] == PREEMPT_ID) { +

Re: [Intel-gfx] [PATCH 01/17] drm/i915/icl: add the main CDCLK functions

On Tue, Jan 23, 2018 at 05:05:20PM -0200, Paulo Zanoni wrote: > This commit adds the basic CDCLK functions, but it's still missing > pieces of the display initialization sequence. > > v2: > - Implement the voltage levels. > - Rebase. > > Signed-off-by: Paulo Zanoni >

Re: [Intel-gfx] [PATCH 07/17] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed

On Tue, Jan 23, 2018 at 05:05:26PM -0200, Paulo Zanoni wrote: > From: Mahesh Kumar > > ICL require DDB allocation of plane to be more than "minimum display > buffer needed" for each level in order to enable WM level. > > This patch implements and consider the same while

Re: [Intel-gfx] [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values

On Tue, Jan 23, 2018 at 05:05:21PM -0200, Paulo Zanoni wrote: > On ICL we have two sets of registers: one for port A and another for > port B. The set of port A registers is the same as the CNL registers. > > Since the procmon table on ICL is the same we want to reuse the CNL > function. To do

[Intel-gfx] [RFC] Move i915 ascii85 functions to linux/ascii85.h

I've been working on a crash dump utility for the drm/msm GPU driver to get the useful GPU information out after a hang. Taking inspiration from the i915 driver I thought it was very smart to use ascii85 format to encode the binary buffers and other bits. This patch moves the two very simple

[Intel-gfx] [PATCH] include: Move ascii85 functions from i915 to linux/ascii85.h

The i915 DRM driver very cleverly used ascii85 encoding for their GPU state file. Move the encode functions to a general header file to support other drivers that might be interested in the same functionality. Signed-off-by: Jordan Crouse ---

Re: [Intel-gfx] [PATCH 09/10] drm/i915/cnl: Enable DDI-F on Cannonlake.

On Fri, Jan 26, 2018 at 02:06:23PM -0800, Rodrigo Vivi wrote: > On Fri, Jan 26, 2018 at 09:39:42PM +, Pandiyan, Dhinakaran wrote: > > > > On Thu, 2018-01-25 at 14:03 -0800, Rodrigo Vivi wrote: > > > Now let's finish the Port-F support by adding the > > > proper port F detection, irq and power

Re: [Intel-gfx] [PATCH 03/17] drm/i915/icl: implement the display init/uninit sequences

On Tue, Jan 23, 2018 at 05:05:22PM -0200, Paulo Zanoni wrote: > This code is similar enough to the CNL code that I considered just > adding ICL support to the CNL function, but I think it's still > different enough, and having a function specific to ICL allows us to > more easily adapt code in

[Intel-gfx] [PATCH] drm/i915/cnl: Enable DDI-F on Cannonlake.

Now let's finish the Port-F support by adding the proper port F detection, irq and power well support. v2: Rebase v3: Use BIT_ULL v4: Cover missed case on ddi init. v5: Update commit message. v6: Rebase on top of display headers rework. v7: Squash power-well handling related to DDI F to this

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev4)

== Series Details == Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev4) URL : https://patchwork.freedesktop.org/series/37134/ State : success == Summary == Warning: bzip CI_DRM_3686/shard-glkb6/results14.json.bz2 wasn't in correct JSON format

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev4)

== Series Details == Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev4) URL : https://patchwork.freedesktop.org/series/37134/ State : success == Summary == Series 37134v4 series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/9] drm/i915/psr: Do not activate PSR on frontbuffer flush from fbdev.

== Series Details == Series: series starting with [1/9] drm/i915/psr: Do not activate PSR on frontbuffer flush from fbdev. URL : https://patchwork.freedesktop.org/series/37222/ State : failure == Summary == Series 37222v1 series starting with [1/9] drm/i915/psr: Do not activate PSR on

[Intel-gfx] [PATCH] drm/i915/cnl: Add AUX-F support

On some Cannonlake SKUs we have a dedicated Aux for port F, that is only the full split between port A and port E. There is still no Aux E for Port E, as in previous platforms, because port_E still means shared lanes with port A. v2: Rebase. v3: Add couple missed PORT_F cases on intel_dp. v4:

[Intel-gfx] [PATCH 3/9] drm/i915/psr: Extract PSR DPCD initialization and move it to intel_psr.c

intel_edp_init_dpcd() is cluttered with PSR specific DPCD checks and intel_dp.c is huge. No functional change intended. Cc: Rodrigo Vivi Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/intel_dp.c | 64

[Intel-gfx] [PATCH 1/9] drm/i915/psr: Do not activate PSR on frontbuffer flush from fbdev.

There is no corresponding invalidate call before the buffer is written to, this results in screen freezing sometime after switching to console mode with PSR enabled. Invalidating the front buffer in the fbdev call backs won't work either as some of them are called in atomic contexts and {drrs,

[Intel-gfx] [PATCH 4/9] drm/i915/psr: Check for the specific AUX_FRAME_SYNC cap bit.

The cap check should be specifically for bit 0 instead of any bit. Cc: Rodrigo Vivi Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/intel_psr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 2/9] drm/i915/frontbuffer: Mark frontbuffer flush and invalidate with might_sleep()

Frontbuffer flush and invalidate call psr, fbc and drrs functions that use mutexes but they can be called in atomic contexts in the fbdev path. The point where the spinlocks are acquired is up in the call stack that is not entirely easy to spot, so annotate with might_sleep(). Cc: Rodrigo Vivi

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev3)

== Series Details == Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev3) URL : https://patchwork.freedesktop.org/series/37134/ State : success == Summary == Series 37134v3 series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for

[Intel-gfx] [PATCH 6/9] drm/i915/dp: Remove redundant sleep after AUX transaction length check.

The core already takes care of the delay before retrying. The delay now changes to (500, 600)us instead of (500 + 1000, 600 + 1500)us. Cc: Rodrigo Vivi Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/intel_dp.c | 8 1

[Intel-gfx] [PATCH 7/9] drm/i915/dp: Move comment about hw timeout to the right place.

No functional change. Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/intel_dp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index

[Intel-gfx] [PATCH 5/9] drm/i915/psr: Inline psr2 caps checks.

Add a macro to check for a bit offset in a DPCD reg, use this macro to eliminate three functions and a local. Cc: Rodrigo Vivi Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/intel_psr.c | 66

[Intel-gfx] [PATCH 8/9] drm/dp: Export AUX_RETRY_INTERVAL

Drivers can use this in their retry loops too. Cc: dri-de...@lists.freedesktop.org Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/drm_dp_helper.c | 12 +--- include/drm/drm_dp_helper.h | 2 ++ 2 files changed, 7 insertions(+), 7 deletions(-)

[Intel-gfx] [PATCH 9/9] drm/i915/dp: Use the same aux retry interval as the core.

Keeps the wait times consistent. Cc: Rodrigo Vivi Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/intel_dp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c