Re: [Intel-gfx] [PATCH] drm/i915/audio: do not set Maud/Naud values manually on KBL

On Tue, Feb 06, 2018 at 11:49:18AM +, Jani Nikula wrote: > Apparently using the manual Maud/Naud mode does not work on KBL. The > details on the failure mode are scarce, except that there's no audio, > and there is obviously no idea on the root cause either. It is also > unknown whether the

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Fix sleep under atomic in RC6 readout (rev2)

== Series Details == Series: drm/i915/pmu: Fix sleep under atomic in RC6 readout (rev2) URL : https://patchwork.freedesktop.org/series/37742/ State : success == Summary == Series 37742v2 drm/i915/pmu: Fix sleep under atomic in RC6 readout

[Intel-gfx] [PATCH] drm/i915/ivb+: Use the correct render forcewake ACK register

FORCEWAKE_ACK is depricated by BSpec at least starting from BDW, referring to the multi-threaded version of it instead. Accessing FORCEWAKE_ACK triggers an unclaimed register access error - at least on GLK - see the Reference: below. As opposed to this debugfs file we normally use the MT version

[Intel-gfx] [PATCH v2] drm/i915/pmu: Fix sleep under atomic in RC6 readout

From: Tvrtko Ursulin We are not allowed to call intel_runtime_pm_get from the PMU counter read callback since the former can sleep, and the latter is running under IRQ context. To workaround this, we record the last known RC6 and while runtime suspended estimate its

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/10] drm/vblank: Data type fixes for 64-bit vblank sequences.

== Series Details == Series: series starting with [01/10] drm/vblank: Data type fixes for 64-bit vblank sequences. URL : https://patchwork.freedesktop.org/series/37598/ State : success == Summary == Series 37598v1 series starting with [01/10] drm/vblank: Data type fixes for 64-bit vblank

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ivb+: Use the correct render forcewake ACK register

== Series Details == Series: drm/i915/ivb+: Use the correct render forcewake ACK register URL : https://patchwork.freedesktop.org/series/37753/ State : success == Summary == Series 37753v1 drm/i915/ivb+: Use the correct render forcewake ACK register

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Remove superfluous worker wakeups when RPS is already boosted

== Series Details == Series: drm/i915: Remove superfluous worker wakeups when RPS is already boosted URL : https://patchwork.freedesktop.org/series/37743/ State : success == Summary == Test perf: Subgroup oa-exponents: pass -> FAIL (shard-apl) fdo#102254

Re: [Intel-gfx] [PATCH] drm/i915/breadcrumbs: Ignore unsubmitted signalers

Quoting Chris Wilson (2018-02-06 09:46:33) > When a request is preempted, it is unsubmitted from the HW queue and > removed from the active list of breadcrumbs. In the process, this > however triggers the signaler and it may see the clear rbtree with the > old, and still valid, seqno. This

Re: [Intel-gfx] [PATCH] drm/i915/pmu: Fix sleep under atomic in RC6 readout

On 06/02/2018 16:10, Imre Deak wrote: On Tue, Feb 06, 2018 at 04:04:10PM +, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-02-06 14:31:07) +static u64 read_rc6_residency(struct drm_i915_private *i915) +{ + u64 val; + + val = intel_rc6_residency_ns(i915, IS_VALLEYVIEW(i915) ?

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/3] drm/i915: Add intel_bios_cleanup() function

== Series Details == Series: series starting with [v4,1/3] drm/i915: Add intel_bios_cleanup() function URL : https://patchwork.freedesktop.org/series/37741/ State : success == Summary == Series 37741v1 series starting with [v4,1/3] drm/i915: Add intel_bios_cleanup() function

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/pmu: Fix sleep under atomic in RC6 readout

== Series Details == Series: drm/i915/pmu: Fix sleep under atomic in RC6 readout URL : https://patchwork.freedesktop.org/series/37742/ State : warning == Summary == Series 37742v1 drm/i915/pmu: Fix sleep under atomic in RC6 readout

[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [v4,1/3] drm/i915: Add intel_bios_cleanup() function

== Series Details == Series: series starting with [v4,1/3] drm/i915: Add intel_bios_cleanup() function URL : https://patchwork.freedesktop.org/series/37741/ State : warning == Summary == Test gem_exec_schedule: Subgroup reorder-wide-vebox: incomplete -> PASS

Re: [Intel-gfx] [PATCH] sna: CustomEDID fix

> Quoting dom.const...@free.fr (2018-02-02 18:37:12) > > Hello, > > > > For my HTPC setup, I'm using the option "CustomEDID". > > With this option, output attaching and destroying events leads to > > crashes. > > > > The following sequence leads to a crash: > > - In xorg.conf: Option

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/breadcrumbs: Ignore unsubmitted signalers

== Series Details == Series: series starting with [1/3] drm/i915/breadcrumbs: Ignore unsubmitted signalers URL : https://patchwork.freedesktop.org/series/37725/ State : failure == Summary == Series 37725v1 series starting with [1/3] drm/i915/breadcrumbs: Ignore unsubmitted signalers

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: pch detection refactoring

== Series Details == Series: drm/i915: pch detection refactoring URL : https://patchwork.freedesktop.org/series/37673/ State : warning == Summary == Series 37673v1 drm/i915: pch detection refactoring https://patchwork.freedesktop.org/api/1.0/series/37673/revisions/1/mbox/ Test debugfs_test:

[Intel-gfx] [PATCH 2/2] yuv422 - rough patch for 10/12/16 bit packed support

Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/drm_fourcc.c | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_display.c | 24 +--- drivers/gpu/drm/i915/intel_sprite.c | 12 +---

[Intel-gfx] [PATCH 1/2] YUV444 10/12/16 bit declarations and additions

Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/drm_fourcc.c | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_display.c | 42 +++- drivers/gpu/drm/i915/intel_sprite.c | 7 +-

[Intel-gfx] [PATCH] drm/i915: Display WA #0827 for NV12 to RGB switch

From: Chandra Konduru Display WA #0827: Switching the plane format from NV12 to RGB and leaving system idle results in display underrun and corruption. WA: Set the bit 15 & bit 19 to 1b in the CLKGATE_DIS_PSL register for the pipe in which NV12 plane is enabled.

[Intel-gfx] [PATCH] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

If the fb format is YUV, enable the plane CSC mode bits for the conversion. Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_display.c | 2 ++ 2 files changed, 8 insertions(+) diff --git

[Intel-gfx] [PATCH] drm/i915: NV12 changes for Gen10

Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_atomic.c | 5 ++--- drivers/gpu/drm/i915/intel_display.c | 7 ++- drivers/gpu/drm/i915/intel_sprite.c | 4 3 files changed, 12 insertions(+), 4 deletions(-) diff --git

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/pmu: Fix PMU enable vs execlists tasklet race (rev4)

== Series Details == Series: drm/i915/pmu: Fix PMU enable vs execlists tasklet race (rev4) URL : https://patchwork.freedesktop.org/series/37575/ State : success == Summary == Test kms_frontbuffer_tracking: Subgroup fbc-2p-scndscrn-cur-indfb-move: skip -> PASS

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Fix PMU enable vs execlists tasklet race (rev4)

On 06/02/2018 09:51, Patchwork wrote: == Series Details == Series: drm/i915/pmu: Fix PMU enable vs execlists tasklet race (rev4) URL : https://patchwork.freedesktop.org/series/37575/ State : success == Summary == Series 37575v4 drm/i915/pmu: Fix PMU enable vs execlists tasklet race

[Intel-gfx] [PATCH] drm/i915/breadcrumbs: Ignore unsubmitted signalers

When a request is preempted, it is unsubmitted from the HW queue and removed from the active list of breadcrumbs. In the process, this however triggers the signaler and it may see the clear rbtree with the old, and still valid, seqno. This confuses the signaler into action and signaling the fence.

[Intel-gfx] [PATCH 1/3] drm/i915/breadcrumbs: Ignore unsubmitted signalers

When a request is preempted, it is unsubmitted from the HW queue and removed from the active list of breadcrumbs. In the process, this however triggers the signaler and it may see the clear rbtree with the old, and still valid, seqno. This confuses the signaler into action and signaling the fence.

Re: [Intel-gfx] [PATCH v8 2/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset

Quoting Jackie Li (2018-02-06 00:02:38) > diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c > b/drivers/gpu/drm/i915/intel_guc_ads.c > index ac62753..7215594 100644 > --- a/drivers/gpu/drm/i915/intel_guc_ads.c > +++ b/drivers/gpu/drm/i915/intel_guc_ads.c > @@ -113,17 +113,6 @@ int

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/breadcrumbs: Ignore unsubmitted signalers

== Series Details == Series: drm/i915/breadcrumbs: Ignore unsubmitted signalers URL : https://patchwork.freedesktop.org/series/37724/ State : success == Summary == Series 37724v1 drm/i915/breadcrumbs: Ignore unsubmitted signalers

Re: [Intel-gfx] [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers

Quoting Jackie Li (2018-02-06 00:02:41) > +static inline bool __reg_locked(struct drm_i915_private *dev_priv, > + i915_reg_t reg) > +{ > + /* Explicitly cast the return value to bool. */ You already did by using bool. > + return !!(I915_READ(reg) &

[Intel-gfx] [PATCH 2/3] drm/i915/breadcrumbs: Reduce signaler rbtree to a sorted list

The goal here is to try and reduce the latency of signaling additional requests following the wakeup from interrupt by reducing the list of to-be-signaled requests from an rbtree to a sorted linked list. The original choice of using an rbtree was to facilitate random insertions of request into the

[Intel-gfx] [PATCH 3/3] drm/i915/breadcrumbs: Assert all missed breadcrumbs were signaled

When parking the engines and their breadcrumbs, if we have waiters left then they missed their wakeup. Verify that each waiter's seqno did complete. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/intel_breadcrumbs.c |

Re: [Intel-gfx] [PATCH] drm/i915/breadcrumbs: Ignore unsubmitted signalers

Quoting Chris Wilson (2018-02-06 09:46:33) > When a request is preempted, it is unsubmitted from the HW queue and > removed from the active list of breadcrumbs. In the process, this > however triggers the signaler and it may see the clear rbtree with the > old, and still valid, seqno. This

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: remove port A/E lane sharing limitation. (rev3)

== Series Details == Series: drm/i915/icl: remove port A/E lane sharing limitation. (rev3) URL : https://patchwork.freedesktop.org/series/37325/ State : success == Summary == Test gem_eio: Subgroup in-flight-contexts: pass -> DMESG-WARN (shard-snb) fdo#104058

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Fix PMU enable vs execlists tasklet race (rev4)

== Series Details == Series: drm/i915/pmu: Fix PMU enable vs execlists tasklet race (rev4) URL : https://patchwork.freedesktop.org/series/37575/ State : success == Summary == Series 37575v4 drm/i915/pmu: Fix PMU enable vs execlists tasklet race

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Display WA #0827 for NV12 to RGB switch (rev4)

== Series Details == Series: drm/i915: Display WA #0827 for NV12 to RGB switch (rev4) URL : https://patchwork.freedesktop.org/series/37729/ State : failure == Summary == Applying: YUV444 10/12/16 bit declarations and additions error: Failed to merge in the changes. Using index info to

[Intel-gfx] [PATCH] drm/i915/audio: do not set Maud/Naud values manually on KBL

Apparently using the manual Maud/Naud mode does not work on KBL. The details on the failure mode are scarce, except that there's no audio, and there is obviously no idea on the root cause either. It is also unknown whether the failure can be reproduced on newer platforms in some scenarios. The

Re: [Intel-gfx] [PATCH] drm/i915: Display WA #0827 for NV12 to RGB switch

On Tue, Feb 06, 2018 at 04:36:42PM +0530, Vidya Srinivas wrote: > From: Chandra Konduru > > Display WA #0827: > Switching the plane format from NV12 to RGB and leaving system idle results > in display underrun and corruption. WA: Set the bit 15 & bit 19 to 1b > in the

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/audio: do not set Maud/Naud values manually on KBL

== Series Details == Series: drm/i915/audio: do not set Maud/Naud values manually on KBL URL : https://patchwork.freedesktop.org/series/37730/ State : success == Summary == Series 37730v1 drm/i915/audio: do not set Maud/Naud values manually on KBL

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/breadcrumbs: Ignore unsubmitted signalers

== Series Details == Series: drm/i915/breadcrumbs: Ignore unsubmitted signalers URL : https://patchwork.freedesktop.org/series/37724/ State : warning == Summary == Test gem_eio: Subgroup in-flight: dmesg-warn -> PASS (shard-snb) fdo#104058 Test kms_flip:

Re: [Intel-gfx] [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers

On Tue, 06 Feb 2018 07:39:27 +0100, Sagar Arun Kamble wrote: On 2/6/2018 5:32 AM, Jackie Li wrote: GuC WOPCM registers are write-once registers. Current driver code accesses these registers without checking the accessibility to these registers, this will lead

[Intel-gfx] [PATCH igt] igt/gem_eio: Use slow spinners to inject hangs

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104676 Signed-off-by: Chris Wilson --- lib/igt_gt.c| 1 + tests/gem_eio.c | 77 +++-- 2 files changed, 43 insertions(+), 35 deletions(-) diff --git

Re: [Intel-gfx] [PULL] gvt-next-fixes for 4.16

Hi Zhi, Daniel asked few weeks ago about the scripts that you run there, but I didn't see any follow-up. I don't understand why yet, but apparently gvt pull request is not going to patchwork so dim is not able to add the "Link:" hence end up without mandatory patchwork links. Last round I

[Intel-gfx] ✗ Fi.CI.BAT: warning for ICL display initialization, selected patches (rev3)

== Series Details == Series: ICL display initialization, selected patches (rev3) URL : https://patchwork.freedesktop.org/series/37668/ State : warning == Summary == Series 37668v3 ICL display initialization, selected patches

Re: [Intel-gfx] [PATCH v8 3/6] drm/i915/guc: Implement dynamic GuC WOPCM offset and size

On Tue, 06 Feb 2018 07:20:41 +0100, Sagar Arun Kamble wrote: change looks good to me. minor updates suggested with r-b. On 2/6/2018 5:32 AM, Jackie Li wrote: Hardware may have specific restrictions on GuC WOPCM offset and size. On Gen9, the value of the GuC WOPCM

Re: [Intel-gfx] [PATCH v8 4/6] drm/i915/guc: Add dynamic GuC WOPCM offset and size support for CNL

On Tue, 06 Feb 2018 07:31:06 +0100, Sagar Arun Kamble wrote: On 2/6/2018 5:32 AM, Jackie Li wrote: CNL has its own specific reserved GuC WOPCM size and hardware restrictions on GuC WOPCM size. On CNL A0 and Gen9, there's a hardware restriction that requires

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/ivb+: Use the correct render forcewake ACK register

== Series Details == Series: drm/i915/ivb+: Use the correct render forcewake ACK register URL : https://patchwork.freedesktop.org/series/37753/ State : success == Summary == Test gem_exec_schedule: Subgroup reorder-wide-vebox: incomplete -> PASS (shard-apl)

Re: [Intel-gfx] [PATCH] drm/i915: Reject undefined colorkey flags

Quoting Ville Syrjala (2018-02-06 20:43:33) > From: Ville Syrjälä > > Check that userspace isn't passing in garbage in the colorkey > ioctl flags. > > Signed-off-by: Ville Syrjälä I think we can retrospectively apply this filter.

[Intel-gfx] [PATCH 2/6] drm/i915/icl: add the main CDCLK functions

This commit adds the basic CDCLK functions, but it's still missing pieces of the display initialization sequence. v2: - Implement the voltage levels. - Rebase. v3: - Adjust to the new "bypass" clock (Imre). - Call intel_dump_cdclk_state() too. - Rename a variable to avoid confusion. -

Re: [Intel-gfx] [PATCH v8 1/6] drm/i915/guc: Move GuC WOPCM related code into separate files

On Tue, 06 Feb 2018 06:15:54 +0100, Sagar Arun Kamble wrote: On 2/6/2018 5:32 AM, Jackie Li wrote: intel_guc_reg.h should only include definition for GuC registers and related register bits. Non-register related GuC WOPCM macro definitions should not be defined in

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Reject undefined colorkey flags

== Series Details == Series: drm/i915: Reject undefined colorkey flags URL : https://patchwork.freedesktop.org/series/37764/ State : success == Summary == Test perf: Subgroup enable-disable: fail -> PASS (shard-apl) fdo#103715 Subgroup buffer-fill:

Re: [Intel-gfx] [PATCH v2] drm/i915/pmu: Fix sleep under atomic in RC6 readout

Hi Rafael, On Tue, Feb 06, 2018 at 09:11:02PM +, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2018-02-06 18:33:11) > > From: Tvrtko Ursulin > > > > We are not allowed to call intel_runtime_pm_get from the PMU counter read > > callback since the former can sleep,

[Intel-gfx] [PATCH] drm/i915: Reject undefined colorkey flags

From: Ville Syrjälä Check that userspace isn't passing in garbage in the colorkey ioctl flags. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_sprite.c | 3 +++ 1 file changed, 3 insertions(+) diff --git

Re: [Intel-gfx] [PATCH] drm/i915/ivb+: Use the correct render forcewake ACK register

Quoting Imre Deak (2018-02-06 18:20:07) > FORCEWAKE_ACK is depricated by BSpec at least starting from BDW, > referring to the multi-threaded version of it instead. Accessing > FORCEWAKE_ACK triggers an unclaimed register access error - at > least on GLK - see the Reference: below. > > As opposed

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Reject undefined colorkey flags

== Series Details == Series: drm/i915: Reject undefined colorkey flags URL : https://patchwork.freedesktop.org/series/37764/ State : success == Summary == Series 37764v1 drm/i915: Reject undefined colorkey flags https://patchwork.freedesktop.org/api/1.0/series/37764/revisions/1/mbox/

Re: [Intel-gfx] [PATCH v2] drm/i915/pmu: Fix sleep under atomic in RC6 readout

Quoting Tvrtko Ursulin (2018-02-06 18:33:11) > From: Tvrtko Ursulin > > We are not allowed to call intel_runtime_pm_get from the PMU counter read > callback since the former can sleep, and the latter is running under IRQ > context. > > To workaround this, we record the

Re: [Intel-gfx] [PATCH 2/6] drm/i915/icl: add the main CDCLK functions

Em Seg, 2018-02-05 às 15:13 -0800, Ausmus, James escreveu: > On Mon, Feb 05, 2018 at 01:40:42PM -0200, Paulo Zanoni wrote: > > This commit adds the basic CDCLK functions, but it's still missing > > pieces of the display initialization sequence. > > > > v2: > > - Implement the voltage levels. > >

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove superfluous worker wakeups when RPS is already boosted

== Series Details == Series: drm/i915: Remove superfluous worker wakeups when RPS is already boosted URL : https://patchwork.freedesktop.org/series/37743/ State : success == Summary == Series 37743v1 drm/i915: Remove superfluous worker wakeups when RPS is already boosted

Re: [Intel-gfx] [PATCH] drm/i915/pmu: Fix sleep under atomic in RC6 readout

On Tue, Feb 06, 2018 at 04:04:10PM +, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2018-02-06 14:31:07) > > +static u64 read_rc6_residency(struct drm_i915_private *i915) > > +{ > > + u64 val; > > + > > + val = intel_rc6_residency_ns(i915, IS_VALLEYVIEW(i915) ? > > +

Re: [Intel-gfx] [PATCH igt v2] tests: Add a random load generator

On 03/02/18 02:33, Chris Wilson wrote: Apply a random load to one or all engines in order to apply stress to RPS as it tries to constantly adjust the GPU frequency to meet the changing workload. This can be used to reproduce the byt (j1900) system hang. v2: igt_until_timeout Signed-off-by:

Re: [Intel-gfx] [PATCH] sna: CustomEDID fix

Quoting dom.const...@free.fr (2018-02-02 18:37:12) > Hello, > > For my HTPC setup, I'm using the option "CustomEDID". > With this option, output attaching and destroying events leads to crashes. > > The following sequence leads to a crash: > - In xorg.conf: Option "CustomEDID"

[Intel-gfx] Thinkpad X1 Carbon 3rd - Reducing the compressed framebuffer size

Hi! I'm periodically getting following message in dmesg on Lenovo Thinkpad X1 Carbon 3rd generation: [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS. In BIOS I already set GPU

Re: [Intel-gfx] [PATCH] drm/i915/pmu: Fix sleep under atomic in RC6 readout

Quoting Tvrtko Ursulin (2018-02-06 14:31:07) > +static u64 read_rc6_residency(struct drm_i915_private *i915) > +{ > + u64 val; > + > + val = intel_rc6_residency_ns(i915, IS_VALLEYVIEW(i915) ? > + VLV_GT_RENDER_RC6 : > GEN6_GT_GFX_RC6); > +

Re: [Intel-gfx] [PULL] gvt-next-fixes for 4.16

On 2018.02.06 11:45:04 -0800, Rodrigo Vivi wrote: > > Hi Zhi, > > Daniel asked few weeks ago about the scripts that you run there, > but I didn't see any follow-up. > > I don't understand why yet, but apparently gvt pull request > is not going to patchwork so dim is not able to add the "Link:"

Re: [Intel-gfx] [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers

On 02/05/2018 10:39 PM, Sagar Arun Kamble wrote: +/** + * intel_guc_wopcm_init_hw() - Setup GuC WOPCM registers. + * @guc: intel guc. + * + * Setup the GuC WOPCM size and offset registers with the stored values. It will + * also check the registers locking status to determine whether these

Re: [Intel-gfx] [PATCH v8 1/6] drm/i915/guc: Move GuC WOPCM related code into separate files

On 02/06/2018 01:11 PM, Michal Wajdeczko wrote: On Tue, 06 Feb 2018 06:15:54 +0100, Sagar Arun Kamble wrote: On 2/6/2018 5:32 AM, Jackie Li wrote: intel_guc_reg.h should only include definition for GuC registers and related register bits. Non-register related

Re: [Intel-gfx] [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers

On 02/06/2018 02:56 PM, Michal Wajdeczko wrote: +    /* Explicitly cast the return value to bool. */ +    return !!(I915_READ(reg) & GUC_WOPCM_REG_LOCKED); you should avoid reusing bits defined for one register in others it's a common bit. use BIT(0) instead? +    offset &=

Re: [Intel-gfx] [PATCH 06/10] drm/tegra: Handle 64-bit return from drm_crtc_vblank_count()

On Fri, 2018-02-02 at 21:12 -0800, Dhinakaran Pandiyan wrote: > 570e86963a51 ("drm: Widen vblank count to 64-bits [v3]") changed the > return type for drm_crtc_vblank_count() to u64. This could cause > potential problems if the return value is used in arithmetic operations > with a 32-bit

Re: [Intel-gfx] [PATCH 1/9] drm/i915/psr: Do not activate PSR on frontbuffer flush from fbdev.

On Wed, 2018-01-31 at 22:56 -0800, Rodrigo Vivi wrote: > On Sat, Jan 27, 2018 at 02:49:15AM +, Dhinakaran Pandiyan wrote: > > There is no corresponding invalidate call before the buffer is written > > to, this results in screen freezing sometime after switching to console > > mode with PSR

Re: [Intel-gfx] [PATCH] drm/i915: Display WA #0827 for NV12 to RGB switch

Hi Maarten Sorry, my bad. This was a wrong push from my end. I have changed the tag to Not applicable. Apologies. Have sent out the NV12 series separately. Regards Vidya > -Original Message- > From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com] > Sent: Tuesday, February

Re: [Intel-gfx] [PULL] gvt-next-fixes for 4.16

Zhenyu Wang writes: > On 2018.02.06 11:45:04 -0800, Rodrigo Vivi wrote: >> >> Hi Zhi, >> >> Daniel asked few weeks ago about the scripts that you run there, >> but I didn't see any follow-up. >> >> I don't understand why yet, but apparently gvt pull request >> is not

Re: [Intel-gfx] [PATCH v8 3/6] drm/i915/guc: Implement dynamic GuC WOPCM offset and size

On 02/06/2018 02:25 PM, Michal Wajdeczko wrote: default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);   -    /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not +    /* + * GuC requires the ring to be placed above GuC WOPCM top. If GuC is not    *

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [01/10] drm/vblank: Data type fixes for 64-bit vblank sequences.

== Series Details == Series: series starting with [01/10] drm/vblank: Data type fixes for 64-bit vblank sequences. URL : https://patchwork.freedesktop.org/series/37598/ State : warning == Summary == Series 37598v1 series starting with [01/10] drm/vblank: Data type fixes for 64-bit vblank

[Intel-gfx] [PULL] gvt-next-fixes for 4.16

Hi guys: Here are the latest gvt-next-fixes pull. It contains vGPU reset enhancement, which refines vGPU reset flow and the support of virtual aperture read/write when x-no-mmap=on is set in KVM, which is required by a test case from Redhat and also another fix for virtual OpRegion.

Re: [Intel-gfx] [PATCH v3] drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

Quoting Rafael Antognolli (2018-02-05 23:33:30) > This workaround should prevent a bug that can be hit on a context > restore. To avoid the issue, we must emit a PIPE_CONTROL with CS stall > (0x7a04 0x0010 0x 0x) followed by 12DW's of > NOOP(0x0) in the indirect context

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/pmu: Fix PMU enable vs execlists tasklet race (rev2)

== Series Details == Series: drm/i915/pmu: Fix PMU enable vs execlists tasklet race (rev2) URL : https://patchwork.freedesktop.org/series/37575/ State : success == Summary == Test kms_cursor_legacy: Subgroup flip-vs-cursor-atomic: fail -> PASS (shard-hsw)

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: remove port A/E lane sharing limitation. (rev3)

== Series Details == Series: drm/i915/icl: remove port A/E lane sharing limitation. (rev3) URL : https://patchwork.freedesktop.org/series/37325/ State : success == Summary == Series 37325v3 drm/i915/icl: remove port A/E lane sharing limitation.

Re: [Intel-gfx] [PATCH v4 1/7] drm/i915: Add CRTC output format YCBCR 4:2:0

Regards Shashank On 2/2/2018 7:30 PM, Ville Syrjälä wrote: On Fri, Feb 02, 2018 at 11:38:07AM +0530, Sharma, Shashank wrote: Thanks for the comments, mine inline. Regards Shashank On 2/2/2018 12:39 AM, Ville Syrjälä wrote: On Tue, Jan 30, 2018 at 03:05:57PM +0530, Shashank Sharma wrote:

Re: [Intel-gfx] [PATCH v4 7/7] drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON

Regards Shashank On 2/2/2018 7:22 PM, Ville Syrjälä wrote: On Fri, Feb 02, 2018 at 11:44:01AM +0530, Sharma, Shashank wrote: Regards Shashank On 2/2/2018 12:39 AM, Ville Syrjälä wrote: On Tue, Jan 30, 2018 at 03:06:03PM +0530, Shashank Sharma wrote: From: "Sharma, Shashank"

[Intel-gfx] [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function

From: Mahesh Kumar This patch splits skl_compute_wm/ddb functions into two parts. One adds all affected pipes after the commit to atomic_state structure and second part does compute the DDB. Signed-off-by: Mahesh Kumar ---

[Intel-gfx] [PATCH] drm/i915/skl+: refactor WM calculation for NV12

From: Mahesh Kumar Current code calculates DDB for planar formats in such a way that we store DDB of plane-0 in plane 1 & vice-versa. In order to make this clean this patch refactors WM/DDB calculation for NV12 planar formats. v2: Addressed review comments by Maarten

[Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

From: Mahesh Kumar NV12 requires WM calculation for UV plane as well. UV plane WM should also fulfill all the WM related restrictions. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_drv.h |

[Intel-gfx] [PATCH 00/16] Adding NV12 support

This patch series is adding NV12 support for Broxton display after rebasing on latest drm-tip. Initial series of the patches can be found here: https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html Previous revision history: The first version of patches were reviewed when floated

[Intel-gfx] [PATCH 12/16] drm/i915: Upscale scaler max scale for NV12

From: Chandra Konduru This patch updates scaler max limit support for NV12 v2: Rebased (me) v3: Rebased (me) v4: Missed the Tested-by/Reviewed-by in the previous series Adding the same to commit message in this version. v5: Addressed review comments from Ville and

[Intel-gfx] [PATCH 10/16] drm/i915: Set scaler mode for NV12

From: Chandra Konduru This patch sets appropriate scaler mode for NV12 format. In this mode, skylake scaler does either chroma-upsampling or chroma-upsampling and resolution scaling v2: Review comments from Ville addressed NV12 case to be checked first for setting the

[Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

From: Chandra Konduru This patch adds NV12 to list of supported formats for primary plane v2: Rebased (Chandra Konduru) v3: Rebased (me) v4: Review comments by Ville addressed Removed the skl_primary_formats_with_nv12 and added NV12 case in existing

[Intel-gfx] [PATCH 15/16] drm/i915: Add NV12 support to intel_framebuffer_init

From: Chandra Konduru This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (Chandra Konduru) v3: rebased (me) v4: Review comments by Ville addressed Added platform check for NV12 in

[Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

If the fb format is YUV, enable the plane CSC mode bits for the conversion. Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_display.c | 2 ++ 2 files changed, 8 insertions(+) diff --git

[Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

From: Mahesh Kumar NV12 formats have two registers for DDB. Verify both the registers for NV12 during verify_wm_state. v2: Addressed review comments by Maarten. Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas

[Intel-gfx] [PATCH 06/16] drm/i915/skl+: pass skl_wm_level struct to wm compute func

From: Mahesh Kumar This will reduce number of arguments required to be passed in skl_compute_plane_wm function. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_pm.c | 18 +++--- 1 file changed, 7 insertions(+), 11

[Intel-gfx] [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc

From: Mahesh Kumar Add support of recognizing DRM_FORMAT_NV12 from plane_format register value. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) diff --git

[Intel-gfx] [PATCH 01/16] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

From: Mahesh Kumar skl_wm_values struct contains values of pipe/plane DDB only. so rename it for better readability of code. Similarly skl_copy_wm_for_pipe copies DDB values. s/skl_wm_values/skl_ddb_values s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe Changes since V1:

[Intel-gfx] [PATCH 07/16] drm/i915/skl+: make sure higher latency level has higher wm value

From: Mahesh Kumar DDB allocation optimization algorithm requires/assumes ddb allocation for any memory C-state level DDB value to be as high as level below. Render decompression requires level WM to be as high as wm level-0. This patch fulfils both the requirements.

[Intel-gfx] [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane

From: Chandra Konduru This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed - Removed skl_plane_formats_with_nv12 and added NV12 case in existing skl_plane_formats - Added the 10bpc RGB formats

[Intel-gfx] [PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7

From: Mahesh Kumar Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A) Hardware sometimes fails to wake memory from pkg C states fetching the last few lines of planar YUV 420 (NV12) planes. This causes intermittent underflow and corruption. WA: Disable package C

[Intel-gfx] [PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12

From: Chandra Konduru This patch adds NV12 to format_is_yuv() function for sprite planes. v2: -Use intel_ prefix for format_is_yuv (Ville) v3: Rebased (me) v4: Rebased and addressed review comments from Clinton A Taylor. "static function in intel_sprite.c is not

[Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

From: Mahesh Kumar NV12 requires WM calculation for UV plane as well. UV plane WM should also fulfill all the WM related restrictions. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_drv.h |

[Intel-gfx] [PATCH 01/16] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

From: Mahesh Kumar skl_wm_values struct contains values of pipe/plane DDB only. so rename it for better readability of code. Similarly skl_copy_wm_for_pipe copies DDB values. s/skl_wm_values/skl_ddb_values s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe Changes since V1:

[Intel-gfx] [PATCH 00/16] Adding NV12 support

This patch series is adding NV12 support for Broxton display after rebasing on latest drm-tip. Initial series of the patches can be found here: https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html Previous revision history: The first version of patches were reviewed when floated

[Intel-gfx] [PATCH 12/16] drm/i915: Upscale scaler max scale for NV12

From: Chandra Konduru This patch updates scaler max limit support for NV12 v2: Rebased (me) v3: Rebased (me) v4: Missed the Tested-by/Reviewed-by in the previous series Adding the same to commit message in this version. v5: Addressed review comments from Ville and

[Intel-gfx] [PATCH 07/16] drm/i915/skl+: make sure higher latency level has higher wm value

From: Mahesh Kumar DDB allocation optimization algorithm requires/assumes ddb allocation for any memory C-state level DDB value to be as high as level below. Render decompression requires level WM to be as high as wm level-0. This patch fulfils both the requirements.

[Intel-gfx] [PATCH 02/16] drm/i915/skl+: refactor WM calculation for NV12

From: Mahesh Kumar Current code calculates DDB for planar formats in such a way that we store DDB of plane-0 in plane 1 & vice-versa. In order to make this clean this patch refactors WM/DDB calculation for NV12 planar formats. v2: Addressed review comments by Maarten

[Intel-gfx] [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc

From: Mahesh Kumar Add support of recognizing DRM_FORMAT_NV12 from plane_format register value. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) diff --git

  1   2   >