From: Chandra Konduru
This patch updates scaler max limit support for NV12
v2: Rebased (me)
v3: Rebased (me)
v4: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v5: Addressed review comments from Ville and rebased
- calculation of max
From: Mahesh Kumar
Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable late
From: Mahesh Kumar
NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.
v2: Addressed review comments from Shashank Sharma.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h
From: Mahesh Kumar
Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.
From: Chandra Konduru
This patch adds NV12 to list of supported formats for
primary plane
v2: Rebased (Chandra Konduru)
v3: Rebased (me)
v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats
v5: Rebased (me)
v6: M
From: Chandra Konduru
This patch adds NV12 to format_is_yuv() function
for sprite planes.
v2:
-Use intel_ prefix for format_is_yuv (Ville)
v3: Rebased (me)
v4: Rebased and addressed review comments from Clinton A Taylor.
"static function in intel_sprite.c is not available
to the primary plane
From: Mahesh Kumar
Current code calculates DDB for planar formats in such a way that we
store DDB of plane-0 in plane 1 & vice-versa.
In order to make this clean this patch refactors WM/DDB calculation for
NV12 planar formats.
v2: Addressed review comments by Maarten
v3: Rebased and addressed r
From: Mahesh Kumar
skl_wm_values struct contains values of pipe/plane DDB only.
so rename it for better readability of code. Similarly
skl_copy_wm_for_pipe copies DDB values.
s/skl_wm_values/skl_ddb_values
s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe
Changes since V1:
- also change name of skl
From: Chandra Konduru
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats
v4: Addressed review comments
From: Chandra Konduru
This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (Chandra Konduru)
v3: rebased (me)
v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offs
This patch series is adding NV12 support for Broxton display after rebasing on
latest drm-tip.
Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
Previous revision history:
The first version of patches were reviewed when floated b
If the fb format is YUV, enable the plane CSC mode bits
for the conversion.
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_display.c | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu
On Tue, Feb 13, 2018 at 8:59 PM Vidya Srinivas
wrote:
> This patch series is adding NV12 support for Broxton display after
rebasing on
> latest drm-tip.
> Initial series of the patches can be found here:
> https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
I still don't see su
== Series Details ==
Series: series starting with [1/3] Revert "ALSA: hda: Make use of core codec
functions to sync power state"
URL : https://patchwork.freedesktop.org/series/38212/
State : success
== Summary ==
Test pm_rpm:
Subgroup gem-mmap-cpu:
fail -> PASS
Hi, here's current gvt-fixes pull for 4.16-rc2, as it is close for
chinese new year, team would take one week off at least, so like to
send this out before vacation. This has one to fix GTT mmio 8b access
from guest and two simple ones for mmio switch and typo fix. And sorry
that patchwork link is
== Series Details ==
Series: Adding NV12 support (rev10)
URL : https://patchwork.freedesktop.org/series/28103/
State : failure
== Summary ==
Series 28103v10 Adding NV12 support
https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/10/mbox/
Test debugfs_test:
Subgroup read_a
On Tue, 13 Feb 2018, José Roberto de Souza wrote:
> When PSR/PSR2 is enabled hardware can do AUX transactions by it self, so
> lets use the mutex register that is available in gen9+ to avoid concurrent
> access by hardware and driver.
>
> Reference:
> https://01.org/sites/default/files/documentat
Introduce a helper to determine if the current task is an output poll
worker.
This allows us to fix a long-standing deadlock in several DRM drivers
wherein the ->runtime_suspend callback waits for the output poll worker
to finish and the worker in turn calls a ->detect callback which waits
for run
v2: Add dri-devel mailing list to the CC list(Jani)
v3: Change names, add missing masks (Manasi)
v4: Add missing shifts to mask (Manasi)
v5: Arrange the definitions in ascending order
of the address (Jani)
Cc: dri-de...@lists.freedesktop.org
Cc: Ville Syrjala
Cc: Jani Nikula
Cc: Manasi Navare
Thanks for sharing the results Marta and Jani.
I'll fix it and send the updated patch soon.
Warm Regards,
Abhijeet
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Tue, 13 Feb 2018 08:34:40 +0100,
Saarinen, Jani wrote:
>
> HI,
> > -Original Message-
> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> > Of
> > Takashi Iwai
> > Sent: tiistai 13. helmikuuta 2018 7.11
> > To: Chris Wilson
> > Cc: intel-gfx@lists.freedes
Hi,
> -Original Message-
> From: Takashi Iwai [mailto:ti...@suse.de]
> Sent: tiistai 13. helmikuuta 2018 10.14
> To: Saarinen, Jani
> Cc: Chris Wilson ; intel-gfx@lists.freedesktop.org;
> Kumar, Abhijeet
> Subject: Re: [Intel-gfx] [PATCH] AWOOGA: Revert "ALSA: hda: Make use of core
> cod
On 2/13/2018 1:44 PM, Takashi Iwai wrote:
On Tue, 13 Feb 2018 08:34:40 +0100,
Saarinen, Jani wrote:
HI,
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Takashi Iwai
Sent: tiistai 13. helmikuuta 2018 7.11
To: Chris Wilson
Cc: intel-gfx@
Hi,
On 2/7/2018 10:12 PM, Sharma, Shashank wrote:
Regards
Shashank
On 2/6/2018 6:28 PM, Vidya Srinivas wrote:
From: Mahesh Kumar
NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.
Signed-off-by: Mahesh Kumar
---
drivers/
On Tue, 13 Feb 2018 09:26:32 +0100,
Saarinen, Jani wrote:
>
> Hi,
> > -Original Message-
> > From: Takashi Iwai [mailto:ti...@suse.de]
> > Sent: tiistai 13. helmikuuta 2018 10.14
> > To: Saarinen, Jani
> > Cc: Chris Wilson ;
> > intel-gfx@lists.freedesktop.org;
> > Kumar, Abhijeet
> >
On 2/13/2018 2:00 PM, Takashi Iwai wrote:
On Tue, 13 Feb 2018 09:26:32 +0100,
Saarinen, Jani wrote:
Hi,
-Original Message-
From: Takashi Iwai [mailto:ti...@suse.de]
Sent: tiistai 13. helmikuuta 2018 10.14
To: Saarinen, Jani
Cc: Chris Wilson ; intel-gfx@lists.freedesktop.org;
Kumar, A
On Mon, Feb 12, 2018 at 01:58:32PM -0500, Alex Deucher wrote:
> On Mon, Feb 12, 2018 at 4:45 AM, Lukas Wunner wrote:
> > On Mon, Feb 12, 2018 at 09:03:26AM +, Mike Lothian wrote:
> >> On 12 February 2018 at 03:39, Lukas Wunner wrote:
> >> > On Mon, Feb 12, 2018 at 12:35:51AM +, Mike Lothi
Quoting Takashi Iwai (2018-02-13 08:30:52)
> On Tue, 13 Feb 2018 09:26:32 +0100,
> Saarinen, Jani wrote:
> >
> > Hi,
> > > -Original Message-
> > > From: Takashi Iwai [mailto:ti...@suse.de]
> > > Sent: tiistai 13. helmikuuta 2018 10.14
> > > To: Saarinen, Jani
> > > Cc: Chris Wilson ;
>
On Tuesday 06 February 2018 16:21:43 Pali Rohár wrote:
> Hi! I'm periodically getting following message in dmesg on Lenovo
> Thinkpad X1 Carbon 3rd generation:
>
> [drm] Reducing the compressed framebuffer size. This may lead to less power
> savings than a non-reduced-size. Try to increase stolen
Op 12-02-18 om 21:55 schreef Chris Wilson:
> Quoting Ville Syrjälä (2018-02-12 18:06:58)
>> On Mon, Feb 12, 2018 at 05:24:54PM +, Chris Wilson wrote:
>>> Quoting Ville Syrjälä (2018-02-12 16:55:28)
On Mon, Feb 12, 2018 at 04:41:05PM +0100, Maarten Lankhorst wrote:
> Op 12-02-18 om 16:3
From: Abhijeet Kumar
Finite loop was causing few igt@pm_rpm tests failure for HSW and BDW.
Thus changing it back to infinite one.
References: https://bugs.freedesktop.org/show_bug.cgi?id=105069
Signed-off-by: Abhijeet Kumar
---
sound/hda/hdac_device.c | 4 ++--
1 file changed, 2 insertions(+)
When a request is preempted, it is unsubmitted from the HW queue and
removed from the active list of breadcrumbs. In the process, this
however triggers the signaler and it may see the clear rbtree with the
old, and still valid, seqno, or it may match the cleared seqno with the
now zero rq->global_s
On Tue, 13 Feb 2018 10:09:48 +0100,
abhijeet.ku...@intel.com wrote:
>
> From: Abhijeet Kumar
>
> Finite loop was causing few igt@pm_rpm tests failure for HSW and BDW.
> Thus changing it back to infinite one.
This missing the explanation why the finite loop fails.
I can guess, but some more deta
On 13/02/18 07:38, Rodrigo Vivi wrote:
These patches failed to cherry-pick on drm-intel-fixes
Please provide a backport or advise how to proceed.
fd10e2ce9905 ("drm/i915/breadcrumbs: Ignore unsubmitted signalers")
1fe699e30113 ("drm/i915/pmu: Fix sleep under atomic in RC6 readout")
I'm bui
icl offers a much reduced context space, and in its simplest setup we
cannot allocate one context per priority level, so trim the number and
reuse the same context for multiple priority requests.
Signed-off-by: Chris Wilson
---
tests/gem_exec_schedule.c | 38 +++--
From: Tvrtko Ursulin
Commit 99e48bf98dd0 ("drm/i915: Lock out execlist tasklet while peeking
inside for busy-stats") added a tasklet_disable call in busy stats
enabling, but we failed to understand that the PMU enable callback runs
as an hard IRQ (IPI).
Consequence of this is that the PMU enable
From: Chris Wilson
As we peek inside struct device to query members guarded by CONFIG_PM,
so must be the code.
Reported-by: kbuild test robot
Fixes: 1fe699e30113 ("drm/i915/pmu: Fix sleep under atomic in RC6 readout")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
From: Chris Wilson
In order to prevent a race condition where we may end up overaccounting
the active state and leaving the busy-stats believing the GPU is 100%
busy, lock out the tasklet while we reconstruct the busy state. There is
no direct spinlock guard for the execlists->port[], so we need
From: Tvrtko Ursulin
We are not allowed to call intel_runtime_pm_get from the PMU counter read
callback since the former can sleep, and the latter is running under IRQ
context.
To workaround this, we record the last known RC6 and while runtime
suspended estimate its increase by querying the runt
On Tue, 13 Feb 2018, Tvrtko Ursulin wrote:
> On 13/02/18 07:38, Rodrigo Vivi wrote:
>>
>> These patches failed to cherry-pick on drm-intel-fixes
>>
>> Please provide a backport or advise how to proceed.
>>
>> fd10e2ce9905 ("drm/i915/breadcrumbs: Ignore unsubmitted signalers")
>> 1fe699e30113 ("
== Series Details ==
Series: ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()
URL : https://patchwork.freedesktop.org/series/38140/
State : success
== Summary ==
Series 38140v1 ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()
https://patchwork.freedesktop.org/api/1.
== Series Details ==
Series: drm/i915/breadcrumbs: Ignore unsubmitted signalers (rev2)
URL : https://patchwork.freedesktop.org/series/37724/
State : failure
== Summary ==
Applying: drm/i915/breadcrumbs: Ignore unsubmitted signalers
error: Failed to merge in the changes.
Using index info to rec
Quoting Patchwork (2018-02-13 09:42:41)
> == Series Details ==
>
> Series: ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()
> URL : https://patchwork.freedesktop.org/series/38140/
> State : success
>
> == Summary ==
>
> Series 38140v1 ALSA: hda: Remove finite loop from snd_hdac_s
This patch series is adding NV12 support for Broxton display after rebasing on
latest drm-tip.
Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
Previous revision history:
The first version of patches were reviewed when floated b
From: Mahesh Kumar
skl_wm_values struct contains values of pipe/plane DDB only.
so rename it for better readability of code. Similarly
skl_copy_wm_for_pipe copies DDB values.
s/skl_wm_values/skl_ddb_values
s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe
Changes since V1:
- also change name of skl
From: Chandra Konduru
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling
v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler
v3: Rebased (me)
v
From: Mahesh Kumar
Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable late
From: Mahesh Kumar
Current code calculates DDB for planar formats in such a way that we
store DDB of plane-0 in plane 1 & vice-versa.
In order to make this clean this patch refactors WM/DDB calculation for
NV12 planar formats.
v2: Addressed review comments by Maarten
v3: Rebased and addressed r
From: Mahesh Kumar
DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below the
current level. Render decompression requires level WM to be as high as
wm level-0. This patch fulfils both the requirements.
Signed-off
From: Mahesh Kumar
This patch splits skl_compute_wm/ddb functions into two parts.
One adds all affected pipes after the commit to atomic_state structure
and second part does compute the DDB.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 157 ++---
From: Mahesh Kumar
For YUV 420 Planar formats like NV12,
buffer allocation is done for Y and UV surfaces separately.
For NV12 plane formats, the UV buffer
allocation must be programmed in the Plane Buffer Config register
and the Y buffer allocation must be programmed in the
Plane NV12 Buffer Conf
From: Mahesh Kumar
Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.
From: Mahesh Kumar
This patch passes skl_wm_level structure itself to watermark
computation function skl_compute_plane_wm function (instead
of its internal parameters). It reduces number of arguments
required to be passed.
v2: Addressed review comments by Shashank Sharma
Reviewed-by: Shashank S
From: Chandra Konduru
This patch updates scaler max limit support for NV12
v2: Rebased (me)
v3: Rebased (me)
v4: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v5: Addressed review comments from Ville and rebased
- calculation of max
From: Chandra Konduru
This patch adds NV12 to format_is_yuv() function
for sprite planes.
v2:
-Use intel_ prefix for format_is_yuv (Ville)
v3: Rebased (me)
v4: Rebased and addressed review comments from Clinton A Taylor.
"static function in intel_sprite.c is not available
to the primary plane
From: Mahesh Kumar
NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.
v2: Addressed review comments from Shashank Sharma.
Signed-off-by: Mahesh Kumar
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
dr
From: Chandra Konduru
This patch adds NV12 to list of supported formats for
primary plane
v2: Rebased (Chandra Konduru)
v3: Rebased (me)
v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats
v5: Rebased (me)
v6: M
If the fb format is YUV, enable the plane CSC mode bits
for the conversion.
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_display.c | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu
From: Chandra Konduru
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats
v4: Addressed review comments
From: Chandra Konduru
This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (Chandra Konduru)
v3: rebased (me)
v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offs
From: Chris Wilson
In order to prevent a race condition where we may end up overaccounting
the active state and leaving the busy-stats believing the GPU is 100%
busy, lock out the tasklet while we reconstruct the busy state. There is
no direct spinlock guard for the execlists->port[], so we need
From: Tvrtko Ursulin
We are not allowed to call intel_runtime_pm_get from the PMU counter read
callback since the former can sleep, and the latter is running under IRQ
context.
To workaround this, we record the last known RC6 and while runtime
suspended estimate its increase by querying the runt
From: Tvrtko Ursulin
Commit 99e48bf98dd0 ("drm/i915: Lock out execlist tasklet while peeking
inside for busy-stats") added a tasklet_disable call in busy stats
enabling, but we failed to understand that the PMU enable callback runs
as an hard IRQ (IPI).
Consequence of this is that the PMU enable
From: Chris Wilson
As we peek inside struct device to query members guarded by CONFIG_PM,
so must be the code.
Reported-by: kbuild test robot
Fixes: 1fe699e30113 ("drm/i915/pmu: Fix sleep under atomic in RC6 readout")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
On 2/13/2018 3:15 PM, Chris Wilson wrote:
Quoting Patchwork (2018-02-13 09:42:41)
== Series Details ==
Series: ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()
URL : https://patchwork.freedesktop.org/series/38140/
State : success
== Summary ==
Series 38140v1 ALSA: hda: Remov
From: Abhijeet Kumar
Finite loop and msleep was causing few igt@pm_rpm tests failure
for HSW and BDW. Thus removing them.
Fixes: 3b5b899ca67d ("ALSA: hda: Make use of core codec functions to
sync power state")
References: https://bugs.freedesktop.org/show_bug.cgi?id=105069
Signe
Op 12-02-18 om 18:01 schreef Ville Syrjälä:
> On Fri, Feb 09, 2018 at 06:21:08PM +0100, Maarten Lankhorst wrote:
>> Op 09-02-18 om 11:04 schreef Chris Wilson:
>>> Quoting Maarten Lankhorst (2018-02-09 09:53:59)
Some cleanups to move the uncore.lock around vblank evasion, so run
to complet
== Series Details ==
Series: Adding NV12 support (rev9)
URL : https://patchwork.freedesktop.org/series/28103/
State : failure
== Summary ==
Series 28103v9 Adding NV12 support
https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/9/mbox/
Test debugfs_test:
Subgroup read_all_
On Tue, 2018-02-13 at 15:22 +0530, Vidya Srinivas wrote:
> From: Mahesh Kumar
>
> Add support of recognizing DRM_FORMAT_NV12 from plane_format
> register value.
>
Reviewed-by: Mika Kahola
> Signed-off-by: Mahesh Kumar
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 ++
> 1 file changed, 2
Hi,
Still fails.
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Patchwork
> Sent: tiistai 13. helmikuuta 2018 11.43
> To: Kumar, Abhijeet
> Cc: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] ✓ Fi.CI.BAT: success for ALSA: h
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, February 9, 2018 9:09 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Lin, Johnson ;
>Syrjala, Ville ; Lankhorst, Maarten
>
>Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix Limited Ra
Quoting Maarten Lankhorst (2018-02-13 10:19:42)
> Op 12-02-18 om 18:01 schreef Ville Syrjälä:
> > On Fri, Feb 09, 2018 at 06:21:08PM +0100, Maarten Lankhorst wrote:
> >> Op 09-02-18 om 11:04 schreef Chris Wilson:
> >>> Quoting Maarten Lankhorst (2018-02-09 09:53:59)
> Some cleanups to move the
Hi Lukas,
On Sun, Feb 11, 2018 at 10:38:28AM +0100, Lukas Wunner wrote:
> Fix a deadlock on hybrid graphics laptops that's been present since 2013:
>
> DRM drivers poll connectors in 10 sec intervals. The poll worker is
> stopped on ->runtime_suspend with cancel_delayed_work_sync(). However
> t
== Series Details ==
Series: ALSA: hda: Remove finite loop from snd_hdac_sync_power_state() (rev2)
URL : https://patchwork.freedesktop.org/series/38140/
State : success
== Summary ==
Series 38140v2 ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()
https://patchwork.freedesktop.org
Hi Mika,
Thanks for the review.
Please find my comments inline:
On 2/12/2018 8:04 PM, Kahola, Mika wrote:
On Wed, 2018-01-24 at 18:20 +0530, Nautiyal, Ankit K wrote:
From: Ankit Nautiyal
This patch adds the support to print the aspect ratio of the modes
(if provided) along with other mode
From: Tvrtko Ursulin
Gen11 will add more VCS and VECS rings so prepare the
infrastructure to support that.
Bspec: 7021
v2: Rebase.
v3: Rebase.
v4: Rebase.
v5: Rebase.
v6:
- Update for POR changes. (Daniele Ceraolo Spurio)
- Add provisional guc engine ids - to be checked and confirmed.
v7:
On Tue, Feb 13, 2018 at 10:55:06AM +, Liviu Dudau wrote:
> On Sun, Feb 11, 2018 at 10:38:28AM +0100, Lukas Wunner wrote:
> > DRM drivers poll connectors in 10 sec intervals. The poll worker is
> > stopped on ->runtime_suspend with cancel_delayed_work_sync(). However
> > the poll worker invoke
igt_partial_tiling managed to fail with an -EBUSY. This usually means a
pin leak, but that should be impossible given the test setup. Add a
couple of error messages to help identify the path that failed.
References: https://bugs.freedesktop.org/show_bug.cgi?id=105073
Signed-off-by: Chris Wilson
-
== Series Details ==
Series: drm/i915/icl: Prepare for more rings
URL : https://patchwork.freedesktop.org/series/38150/
State : success
== Summary ==
Series 38150v1 drm/i915/icl: Prepare for more rings
https://patchwork.freedesktop.org/api/1.0/series/38150/revisions/1/mbox/
Test gem_exec_relo
Chris Wilson writes:
> igt_partial_tiling managed to fail with an -EBUSY. This usually means a
> pin leak, but that should be impossible given the test setup. Add a
> couple of error messages to help identify the path that failed.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=10507
== Series Details ==
Series: drm/i915/selftests: Report setup errors for igt_partial_tiling
URL : https://patchwork.freedesktop.org/series/38154/
State : success
== Summary ==
Series 38154v1 drm/i915/selftests: Report setup errors for igt_partial_tiling
https://patchwork.freedesktop.org/api/1.
On 2/13/2018 3:54 PM, abhijeet.ku...@intel.com wrote:
From: Abhijeet Kumar
Finite loop and msleep was causing few igt@pm_rpm tests failure
for HSW and BDW. Thus removing them.
Fixes: 3b5b899ca67d ("ALSA: hda: Make use of core codec functions to
sync power state")
References:
Quoting Mika Kuoppala (2018-02-13 12:17:51)
> Chris Wilson writes:
>
> > igt_partial_tiling managed to fail with an -EBUSY. This usually means a
> > pin leak, but that should be impossible given the test setup. Add a
> > couple of error messages to help identify the path that failed.
> >
> > Refe
Quoting Kumar, Abhijeet (2018-02-13 12:41:42)
>
>
> On 2/13/2018 3:54 PM, abhijeet.ku...@intel.com wrote:
>
> From: Abhijeet Kumar
>
> Finite loop and msleep was causing few igt@pm_rpm tests failure
> for HSW and BDW. Thus removing them.
>
> Fixes: 3b5b899ca67d ("ALSA: hda: Ma
On Tue, 13 Feb 2018, abhijeet.ku...@intel.com wrote:
> From: Abhijeet Kumar
>
> Finite loop and msleep was causing few igt@pm_rpm tests failure
> for HSW and BDW. Thus removing them.
>
> Fixes: 3b5b899ca67d ("ALSA: hda: Make use of core codec functions to
> sync power state")
Side n
On Mon, Feb 12, 2018 at 10:21:11PM +, Chris Wilson wrote:
> Cc: Ville Syrjälä
> Cc: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_sprite.c | 65
> ++---
> 1 file changed, 38 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_sp
On 2/13/2018 6:17 PM, Chris Wilson wrote:
Quoting Kumar, Abhijeet (2018-02-13 12:41:42)
On 2/13/2018 3:54 PM, abhijeet.ku...@intel.com wrote:
From: Abhijeet Kumar
Finite loop and msleep was causing few igt@pm_rpm tests failure
for HSW and BDW. Thus removing them.
Fixes
On Tue, Feb 13, 2018 at 09:50:30AM +0100, Pali Rohár wrote:
> On Tuesday 06 February 2018 16:21:43 Pali Rohár wrote:
> > Hi! I'm periodically getting following message in dmesg on Lenovo
> > Thinkpad X1 Carbon 3rd generation:
> >
> > [drm] Reducing the compressed framebuffer size. This may lead to
On Tue, 13 Feb 2018 13:47:25 +0100,
Chris Wilson wrote:
>
> Quoting Kumar, Abhijeet (2018-02-13 12:41:42)
> >
> >
> > On 2/13/2018 3:54 PM, abhijeet.ku...@intel.com wrote:
> >
> > From: Abhijeet Kumar
> >
> > Finite loop and msleep was causing few igt@pm_rpm tests failure
> > for
On Tuesday 13 February 2018 15:27:26 Ville Syrjälä wrote:
> On Tue, Feb 13, 2018 at 09:50:30AM +0100, Pali Rohár wrote:
> > On Tuesday 06 February 2018 16:21:43 Pali Rohár wrote:
> > > Hi! I'm periodically getting following message in dmesg on Lenovo
> > > Thinkpad X1 Carbon 3rd generation:
> > >
On 12/02/2018 21:11, Chris Wilson wrote:
When we need to rebind the vma into the global GTT for snb, we need to
drop the current reloc_cache as it will be holding a kmap_atomic() and
we may need to sleep for i915_vma_bind(). In practice, this is not an
issue as we already hold an rpm reference f
Quoting Tvrtko Ursulin (2018-02-13 13:42:03)
>
> On 12/02/2018 21:11, Chris Wilson wrote:
> > When we need to rebind the vma into the global GTT for snb, we need to
> > drop the current reloc_cache as it will be holding a kmap_atomic() and
> > we may need to sleep for i915_vma_bind(). In practice,
Quoting Chris Wilson (2018-02-13 13:45:33)
> Quoting Tvrtko Ursulin (2018-02-13 13:42:03)
> >
> > On 12/02/2018 21:11, Chris Wilson wrote:
> > > When we need to rebind the vma into the global GTT for snb, we need to
> > > drop the current reloc_cache as it will be holding a kmap_atomic() and
> > >
Am 12.02.2018 um 18:14 schrieb Ville Syrjälä:
On Mon, Feb 12, 2018 at 02:55:33PM +, Chris Wilson wrote:
Use the new idr_init_base() function to create an IDR that knows id==0
is never allocated as it maps to an invalid identifier. By knowing that
id==0 is invalid, the IDR can start from id=1
On 2/13/2018 6:17 PM, Chris Wilson wrote:
Quoting Kumar, Abhijeet (2018-02-13 12:41:42)
On 2/13/2018 3:54 PM, abhijeet.ku...@intel.com wrote:
From: Abhijeet Kumar
Finite loop and msleep was causing few igt@pm_rpm tests failure
for HSW and BDW. Thus removing them.
Fixes
On 13/02/2018 13:46, Chris Wilson wrote:
Quoting Chris Wilson (2018-02-13 13:45:33)
Quoting Tvrtko Ursulin (2018-02-13 13:42:03)
On 12/02/2018 21:11, Chris Wilson wrote:
When we need to rebind the vma into the global GTT for snb, we need to
drop the current reloc_cache as it will be holding
On 08/02/2018 16:04, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-02-08 16:00:36)
From: Tvrtko Ursulin
We can implement limited RC6 counter wrap-around protection under the
assumption that clients will be reading this value more frequently than
the wrap period on a given platform.
With t
== Series Details ==
Series: ALSA: hda: Remove finite loop from snd_hdac_sync_power_state() (rev2)
URL : https://patchwork.freedesktop.org/series/38140/
State : warning
== Summary ==
Test kms_vblank:
Subgroup pipe-a-wait-forked:
pass -> SKIP (shard-snb)
Test
From: Tvrtko Ursulin
Header uses I915_NUM_ENGINES so needs to include i915.gem.h, and also
it uses requests so we can forward declare struct drm_i915_gem_request.
Signed-off-by: Tvrtko Ursulin
Suggested-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.h | 3 +++
1 file changed, 3 in
Quoting Tvrtko Ursulin (2018-02-13 14:18:33)
> From: Tvrtko Ursulin
>
> Header uses I915_NUM_ENGINES so needs to include i915.gem.h, and also
> it uses requests so we can forward declare struct drm_i915_gem_request.
>
> Signed-off-by: Tvrtko Ursulin
> Suggested-by: Chris Wilson
Reviewed-by: Ch
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