[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable VBT based BL control for DP (v3)

== Series Details == Series: drm/i915: Enable VBT based BL control for DP (v3) URL : https://patchwork.freedesktop.org/series/38559/ State : success == Summary == Series 38559v1 drm/i915: Enable VBT based BL control for DP (v3)

[Intel-gfx] [V3] drm/i915: Enable VBT based BL control for DP

Currently, BXT_PP is hardcoded with value '0'. It practically disabled eDP backlight on MRB (BXT) platform. This patch will tell which BXT_PP registers (there are two set of PP_CONTROL in the spec) to be used as defined in VBT (Video Bios Timing table) and this will enabled eDP backlight

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable VBT based BL control for DP (v3)

== Series Details == Series: drm/i915: Enable VBT based BL control for DP (v3) URL : https://patchwork.freedesktop.org/series/38559/ State : warning == Summary == $ dim checkpatch origin/drm-tip 50f1199ece18 drm/i915: Enable VBT based BL control for DP (v3) -:9: WARNING: Possible unwrapped

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] igt/gem_sync: Exercise and measure idle requests

== Series Details == Series: series starting with [1/2] igt/gem_sync: Exercise and measure idle requests URL : https://patchwork.freedesktop.org/series/38550/ State : success == Summary == IGT patchset tested on top of latest successful build 6fc91dbb67eea6824100905a4ab1fb38f186dba0

[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/2] igt/gem_sync: Exercise and measure idle requests

== Series Details == Series: series starting with [1/2] igt/gem_sync: Exercise and measure idle requests URL : https://patchwork.freedesktop.org/series/38550/ State : warning == Summary == Test perf: Subgroup buffer-fill: fail -> PASS (shard-apl)

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] lib: Always set mismatching index for igt_find_crc_mismatch

== Series Details == Series: series starting with [1/4] lib: Always set mismatching index for igt_find_crc_mismatch URL : https://patchwork.freedesktop.org/series/38547/ State : success == Summary == Test kms_sysfs_edid_timing: pass -> WARN (shard-apl) fdo#100047

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm: Add COLOR_ENCODING and COLOR_RANGE plane properties (rev3)

== Series Details == Series: drm: Add COLOR_ENCODING and COLOR_RANGE plane properties (rev3) URL : https://patchwork.freedesktop.org/series/38286/ State : failure == Summary == Test gem_exec_capture: Subgroup capture-vebox: pass -> INCOMPLETE (shard-apl) Test

Re: [Intel-gfx] [PATCH 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane

On 19/02/18 22:19, Ville Syrjälä wrote: >>> +int drm_plane_create_color_properties(struct drm_plane *plane, >>> + u32 supported_encodings, >>> + u32 supported_ranges, >> Is 0 in the above two supported_ masks a valid value? If yes,

[Intel-gfx] [PATCH] drm/i915: Enable VBT based BL control for DP (v3)

Currently, BXT_PP is hardcoded with value '0'. It practically disabled eDP backlight on MRB (BXT) platform. This patch will tell which BXT_PP registers (there are two set of PP_CONTROL in the spec) to be used as defined in VBT (Video Bios Timing table) and this will enabled eDP backlight

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Track number of pending freed objects (rev2)

== Series Details == Series: drm/i915: Track number of pending freed objects (rev2) URL : https://patchwork.freedesktop.org/series/38537/ State : warning == Summary == Test gem_eio: Subgroup in-flight: pass -> FAIL (shard-hsw) fdo#104676 Test

[Intel-gfx] [V3] drm/i915: Enable VBT based BL control for DP

Currently, BXT_PP is hardcoded with value '0'. It practically disabled eDP backlight on MRB (BXT) platform. This patch will tell which BXT_PP registers (there are two set of PP_CONTROL in the spec) to be used as defined in VBT (Video Bios Timing table) and this will enabled eDP backlight

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable VBT based BL control for DP (v3) (rev2)

== Series Details == Series: drm/i915: Enable VBT based BL control for DP (v3) (rev2) URL : https://patchwork.freedesktop.org/series/38559/ State : warning == Summary == $ dim checkpatch origin/drm-tip 10e3cca20783 drm/i915: Enable VBT based BL control for DP -:9: WARNING: Possible unwrapped

[Intel-gfx] [PATCH] drm/i915: fix the issue DP-1 not working in guest

In GVT guest, when port A is DP, i915 will force it as an EDP panel, which will cause DP-1 not working in GVT guest. This patch fixed this issue by check intel_vgpu_active() in intel_ddi_compute_config(). Signed-off-by: Min He Signed-off-by: Nuhairi Anuar

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable VBT based BL control for DP (v3)

== Series Details == Series: drm/i915: Enable VBT based BL control for DP (v3) URL : https://patchwork.freedesktop.org/series/38559/ State : success == Summary == Test kms_setmode: Subgroup basic: pass -> FAIL (shard-hsw) fdo#99912 Test perf:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable VBT based BL control for DP (v3) (rev3)

== Series Details == Series: drm/i915: Enable VBT based BL control for DP (v3) (rev3) URL : https://patchwork.freedesktop.org/series/38559/ State : success == Summary == Series 38559v3 drm/i915: Enable VBT based BL control for DP (v3)

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: fix the issue DP-1 not working in guest (rev2)

== Series Details == Series: drm/i915: fix the issue DP-1 not working in guest (rev2) URL : https://patchwork.freedesktop.org/series/25753/ State : failure == Summary == Test perf: Subgroup buffer-fill: fail -> PASS (shard-apl) fdo#103755 Test kms_flip:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable VBT based BL control for DP (v3) (rev2)

== Series Details == Series: drm/i915: Enable VBT based BL control for DP (v3) (rev2) URL : https://patchwork.freedesktop.org/series/38559/ State : success == Summary == Series 38559v2 drm/i915: Enable VBT based BL control for DP (v3)

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: fix the issue DP-1 not working in guest (rev2)

== Series Details == Series: drm/i915: fix the issue DP-1 not working in guest (rev2) URL : https://patchwork.freedesktop.org/series/25753/ State : success == Summary == Series 25753v2 drm/i915: fix the issue DP-1 not working in guest

Re: [Intel-gfx] [PATCH] drm/i915: Release connector iterator on a digital port conflict.

Op 16-02-18 om 00:38 schreef Rodrigo Vivi: > On Thu, Feb 15, 2018 at 10:14:25AM +0100, Maarten Lankhorst wrote: >> <4>[ 30.702366] >> <4>[ 30.702383] WARNING: lock held when returning to user space! >> <4>[ 30.702404] 4.16.0-rc1-CI-kasan_1+ #1

Re: [Intel-gfx] [PATCH i-g-t] perf_pmu: Fix some compile warnings with old compilers / 32-bit builds

Quoting Tvrtko Ursulin (2018-02-19 10:04:08) > From: Tvrtko Ursulin > > Correct printf format for uint64_t and one "may be uninitialized". > > Signed-off-by: Tvrtko Ursulin > Reported-by: Chris Wilson Fixing those

[Intel-gfx] [PATCH 1/2] drm/mm: Fix caching of leftmost node in the interval tree

When we descend the tree to find our slot, if we step to the right, we are no longer the leftmost node. Fixes: f808c13fd373 ("lib/interval_tree: fast overlap detection") Signed-off-by: Chris Wilson Cc: Davidlohr Bueso Cc: Jérôme Glisse

[Intel-gfx] [PATCH 2/2] drm/mm: Micro-optimise updating the upper layers of the interval tree

When we insert a node into a hole inside the interval tree, we need to climb the layers above us to update the cached interval. When doing so, we know that the initial node exists as it is our starting hole. add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-10 (-10) Function

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/mm: Fix caching of leftmost node in the interval tree

== Series Details == Series: series starting with [1/2] drm/mm: Fix caching of leftmost node in the interval tree URL : https://patchwork.freedesktop.org/series/38493/ State : success == Summary == Series 38493v1 series starting with [1/2] drm/mm: Fix caching of leftmost node in the

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: deprecate pci_get_bus_and_slot()

== Series Details == Series: drm/i915: deprecate pci_get_bus_and_slot() URL : https://patchwork.freedesktop.org/series/34822/ State : failure == Summary == Series 34822v1 drm/i915: deprecate pci_get_bus_and_slot() https://patchwork.freedesktop.org/api/1.0/series/34822/revisions/1/mbox/ Test

Re: [Intel-gfx] [PATCH V3 09/29] drm/i915: deprecate pci_get_bus_and_slot()

Quoting Jani Nikula (2018-02-19 11:34:34) > On Fri, 16 Feb 2018, Bjorn Helgaas wrote: > > On Mon, Nov 27, 2017 at 11:57:46AM -0500, Sinan Kaya wrote: > >> pci_get_bus_and_slot() is restrictive such that it assumes domain=0 as > >> where a PCI device is present. This restricts

[Intel-gfx] [PATCH i-g-t] perf_pmu: Fix some compile warnings with old compilers / 32-bit builds

From: Tvrtko Ursulin Correct printf format for uint64_t and one "may be uninitialized". Signed-off-by: Tvrtko Ursulin Reported-by: Chris Wilson --- tests/perf_pmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2

[Intel-gfx] [4.9-stable 2/9] drm/i915: hide unused intel_panel_set_backlight function

commit fd94d53e55bd487368dfee9f1af24da78b2bb582 upstream. Building i915 without backlight support results in a harmless warning for intel_panel_set_backlight: drivers/gpu/drm/i915/intel_panel.c:653:13: error: 'intel_panel_set_backlight' defined but not used [-Werror=unused-function] This moves

Re: [Intel-gfx] [PATCH 4/5] drm/i915/frontbuffer: Remove early frontbuffer flush in prepare_plane_fb()

Op 16-02-18 om 20:27 schreef Pandiyan, Dhinakaran: > On Fri, 2018-02-16 at 08:55 +, Chris Wilson wrote: >> Quoting Dhinakaran Pandiyan (2018-02-16 04:33:21) >>> Preparing a framebuffer should not require a flush. _post_plane_update() >>> takes care of flushing when a flip is scheduled, this

[Intel-gfx] [PATCH v2] drm/i915: Prune gen8_gt_irq_handler

The compiler is not automatically caching the i915->regs address inside a register and emitting a load for every mmio access. For simple functions like gen8_gt_irq_handler that are already using the raw accessors, we can open-code them for substantial savings: add/remove: 0/0 grow/shrink: 0/2

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Use seqlock in engine stats (rev2)

On 16/02/2018 10:13, Chris Wilson wrote: Quoting Patchwork (2018-02-15 23:50:52) == Series Details == Series: drm/i915: Use seqlock in engine stats (rev2) URL : https://patchwork.freedesktop.org/series/38347/ State : failure == Summary == Test perf_pmu: Subgroup busy-start-vcs0:

Re: [Intel-gfx] [PATCH V3 09/29] drm/i915: deprecate pci_get_bus_and_slot()

On Fri, 16 Feb 2018, Bjorn Helgaas wrote: > On Mon, Nov 27, 2017 at 11:57:46AM -0500, Sinan Kaya wrote: >> pci_get_bus_and_slot() is restrictive such that it assumes domain=0 as >> where a PCI device is present. This restricts the device drivers to be >> reused for other

Re: [Intel-gfx] [PATCH 0/6] Add support for in-line nested struct comments

On Sun, 18 Feb 2018, Jonathan Corbet wrote: > On Fri, 16 Feb 2018 11:48:14 -0200 > Mauro Carvalho Chehab wrote: > >> his series fix two bugs at kernel-doc.rst examples and add support >> for in-line nested struct comments. >> >> It also converts one

[Intel-gfx] [PATCH igt] igt/gem_exec_whisper: Fork all-engine tests one-per-engine

Add a new mode for some more stress, submit the all-engines tests simultaneously, a stream per engine. Signed-off-by: Chris Wilson --- tests/gem_exec_whisper.c | 23 --- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v6] tests/perf_pmu: Verify engine busyness accuracy

Quoting Tvrtko Ursulin (2018-02-19 09:19:47) > > Do you have a link to BSW hang? Is that obviously related to PMU? It's only occurring in this test, just looks like an issue with the spinner: [bsw]

Re: [Intel-gfx] Thinkpad X1 Carbon 3rd - Reducing the compressed framebuffer size

On Tuesday 13 February 2018 19:45:56 Ville Syrjälä wrote: > On Tue, Feb 13, 2018 at 06:43:41PM +0100, Pali Rohár wrote: > > On Tuesday 13 February 2018 18:12:21 Ville Syrjälä wrote: > > > On Tue, Feb 13, 2018 at 05:04:37PM +0100, Pali Rohár wrote: > > > > So it can be done only once after reboot?

Re: [Intel-gfx] [PATCH 0/1 RFC] Documentation patch for batchbuffer submission

On Fri, 16 Feb 2018, kevin.rogo...@intel.com wrote: > From: Kevin Rogovin > > This patch attempts to provide text for the kernel documentation on the > subject of batchbuffer submission. The contents of the patch are essentially: > - explain the nature of (PP)GTT and

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v6] tests/perf_pmu: Verify engine busyness accuracy

On 17/02/2018 11:36, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-02-15 15:34:53) From: Tvrtko Ursulin A subtest to verify that the engine busyness is reported with expected accuracy on platforms where the feature is available. We test three patterns: 2%, 50%

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Use seqlock in engine stats (rev2)

Quoting Tvrtko Ursulin (2018-02-19 09:25:00) > > On 16/02/2018 10:13, Chris Wilson wrote: > > Afaict, it's complaining that because the writer is special the reader > > needs irq protection. Which I don't understand, as the point is that the > > writer can run concurrently to the readers (the

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v6] tests/perf_pmu: Verify engine busyness accuracy

On 19/02/2018 09:27, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2018-02-19 09:19:47) >> >> Do you have a link to BSW hang? Is that obviously related to PMU? > > It's only occurring in this test, just looks like an issue with the > spinner: > > [bsw] >

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v6] tests/perf_pmu: Verify engine busyness accuracy

Quoting Tvrtko Ursulin (2018-02-19 10:58:25) > > On 19/02/2018 10:26, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-02-19 09:57:20) > >> > >> On 19/02/2018 09:27, Chris Wilson wrote: > >>> Quoting Tvrtko Ursulin (2018-02-19 09:19:47) > > Do you have a link to BSW hang? Is that

[Intel-gfx] ✓ Fi.CI.BAT: success for igt/perf_pmu: Retain original GTT offset when resubmitting the spinner

== Series Details == Series: igt/perf_pmu: Retain original GTT offset when resubmitting the spinner URL : https://patchwork.freedesktop.org/series/38505/ State : success == Summary == IGT patchset tested on top of latest successful build bf777c92448d51010aba51d1f1b657b0fdc673a6

Re: [Intel-gfx] [PATCH] drm/i915: Remove WARN_ONCE for failing to pm_runtime_if_in_use

On Mon, Feb 19, 2018 at 12:50:46PM +, Chris Wilson wrote: > As the driver is called to handle circumstances beyond it's control, we > cannot assume that the pm_runtime core is happy to see us. For example, > if we are called from shrink_slab to free up our pages during suspend, > rpm may be

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Remove WARN_ONCE for failing to pm_runtime_if_in_use

== Series Details == Series: drm/i915: Remove WARN_ONCE for failing to pm_runtime_if_in_use URL : https://patchwork.freedesktop.org/series/38509/ State : warning == Summary == Series 38509v1 drm/i915: Remove WARN_ONCE for failing to pm_runtime_if_in_use

Re: [Intel-gfx] [PATCH 1/1 RFC] drivers/gpu/drm/i915:Documentation for batchbuffer submission

These documentation improvements are much welcome, here are a few comments from me. Quoting kevin.rogo...@intel.com (2018-02-16 16:04:22) > +Intel GPU Basics > + > + > +An Intel GPU has multiple engines. There are several engine types. > + > +- RCS engine is for rendering 3D and

Re: [Intel-gfx] [PATCH] drm: Handle unexpected holes in color-eviction

Quoting Joonas Lahtinen (2018-02-19 14:40:32) > Quoting Chris Wilson (2018-02-19 13:35:43) > > +++ b/drivers/gpu/drm/drm_mm.c > > @@ -836,9 +836,24 @@ struct drm_mm_node *drm_mm_scan_color_evict(struct > > drm_mm_scan *scan) > > if (!mm->color_adjust) > > return NULL; > >

Re: [Intel-gfx] [Nouveau] [PATCH 0/5] Fix deadlock on runtime suspend in DRM drivers

On Mon, Feb 19, 2018 at 03:05:53PM +0100, Daniel Vetter wrote: > On Mon, Feb 19, 2018 at 12:58:17PM +0100, Lukas Wunner wrote: > > On Mon, Feb 19, 2018 at 12:34:43PM +0100, Daniel Vetter wrote: > > > Well, userspace expects hotplug events, even when we runtime suspend > > > stuff. Hence waking

Re: [Intel-gfx] [CI] drm/i915/cnl: New power domain for AUX IO.

On Fri, Feb 16, 2018 at 04:27:04PM -0800, Rodrigo Vivi wrote: > On Fri, Feb 16, 2018 at 03:25:55PM -0800, Dhinakaran Pandiyan wrote: > > PSR requires AUX IO well to be kept on and the existing AUX domain > > enables other wells too. > > > > Cc: Imre Deak > > >

Re: [Intel-gfx] [PATCH 3/8] drm/atomic: Include color encoding/range in plane state dump

On Wed, Feb 14, 2018 at 09:23:22PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Include color_enconding and color_range in the plane state dump. > > Cc: Harry Wentland > Cc: Daniel Vetter > Cc: Daniel Stone

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Remove WARN_ONCE for failing to pm_runtime_if_in_use

Quoting Patchwork (2018-02-19 13:24:12) > == Series Details == > > Series: drm/i915: Remove WARN_ONCE for failing to pm_runtime_if_in_use > URL : https://patchwork.freedesktop.org/series/38509/ > State : warning > > == Summary == > > Series 38509v1 drm/i915: Remove WARN_ONCE for failing to

Re: [Intel-gfx] [PATCH 0/8] drm: Add COLOR_ENCODING and COLOR_RANGE plane properties

On Wed, Feb 14, 2018 at 09:23:19PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Here's a refresh of Jyri's COLOR_ENCODING and COLOR_RANGE properties, > and the i915 implementation I did on top. I tossed in a few core > updates as well: plane state dump,

[Intel-gfx] [PATCH igt] igt/perf_pmu: Retain original GTT offset when resubmitting the spinner

Since the spin batch contains a relocation to itself, when we resubmit the spinner, we must ensure that it is executed at the same location. While the spinner is busy, resubmitting will reuse the same location, but if it is idle, the kernel may move it between execution. In this case, we need to

Re: [Intel-gfx] [Nouveau] [PATCH 0/5] Fix deadlock on runtime suspend in DRM drivers

On Mon, Feb 19, 2018 at 12:34:43PM +0100, Daniel Vetter wrote: > On Sun, Feb 11, 2018 at 10:38:28AM +0100, Lukas Wunner wrote: > > Fix a deadlock on hybrid graphics laptops that's been present since 2013: > > > > DRM drivers poll connectors in 10 sec intervals. The poll worker is > > stopped on

Re: [Intel-gfx] [PATCH igt] igt/perf_pmu: Retain original GTT offset when resubmitting the spinner

On 19/02/2018 11:17, Chris Wilson wrote: Since the spin batch contains a relocation to itself, when we resubmit the spinner, we must ensure that it is executed at the same location. While the spinner is busy, resubmitting will reuse the same location, but if it is idle, the kernel may move it

[Intel-gfx] [PATCH] drm/i915: Clear the in-use marker on execbuf failure

If we fail to unbind the vma (due to a signal on an active buffer that needs to be moved for the next execbuf), then we need to clear the persistent tracking state we setup for this execbuf. Fixes: c7c6e46f913b ("drm/i915: Convert execbuf to use struct-of-array packing for critical fields")

Re: [Intel-gfx] [PATCH v2] drm/i915: Prune gen8_gt_irq_handler

Chris Wilson writes: > The compiler is not automatically caching the i915->regs address inside > a register and emitting a load for every mmio access. For simple > functions like gen8_gt_irq_handler that are already using the raw > accessors, we can open-code them for

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm: Handle unexpected holes in color-eviction

== Series Details == Series: drm: Handle unexpected holes in color-eviction URL : https://patchwork.freedesktop.org/series/38506/ State : failure == Summary == Test gem_eio: Subgroup in-flight: pass -> FAIL (shard-hsw) fdo#104676 Test kms_flip:

Re: [Intel-gfx] [Nouveau] [PATCH 0/5] Fix deadlock on runtime suspend in DRM drivers

On Mon, Feb 19, 2018 at 03:47:42PM +0100, Lukas Wunner wrote: > On Mon, Feb 19, 2018 at 03:05:53PM +0100, Daniel Vetter wrote: > > On Mon, Feb 19, 2018 at 12:58:17PM +0100, Lukas Wunner wrote: > > > On Mon, Feb 19, 2018 at 12:34:43PM +0100, Daniel Vetter wrote: > > > > Well, userspace expects

Re: [Intel-gfx] [PATCH v2] drm/i915: Prune gen8_gt_irq_handler

Quoting Mika Kuoppala (2018-02-19 13:59:43) > Chris Wilson writes: > > > The compiler is not automatically caching the i915->regs address inside > > a register and emitting a load for every mmio access. For simple > > functions like gen8_gt_irq_handler that are already

Re: [Intel-gfx] [PATCH] drm: Handle unexpected holes in color-eviction

Quoting Chris Wilson (2018-02-19 13:35:43) > +++ b/drivers/gpu/drm/drm_mm.c > @@ -836,9 +836,24 @@ struct drm_mm_node *drm_mm_scan_color_evict(struct > drm_mm_scan *scan) > if (!mm->color_adjust) > return NULL; > > - hole = list_first_entry(>hole_stack,

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Clear the in-use marker on execbuf failure

== Series Details == Series: drm/i915: Clear the in-use marker on execbuf failure URL : https://patchwork.freedesktop.org/series/38515/ State : success == Summary == Series 38515v1 drm/i915: Clear the in-use marker on execbuf failure

Re: [Intel-gfx] [PATCH] drm: Use idr_init_base(1) when using id==0 for invalid

On Mon, Feb 19, 2018 at 02:35:38PM +, Chris Wilson wrote: > Quoting Christian König (2018-02-13 13:48:24) > > Am 12.02.2018 um 18:14 schrieb Ville Syrjälä: > > > On Mon, Feb 12, 2018 at 02:55:33PM +, Chris Wilson wrote: > > >> Use the new idr_init_base() function to create an IDR that

Re: [Intel-gfx] [PATCH 0/8] drm: Add COLOR_ENCODING and COLOR_RANGE plane properties

On Wed, Feb 14, 2018 at 09:23:19PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Here's a refresh of Jyri's COLOR_ENCODING and COLOR_RANGE properties, > and the i915 implementation I did on top. I tossed in a few core > updates as well: plane state dump,

Re: [Intel-gfx] [PATCH] drm/i915: Remove WARN_ONCE for failing to pm_runtime_if_in_use

Quoting Imre Deak (2018-02-19 13:23:47) > On Mon, Feb 19, 2018 at 12:50:46PM +, Chris Wilson wrote: > > As the driver is called to handle circumstances beyond it's control, we > > cannot assume that the pm_runtime core is happy to see us. For example, > > if we are called from shrink_slab to

[Intel-gfx] ✗ Fi.CI.IGT: failure for igt/perf_pmu: Retain original GTT offset when resubmitting the spinner

== Series Details == Series: igt/perf_pmu: Retain original GTT offset when resubmitting the spinner URL : https://patchwork.freedesktop.org/series/38505/ State : failure == Summary == Test gem_exec_suspend: Subgroup basic-s4-devices: incomplete -> PASS

Re: [Intel-gfx] [Nouveau] [PATCH 0/5] Fix deadlock on runtime suspend in DRM drivers

On Mon, Feb 19, 2018 at 12:58:17PM +0100, Lukas Wunner wrote: > On Mon, Feb 19, 2018 at 12:34:43PM +0100, Daniel Vetter wrote: > > On Sun, Feb 11, 2018 at 10:38:28AM +0100, Lukas Wunner wrote: > > > Fix a deadlock on hybrid graphics laptops that's been present since 2013: > > > > > > DRM drivers

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] tests/perf_pmu: Avoid off-lining all CPUs

On 19/02/2018 13:54, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-02-19 13:40:37) From: Tvrtko Ursulin Bail out from the cpu-hotplug test if we failed to bring a CPU back online. This still leaves the machine in a quite bad state, but at least it avoids hard

Re: [Intel-gfx] [PATCH] drm: Use idr_init_base(1) when using id==0 for invalid

Quoting Christian König (2018-02-13 13:48:24) > Am 12.02.2018 um 18:14 schrieb Ville Syrjälä: > > On Mon, Feb 12, 2018 at 02:55:33PM +, Chris Wilson wrote: > >> Use the new idr_init_base() function to create an IDR that knows id==0 > >> is never allocated as it maps to an invalid identifier.

Re: [Intel-gfx] [PATCH] Forward Error Correction is supported on DP 1.4. This patch adds corresponding DPCD register definitions.

On Tue, Feb 13, 2018 at 11:55:35PM -0800, Anusha Srivatsa wrote: > v2: Add dri-devel mailing list to the CC list(Jani) > > v3: Change names, add missing masks (Manasi) > > v4: Add missing shifts to mask (Manasi) > > v5: Arrange the definitions in ascending order > of the address (Jani) > > Cc:

Re: [Intel-gfx] [PATCH 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane

On Wed, Feb 14, 2018 at 09:23:20PM +0200, Ville Syrjala wrote: > From: Jyri Sarha > > Add a standard optional properties to support different non RGB color > encodings in DRM planes. COLOR_ENCODING select the supported non RGB > color encoding, for instance ITU-R BT.709 YCbCr.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Handle unexpected holes in color-eviction

== Series Details == Series: drm: Handle unexpected holes in color-eviction URL : https://patchwork.freedesktop.org/series/38506/ State : warning == Summary == $ dim checkpatch origin/drm-tip 75c60c160f32 drm: Handle unexpected holes in color-eviction -:15: WARNING: Possible unwrapped commit

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v6] tests/perf_pmu: Verify engine busyness accuracy

Quoting Tvrtko Ursulin (2018-02-19 09:57:20) > > On 19/02/2018 09:27, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-02-19 09:19:47) > >> > >> Do you have a link to BSW hang? Is that obviously related to PMU? > > > > It's only occurring in this test, just looks like an issue with the > >

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/mm: Fix caching of leftmost node in the interval tree

== Series Details == Series: series starting with [1/2] drm/mm: Fix caching of leftmost node in the interval tree URL : https://patchwork.freedesktop.org/series/38493/ State : failure == Summary == Test gem_eio: Subgroup in-flight-contexts: dmesg-warn -> PASS

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v6] tests/perf_pmu: Verify engine busyness accuracy

On 19/02/2018 10:26, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-02-19 09:57:20) On 19/02/2018 09:27, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-02-19 09:19:47) Do you have a link to BSW hang? Is that obviously related to PMU? It's only occurring in this test, just looks like

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir (rev2)

== Series Details == Series: series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir (rev2) URL : https://patchwork.freedesktop.org/series/38314/ State : success == Summary == Test kms_cursor_legacy: Subgroup 2x-long-flip-vs-cursor-atomic:

Re: [Intel-gfx] [PATCH 0/5] Fix deadlock on runtime suspend in DRM drivers

On Mon, Feb 19, 2018 at 12:48:04PM +0100, Daniel Vetter wrote: > On Thu, Feb 15, 2018 at 06:38:44AM +0100, Lukas Wunner wrote: > > On Wed, Feb 14, 2018 at 09:58:43AM -0500, Sean Paul wrote: > > > On Wed, Feb 14, 2018 at 03:43:56PM +0100, Michel Dänzer wrote: > > > > On 2018-02-14 03:08 PM, Sean

[Intel-gfx] [PATCH] drm/i915: Remove WARN_ONCE for failing to pm_runtime_if_in_use

As the driver is called to handle circumstances beyond it's control, we cannot assume that the pm_runtime core is happy to see us. For example, if we are called from shrink_slab to free up our pages during suspend, rpm may be disabled and pm_runtime_if_in_use() decides to fail with -EINVAL rather

Re: [Intel-gfx] [PATCH igt] igt/perf_pmu: Retain original GTT offset when resubmitting the spinner

Quoting Tvrtko Ursulin (2018-02-19 13:05:28) > > But I don't think it will fix the issue in GuC mode, at least it didn't > in my testing. For some reason in GuC mode hangs still happen easily. Do > you actually expect i915 may decide to move the VMA in this test, just so? No. With

[Intel-gfx] [PATCH i-g-t v2] perf_pmu: Fix some compile warnings with old compilers / 32-bit builds

From: Tvrtko Ursulin Correct printf format for uint64_t and one "may be uninitialized". v2: Fix one more "may be uninitialized". (Chris Wilson) Signed-off-by: Tvrtko Ursulin Reported-by: Chris Wilson Reviewed-by:

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir (rev2)

== Series Details == Series: series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir (rev2) URL : https://patchwork.freedesktop.org/series/38314/ State : success == Summary == Series 38314v2 series starting with [1/2] drm/i915: Track GT interrupt handling using

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir

Chris Wilson writes: > Keep the master iir and use it to reduce the number of reads and writes > to the GT iir array, i.e. only the bits marked as set by the master iir > are valid inside GT iir array and will be handled during the interrupt. > > Signed-off-by: Chris

Re: [Intel-gfx] [PATCH 0/5] Fix deadlock on runtime suspend in DRM drivers

On Thu, Feb 15, 2018 at 06:38:44AM +0100, Lukas Wunner wrote: > On Wed, Feb 14, 2018 at 09:58:43AM -0500, Sean Paul wrote: > > On Wed, Feb 14, 2018 at 03:43:56PM +0100, Michel Dänzer wrote: > > > On 2018-02-14 03:08 PM, Sean Paul wrote: > > > > On Wed, Feb 14, 2018 at 10:26:35AM +0100, Maarten

[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Handle unexpected holes in color-eviction

== Series Details == Series: drm: Handle unexpected holes in color-eviction URL : https://patchwork.freedesktop.org/series/38506/ State : success == Summary == Series 38506v1 drm: Handle unexpected holes in color-eviction

[Intel-gfx] [PATCH] drm: Handle unexpected holes in color-eviction

During eviction, the driver may free more than one hole in the drm_mm due to the side-effects in evicting the scanned nodes. However, drm_mm_scan_color_evict() expects that the scan result is the first available hole (in the mru freed hole_stack list): kernel BUG at

Re: [Intel-gfx] [Nouveau] [PATCH 0/5] Fix deadlock on runtime suspend in DRM drivers

On Sun, Feb 11, 2018 at 10:38:28AM +0100, Lukas Wunner wrote: > Fix a deadlock on hybrid graphics laptops that's been present since 2013: > > DRM drivers poll connectors in 10 sec intervals. The poll worker is > stopped on ->runtime_suspend with cancel_delayed_work_sync(). However > the poll

[Intel-gfx] [PATCH i-g-t] tests/perf_pmu: Avoid off-lining all CPUs

From: Tvrtko Ursulin Bail out from the cpu-hotplug test if we failed to bring a CPU back online. This still leaves the machine in a quite bad state, but at least it avoids hard hanging it. Signed-off-by: Tvrtko Ursulin --- tests/perf_pmu.c

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] tests/perf_pmu: Avoid off-lining all CPUs

Quoting Tvrtko Ursulin (2018-02-19 13:40:37) > From: Tvrtko Ursulin > > Bail out from the cpu-hotplug test if we failed to bring a CPU back > online. > > This still leaves the machine in a quite bad state, but at least it > avoids hard hanging it. > > Signed-off-by:

Re: [Intel-gfx] [PATCH 0/8] drm: Add COLOR_ENCODING and COLOR_RANGE plane properties

On Mon, Feb 19, 2018 at 04:09:24PM +0100, Daniel Vetter wrote: > On Wed, Feb 14, 2018 at 09:23:19PM +0200, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Here's a refresh of Jyri's COLOR_ENCODING and COLOR_RANGE properties, > > and the i915 implementation I

Re: [Intel-gfx] [PATCH] drm: Handle unexpected holes in color-eviction

On Mon, Feb 19, 2018 at 02:43:59PM +, Chris Wilson wrote: > Quoting Joonas Lahtinen (2018-02-19 14:40:32) > > Quoting Chris Wilson (2018-02-19 13:35:43) > > > +++ b/drivers/gpu/drm/drm_mm.c > > > @@ -836,9 +836,24 @@ struct drm_mm_node *drm_mm_scan_color_evict(struct > > > drm_mm_scan *scan)

[Intel-gfx] [PATCH] drm/i915: Track number of pending freed objects

During igt, we frequently call into the driver to reset both HW and driver state (idling the device, waiting for it to become idle and freeing off old objects) to ensure that we start each test/subtest/pass from known state. This process incurs an RCU barrier or two to ensure that any such pending

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Clear the in-use marker on execbuf failure

== Series Details == Series: drm/i915: Clear the in-use marker on execbuf failure URL : https://patchwork.freedesktop.org/series/38515/ State : success == Summary == Test kms_cursor_crc: Subgroup cursor-64x64-suspend: incomplete -> PASS (shard-hsw) fdo#103540

Re: [Intel-gfx] [Nouveau] [PATCH 0/5] Fix deadlock on runtime suspend in DRM drivers

On Mon, Feb 19, 2018 at 9:54 AM, Daniel Vetter wrote: > On Mon, Feb 19, 2018 at 03:47:42PM +0100, Lukas Wunner wrote: >> On Mon, Feb 19, 2018 at 03:05:53PM +0100, Daniel Vetter wrote: >> > On Mon, Feb 19, 2018 at 12:58:17PM +0100, Lukas Wunner wrote: >> > > On Mon, Feb 19, 2018

Re: [Intel-gfx] [CI] drm/i915/cnl: New power domain for AUX IO.

On Mon, Feb 19, 2018 at 04:47:41PM +0200, Imre Deak wrote: > On Fri, Feb 16, 2018 at 04:27:04PM -0800, Rodrigo Vivi wrote: > > On Fri, Feb 16, 2018 at 03:25:55PM -0800, Dhinakaran Pandiyan wrote: > > > PSR requires AUX IO well to be kept on and the existing AUX domain > > > enables other wells

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir (rev2)

Quoting Patchwork (2018-02-19 11:41:15) > == Series Details == > > Series: series starting with [1/2] drm/i915: Track GT interrupt handling > using the master iir (rev2) > URL : https://patchwork.freedesktop.org/series/38314/ > State : success > > == Summary == > > Test kms_cursor_legacy: >

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Track number of pending freed objects

== Series Details == Series: drm/i915: Track number of pending freed objects URL : https://patchwork.freedesktop.org/series/38537/ State : success == Summary == Series 38537v1 drm/i915: Track number of pending freed objects

[Intel-gfx] [PATCH xf86-video-intel 2/3] Rename current yuv->rgb shader sources to exa_wm_yuv_rgb_bt601

From: Ville Syrjälä Our current yuv->rgb shaders follow the BT.601 conversion formula. Rename the shader sources to indicate that fact. Signed-off-by: Ville Syrjälä --- src/render_program/Makefile.am | 22

[Intel-gfx] [PATCH xf86-video-intel 3/3] sna/video: Add XV_COLORSPACE attribute for the textured Xv adaptor

From: Ville Syrjälä Allow the client to select between BT.601 and BT.709 via the XV_COLORSPACE port attribute with the textured Xv adaptor as well. Since the BT.601 coefficients are currently hardcoded in the yuv->rgb shader, let's just add a mostly duplicated

[Intel-gfx] [PATCH xf86-video-intel 1/3] Remove duplicate exa_wm_yuv_rgb.g5a shader source

From: Ville Syrjälä exa_wm_yuv_rgb.g5a is identical to exa_wm_yuv_rgb.g4a. Just use a symlink intead of duplicating the whole file. Signed-off-by: Ville Syrjälä --- src/render_program/exa_wm_yuv_rgb.g5a | 99

[Intel-gfx] [PATCH xf86-video-intel 0/3] sna/video: XV_COLORSPACE/BT.709 textured Xv support

From: Ville Syrjälä I figured I should expose XV_COLORSPACE/BT.709 on the textured Xv adator as well. So here it is. This depends on the earlier sprite Xv XV_COLORSPACE patch I posted earlier. Ville Syrjälä (3): Remove duplicate exa_wm_yuv_rgb.g5a shader source

Re: [Intel-gfx] [PATCH] drm/i915: Clear the in-use marker on execbuf failure

On 19/02/2018 14:01, Chris Wilson wrote: If we fail to unbind the vma (due to a signal on an active buffer that needs to be moved for the next execbuf), then we need to clear the persistent tracking state we setup for this execbuf. Fixes: c7c6e46f913b ("drm/i915: Convert execbuf to use

Re: [Intel-gfx] [PATCH xf86-video-intel 0/3] sna/video: XV_COLORSPACE/BT.709 textured Xv support

Quoting Ville Syrjala (2018-02-19 18:03:33) > From: Ville Syrjälä > > I figured I should expose XV_COLORSPACE/BT.709 on the textured Xv > adator as well. So here it is. This depends on the earlier sprite > Xv XV_COLORSPACE patch I posted earlier. Looked

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