[Intel-gfx] [CI igt] igt/gem_ctx_isolation: Check isolation of registers between contexts

A new context assumes that all of its registers are in the default state when it is created. What may happen is that a register written by one context may leak into the second, causing mass confusion. v2: Extend back to Sandybridge (etc) v3: Check context preserves registers across

Re: [Intel-gfx] [igt-dev] [PATCH igt] igt/perf_pmu: Disable all cpus

On 21/02/2018 09:17, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-02-21 09:11:15) On 20/02/2018 21:40, Chris Wilson wrote: Rather than iteratively disable and then immediately reenable a CPU, turn off each in turn, forcing the PMU events onto the next CPU without allowing them to retreat

[Intel-gfx] ✓ Fi.CI.BAT: success for igt/gem_ctx_isolation: Check isolation of registers between contexts (rev11)

== Series Details == Series: igt/gem_ctx_isolation: Check isolation of registers between contexts (rev11) URL : https://patchwork.freedesktop.org/series/32531/ State : success == Summary == IGT patchset tested on top of latest successful build 0aeba6e81ad3e00021548093f258c7feb8df415d

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: GuC test run (rev3)

== Series Details == Series: drm/i915: GuC test run (rev3) URL : https://patchwork.freedesktop.org/series/38615/ State : failure == Summary == Series 38615v3 drm/i915: GuC test run https://patchwork.freedesktop.org/api/1.0/series/38615/revisions/3/mbox/ Test core_auth: Subgroup

[Intel-gfx] [PATCH] drm/i915: Check for I915_MODE_FLAG_INHERITED before drm_atomic_helper_check_modeset

Moving the check upwards will mean we we no longer have to add planes and connectors manually, because everything is handled correctly by drm_atomic_helper_check_modeset() as intended. Signed-off-by: Maarten Lankhorst Cc: Lyude Paul Cc:

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Check for I915_MODE_FLAG_INHERITED before drm_atomic_helper_check_modeset

== Series Details == Series: drm/i915: Check for I915_MODE_FLAG_INHERITED before drm_atomic_helper_check_modeset URL : https://patchwork.freedesktop.org/series/38678/ State : warning == Summary == $ dim checkpatch origin/drm-tip a339d719bb21 drm/i915: Check for I915_MODE_FLAG_INHERITED

[Intel-gfx] [CI v3] drm/i915: GuC test run

From: Tvrtko Ursulin With disabled aggressive idling from IGT. To see how shard run fares. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_debugfs.c | 3 --- drivers/gpu/drm/i915/i915_params.h | 2 +-

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/guc: Use correct error code for GuC initialization failure

On 2/21/2018 4:27 AM, Michal Wajdeczko wrote: Since commit 6ca9a2beb54a ("drm/i915: Unwind i915_gem_init() failure") we believed that we correctly handle all errors encountered during GuC initialization, including special one that indicates request to run driver with disabled GPU submission

Re: [Intel-gfx] [igt-dev] [PATCH igt] igt/perf_pmu: Disable all cpus

Quoting Tvrtko Ursulin (2018-02-21 09:24:46) > As I said, it would be easy to support opening our PMU regardless on > which CPU it currently lives on by wrapping the "try the next cpu" logic > in the perf open wrappers. In kernel perf tool for instance does that > already. > > I could also

Re: [Intel-gfx] [PATCH] drm/i915/huc: Mark firmware as failed on auth failure

Quoting Michal Wajdeczko (2018-02-20 22:52:55) > If we fail to authenticate HuC firmware, we should change > its load status to FAIL. While around, print HUC_STATUS > on firmware verification failure. > > Signed-off-by: Michal Wajdeczko > Cc: Rodrigo Vivi

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/doc: Fix documentation for _vblank_restore().

== Series Details == Series: drm/doc: Fix documentation for _vblank_restore(). URL : https://patchwork.freedesktop.org/series/38662/ State : success == Summary == Series 38662v1 drm/doc: Fix documentation for _vblank_restore().

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Add and enable DP AUX CH mutex

On Tuesday, February 20, 2018 6:23:47 PM PST José Roberto de Souza wrote: > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it > self, so lets use the mutex register that is available in gen9+ to > avoid concurrent access by hardware and driver. > > Reference: >

[Intel-gfx] ✓ Fi.CI.BAT: success for igt/gem_ctx_isolation: Check isolation of registers between contexts (rev10)

== Series Details == Series: igt/gem_ctx_isolation: Check isolation of registers between contexts (rev10) URL : https://patchwork.freedesktop.org/series/32531/ State : success == Summary == IGT patchset tested on top of latest successful build 0aeba6e81ad3e00021548093f258c7feb8df415d

Re: [Intel-gfx] [PATCH] drm/i915: fix the issue DP-1 not working in guest

Hi Jani, We cannot disable any port as we might use all the ports for display. And yes, we fake the DP to use EDP panel. Hi Nuhairi, please correct me if I'm wrong. Best regard Mustamin -Original Message- From: Jani Nikula [mailto:jani.nik...@linux.intel.com] Sent: Wednesday,

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/guc: Use correct error code for GuC initialization failure

Quoting Michal Wajdeczko (2018-02-20 22:57:10) > Since commit 6ca9a2beb54a ("drm/i915: Unwind i915_gem_init() failure") > we believed that we correctly handle all errors encountered during > GuC initialization, including special one that indicates request to > run driver with disabled GPU

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable VBT based BL control for DP (v3) (rev5)

== Series Details == Series: drm/i915: Enable VBT based BL control for DP (v3) (rev5) URL : https://patchwork.freedesktop.org/series/38559/ State : success == Summary == Test kms_cursor_crc: Subgroup cursor-256x256-suspend: incomplete -> PASS (shard-hsw)

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Check for I915_MODE_FLAG_INHERITED before drm_atomic_helper_check_modeset

== Series Details == Series: drm/i915: Check for I915_MODE_FLAG_INHERITED before drm_atomic_helper_check_modeset URL : https://patchwork.freedesktop.org/series/38678/ State : failure == Summary == Series 38678v1 drm/i915: Check for I915_MODE_FLAG_INHERITED before

Re: [Intel-gfx] [PATCH] drm/i915: fix the issue DP-1 not working in guest

On Wed, 21 Feb 2018, "Mustaffa, Mustamin B" wrote: > Hi Jani, > > In GVT (virtualization) environment, it only can use DP. Therefore, > we want to enable Port A as DP so that display panel on Port A can be > used by GVT. Why not just disable port A in the guest

[Intel-gfx] [CI igt] igt/gem_ctx_isolation: Check isolation of registers between contexts

A new context assumes that all of its registers are in the default state when it is created. What may happen is that a register written by one context may leak into the second, causing mass confusion. v2: Extend back to Sandybridge (etc) v3: Check context preserves registers across

Re: [Intel-gfx] [igt-dev] [PATCH igt] igt/perf_pmu: Disable all cpus

Quoting Tvrtko Ursulin (2018-02-21 09:11:15) > > On 20/02/2018 21:40, Chris Wilson wrote: > > Rather than iteratively disable and then immediately reenable a CPU, > > turn off each in turn, forcing the PMU events onto the next CPU without > > allowing them to retreat back to CPU0 after the first.

Re: [Intel-gfx] [igt-dev] [PATCH igt] igt/perf_pmu: Disable all cpus

On 20/02/2018 21:40, Chris Wilson wrote: Rather than iteratively disable and then immediately reenable a CPU, turn off each in turn, forcing the PMU events onto the next CPU without allowing them to retreat back to CPU0 after the first. If this fails, Hm, interesting and I think it possibly

Re: [Intel-gfx] [CI v3] drm/i915: GuC test run

Hi guys, I was trying to do a test run with GuC enabled but I am possibly doing something wrong, or something is broken on SKL GVT machine. Could you please check: On 21/02/2018 08:08, Tvrtko Ursulin wrote: > diff --git a/drivers/gpu/drm/i915/i915_params.h >

Re: [Intel-gfx] [igt-dev] [PATCH igt v2] igt/perf_pmu: Use a self-correcting busy pwm

Quoting Tvrtko Ursulin (2018-02-21 10:39:29) > > On 20/02/2018 13:50, Chris Wilson wrote: > > Convert the busy pwm from using a single calibration pass with a fixed > > target into a self-correcting pwm that tries to adjust how long to sleep > > on each pwm in order to converge at the target busy

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v2] tests/perf_pmu: Skip hotplug test on Broxton

Quoting Tvrtko Ursulin (2018-02-21 10:59:32) > From: Tvrtko Ursulin > > Apollolake machine in the shards cannot bring the CPU0 back online so > skip the test on all Broxtons for now. > > v2: Fix inverted check. > > Signed-off-by: Tvrtko Ursulin

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/guc: Use correct error code for GuC initialization failure

On Wed, 21 Feb 2018 09:08:08 +0100, Sagar Arun Kamble wrote: On 2/21/2018 4:27 AM, Michal Wajdeczko wrote: Since commit 6ca9a2beb54a ("drm/i915: Unwind i915_gem_init() failure") we believed that we correctly handle all errors encountered during GuC

Re: [Intel-gfx] [PATCH igt v2] lib: Skip aliased bsd ABI ring if bsd2 is available

On 21/02/2018 12:53, Tvrtko Ursulin wrote: On 21/02/2018 12:17, Chris Wilson wrote: How much do I want this uABI to rot away? Say "Never again!" to implicit aliasing. In the meantime, we do not need to perform duplicate work on bsd2 machines, as especially we do not know which engine bsd

Re: [Intel-gfx] [PATCH] drm/i915: Rename drm_i915_gem_request to i915_request

On Wed, Feb 21, 2018 at 09:56:36AM +, Chris Wilson wrote: > We want to de-emphasize the link between the request (dependency, > execution and fence tracking) from GEM and so rename the struct from > drm_i915_gem_request to i915_request. That is we may implement the GEM > user interface on top

[Intel-gfx] [PATCH 00/16] Adding NV12 support

This patch series is adding NV12 support for Broxton display after rebasing on latest drm-tip. Initial series of the patches can be found here: https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html Previous revision history: The first version of patches were reviewed when floated

[Intel-gfx] [PATCH 01/16] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

From: Mahesh Kumar skl_wm_values struct contains values of pipe/plane DDB only. so rename it for better readability of code. Similarly skl_copy_wm_for_pipe copies DDB values. s/skl_wm_values/skl_ddb_values s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe Changes since V1:

[Intel-gfx] [PATCH 06/16] drm/i915/skl+: pass skl_wm_level struct to wm compute func

From: Mahesh Kumar This patch passes skl_wm_level structure itself to watermark computation function skl_compute_plane_wm function (instead of its internal parameters). It reduces number of arguments required to be passed. v2: Addressed review comments by Shashank

[Intel-gfx] [PATCH 02/16] drm/i915/skl+: refactor WM calculation for NV12

From: Mahesh Kumar Current code calculates DDB for planar formats in such a way that we store DDB of plane-0 in plane 1 & vice-versa. In order to make this clean this patch refactors WM/DDB calculation for NV12 planar formats. v2: Addressed review comments by Maarten

[Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

From: Mahesh Kumar For YUV 420 Planar formats like NV12, buffer allocation is done for Y and UV surfaces separately. For NV12 plane formats, the UV buffer allocation must be programmed in the Plane Buffer Config register and the Y buffer allocation must be programmed in

Re: [Intel-gfx] [igt-dev] [PATCH igt v2] igt/perf_pmu: Use a self-correcting busy pwm

On 20/02/2018 13:50, Chris Wilson wrote: Convert the busy pwm from using a single calibration pass with a fixed target into a self-correcting pwm that tries to adjust how long to sleep on each pwm in order to converge at the target busy %%. Being self-correcting, it should fare better against

Re: [Intel-gfx] [PATCH i-g-t] tests/perf_pmu: Skip hotplug test on Broxton

Quoting Tvrtko Ursulin (2018-02-21 10:57:38) > From: Tvrtko Ursulin > > Apollolake machine in the shards cannot bring the CPU0 back online so > skip the test on all Broxtons for now. > > Signed-off-by: Tvrtko Ursulin > --- > tests/perf_pmu.c

[Intel-gfx] [PATCH i-g-t v2] tests/perf_pmu: Skip hotplug test on Broxton

From: Tvrtko Ursulin Apollolake machine in the shards cannot bring the CPU0 back online so skip the test on all Broxtons for now. v2: Fix inverted check. Signed-off-by: Tvrtko Ursulin --- tests/perf_pmu.c | 1 + 1 file changed, 1

[Intel-gfx] [PATCH igt 1/2] lib: Export kmsg()

Export the kmsg() function for use by tests to write into the kernel message log, useful for tests to inline their progress with kernel error messages. Signed-off-by: Chris Wilson --- lib/igt_core.c | 20 ++-- lib/igt_core.h | 17 + 2

[Intel-gfx] [PATCH igt 2/2] igt/debugfs_tests: Record which file is being opened in kmsg

When tracking down the cause of a particular kernel warning, knowing which file it is associated with can be a big clue. So write the filename into the kernel message log prior to opening it. Signed-off-by: Chris Wilson --- tests/debugfs_test.c | 3 ++- 1 file changed,

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Adding NV12 support (rev12)

== Series Details == Series: Adding NV12 support (rev12) URL : https://patchwork.freedesktop.org/series/28103/ State : warning == Summary == $ dim checkpatch origin/drm-tip 74d9f6f867c3 drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values 98b6c62d8823 drm/i915/skl+: refactor WM

Re: [Intel-gfx] [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane

Reviewed-by: Shashank Sharma Regards Shashank On 2/21/2018 3:50 PM, Vidya Srinivas wrote: From: Chandra Konduru This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed

[Intel-gfx] ✗ Fi.CI.BAT: failure for Adding NV12 support (rev12)

== Series Details == Series: Adding NV12 support (rev12) URL : https://patchwork.freedesktop.org/series/28103/ State : failure == Summary == Series 28103v12 Adding NV12 support https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/12/mbox/ Test gem_mmap_gtt: Subgroup

Re: [Intel-gfx] [PATCH igt] lib: Skip aliased bsd ABI ring if bsd2 is available

On 21/02/2018 11:21, Chris Wilson wrote: How much do I want this uABI to rot away? Say "Never again!" to implicit aliasing. In the meantime, we do not need to perform duplicate work on bsd2 machines, as especially we do not know which engine bsd relates to. Signed-off-by: Chris Wilson

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Check for I915_MODE_FLAG_INHERITED before drm_atomic_helper_check_modeset

== Series Details == Series: drm/i915: Check for I915_MODE_FLAG_INHERITED before drm_atomic_helper_check_modeset URL : https://patchwork.freedesktop.org/series/38678/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2914152024df drm/i915: Check for I915_MODE_FLAG_INHERITED

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Check for I915_MODE_FLAG_INHERITED before drm_atomic_helper_check_modeset

== Series Details == Series: drm/i915: Check for I915_MODE_FLAG_INHERITED before drm_atomic_helper_check_modeset URL : https://patchwork.freedesktop.org/series/38678/ State : warning == Summary == Series 38678v1 drm/i915: Check for I915_MODE_FLAG_INHERITED before

Re: [Intel-gfx] [PATCH igt v2] lib: Skip aliased bsd ABI ring if bsd2 is available

On 21/02/2018 12:17, Chris Wilson wrote: How much do I want this uABI to rot away? Say "Never again!" to implicit aliasing. In the meantime, we do not need to perform duplicate work on bsd2 machines, as especially we do not know which engine bsd relates to. v2: When in doubt, shout!

Re: [Intel-gfx] Thinkpad X1 Carbon 3rd - Reducing the compressed framebuffer size

On Wednesday 21 February 2018 15:28:53 Ville Syrjälä wrote: > On Mon, Feb 19, 2018 at 10:36:50AM +0100, Pali Rohár wrote: > > On Tuesday 13 February 2018 19:45:56 Ville Syrjälä wrote: > > > On Tue, Feb 13, 2018 at 06:43:41PM +0100, Pali Rohár wrote: > > > > On Tuesday 13 February 2018 18:12:21

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Make global seqno known in i915_gem_request_execute tracepoint

On 20/02/2018 11:18, Patchwork wrote: == Series Details == Series: drm/i915: Make global seqno known in i915_gem_request_execute tracepoint URL : https://patchwork.freedesktop.org/series/38578/ State : success == Summary == Series 38578v1 drm/i915: Make global seqno known in

Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

On 21.02.2018 12:20, Vidya Srinivas wrote: From: Chandra Konduru This patch adds NV12 to list of supported formats for primary plane v2: Rebased (Chandra Konduru) v3: Rebased (me) v4: Review comments by Ville addressed Removed the skl_primary_formats_with_nv12 and

[Intel-gfx] [PATCH igt 1/2] Iterate over physical engines

We current have a single for_each_engine() iterator which we use to generate both a set of uABI engines and a set of physical engines. Determining what uABI ring-id corresponds to an actual HW engine is tricky, so pull that out to a library function and introduce for_each_physical_engine() for

[Intel-gfx] [PATCH igt 2/2] igt/gem_spin_batch: Avoid waiting when running concurrently

If we do a global wait while trying to execute spinners in parallel, it ends badly with a GPU hang. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104352 Signed-off-by: Chris Wilson --- tests/gem_spin_batch.c | 16 +--- 1 file changed, 9

Re: [Intel-gfx] [igt-dev] [PATCH igt 1/2] igt/kms_frontbuffer_tracking: Disable FBC testing for -ENODEV

While you are at it could you fix the kms_fbcon_fbt test in the same manner? And you'll have my R-b > -Original Message- > From: igt-dev [mailto:igt-dev-boun...@lists.freedesktop.org] On Behalf Of > Chris Wilson > Sent: Friday, February 16, 2018 11:00 AM > To:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Remove the ring advancement under preemption

== Series Details == Series: drm/i915/execlists: Remove the ring advancement under preemption URL : https://patchwork.freedesktop.org/series/38698/ State : success == Summary == Series 38698v1 drm/i915/execlists: Remove the ring advancement under preemption

[Intel-gfx] [PATCH igt] igt/kms_fbcon_fbt: Handle ENODEV when checking i915_fbc_info for chipset support

If the machine doesn't support FBC, it will return -ENODEV from i915_fbc_info, which we want to interpret as unsupported. Reported-by: Marta Lofstedt Signed-off-by: Chris Wilson Reviewed-by: Marta Lofstedt ---

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Add and enable DP AUX CH mutex

On Wed, Feb 21, 2018 at 01:12:08PM -0800, Souza, Jose wrote: > On Wed, 2018-02-21 at 12:45 -0800, Rodrigo Vivi wrote: > > On Tue, Feb 20, 2018 at 06:23:47PM -0800, José Roberto de Souza > > wrote: > > > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it > > > self, so lets use the

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Scanout fence fixes/cleanups (rev3)

== Series Details == Series: drm/i915: Scanout fence fixes/cleanups (rev3) URL : https://patchwork.freedesktop.org/series/38714/ State : success == Summary == Test drv_suspend: Subgroup fence-restore-untiled: skip -> PASS (shard-snb) Test kms_flip:

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/hsw: add missing disabled EUs registers reads (rev4)

== Series Details == Series: drm/i915/hsw: add missing disabled EUs registers reads (rev4) URL : https://patchwork.freedesktop.org/series/38441/ State : success == Summary == Test kms_flip: Subgroup 2x-dpms-vs-vblank-race: pass -> FAIL (shard-hsw)

[Intel-gfx] ✗ Fi.CI.BAT: failure for ICL GEM enabling (v2) (rev6)

== Series Details == Series: ICL GEM enabling (v2) (rev6) URL : https://patchwork.freedesktop.org/series/38174/ State : failure == Summary == Applying: drm/i915/icl: Add the ICL PCI IDs Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_pci.c M

Re: [Intel-gfx] [PATCH 5/6] drm/i915: Extract intel_plane_{pin, unpin}_fb()

Quoting Ville Syrjala (2018-02-21 16:02:34) > From: Ville Syrjälä > > We've replicated the fb pin/unpin code in a few places. Pull it into > convenint helpers. > > Slight change in locking behaviour as intel_cleanup_plane_fb() now > grab struct_mutex

[Intel-gfx] [PATCH v9] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the Video Enhancement engines (aka VEBOX, aka VECS) could be fused off. Also, each VDBOX and VEBOX has its own power well, which only exist if the related engine exists in the HW. Unfortunately, we have a Catch-22 situation

Re: [Intel-gfx] [PATCH 2/4] drm/i915/icl: Show interrupt registers in debugfs

On 20/02/18 07:37, Mika Kuoppala wrote: From: Tvrtko Ursulin Show GEN11 specific interrupt registers in debugfs v2: Update for POR changes. (Daniele Ceraolo Spurio) v3: get runtime pm ref. unify common parts with gen8 (Daniele) Cc: Ceraolo Spurio, Daniele

Re: [Intel-gfx] [PATCH v3 3/6] drm/i915: Clean up fbc vs. plane checks

Quoting Ville Syrjala (2018-02-21 17:31:01) > From: Ville Syrjälä > > Let's record the information whether a plane can do fbc or not under > struct inte_plane. > > v2: Rebase due to i9xx_plane_id > Handle BDW/HSW correctly > v3: Move inte_fbc_init() back since

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Require fence only for FBC capable planes

Quoting Ville Syrjala (2018-02-21 16:02:33) > From: Ville Syrjälä > > As only a subset of primary planes are FBC capable there's no need > to waste fences on all of them. So let's skip the fence if the plane > isn't even fbc capable. > > In the future we might

Re: [Intel-gfx] [PATCH 6/6] drm/i915: Add a FIXME about FBC vs. fence. 90/270 degree rotation

Quoting Ville Syrjala (2018-02-21 16:02:35) > From: Ville Syrjälä > > Currently the FBC code doesn't handle the 90/270 degree rotated case > correctly. We would need the GTT tracking to monitor the fence on the > normal GTT view (the rotated view doesn't even have

Re: [Intel-gfx] [PATCH] drm/i915: Check for I915_MODE_FLAG_INHERITED before drm_atomic_helper_check_modeset

Nice, this is a no-brainer Reviewed-by: Lyude Paul On Wed, 2018-02-21 at 10:28 +0100, Maarten Lankhorst wrote: > Moving the check upwards will mean we we no longer have to add planes > and connectors manually, because everything is handled correctly by >

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Nuke aux regs from intel_dp

On Tue, 2018-02-20 at 21:00 +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Just store function pointers that give us the correct register offsets > instead of storing the register offsets themselves. Slightly less > efficient perhaps but saves a few bytes

[Intel-gfx] [PATCH igt v3] Iterate over physical engines

We current have a single for_each_engine() iterator which we use to generate both a set of uABI engines and a set of physical engines. Determining what uABI ring-id corresponds to an actual HW engine is tricky, so pull that out to a library function and introduce for_each_physical_engine() for

Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Support engine busy stats

Quoting Tvrtko Ursulin (2018-02-22 06:07:32) > From: Tvrtko Ursulin > > Place context in/out hooks into the GuC backend, when contexts are > assigned to ports, and removed from them, in order to be able to > provide engine busy stats in GuC mode. > > Signed-off-by:

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Add enum aux_ch and clean up the aux init to use it

== Series Details == Series: series starting with [1/2] drm/i915: Add enum aux_ch and clean up the aux init to use it URL : https://patchwork.freedesktop.org/series/38744/ State : warning == Summary == $ dim checkpatch origin/drm-tip b28837aa5cbe drm/i915: Add enum aux_ch and clean up the

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: GuC test run (rev4)

== Series Details == Series: drm/i915: GuC test run (rev4) URL : https://patchwork.freedesktop.org/series/38615/ State : failure == Summary == Test kms_flip: Subgroup modeset-vs-vblank-race: fail -> PASS (shard-hsw) fdo#103060 +1 Test perf: Subgroup

Re: [Intel-gfx] drm-intel-fixes issues on CI

Quoting Rodrigo Vivi (2018-02-22 04:26:29) > Hi guys, > > looking at gem_eio_flight* for gen9 on: > https://intel-gfx-ci.01.org/tree/drm-intel-fixes/shards.html > > run 246 x 247 > pure v4.16-rc2 x our fixes > > would any of 2 patches explain: > > drm/i915: Clear the in-use marker on execbuf

Re: [Intel-gfx] [PULL] git-fixes for 4.16-rc2

Quoting Zhenyu Wang (2018-02-22 03:13:19) > On 2018.02.20 20:15:22 +, Chris Wilson wrote: > > Quoting Zhenyu Wang (2018-02-14 05:28:27) > > > > > > Hi, here's current gvt-fixes pull for 4.16-rc2, as it is close for > > > chinese new year, team would take one week off at least, so like to > >

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add enum aux_ch and clean up the aux init to use it

On Tue, 2018-02-20 at 11:31 -0800, Rodrigo Vivi wrote: > On Tue, Feb 20, 2018 at 07:05:22PM +0200, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Since we no longer have a 1:1 correspondence between ports and AUX > > channels, let's give AUX channels their

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add enum aux_ch and clean up the aux init to use it

On Wed, 2018-02-21 at 23:28 -0800, Dhinakaran Pandiyan wrote: > From: Ville Syrjälä > > Since we no longer have a 1:1 correspondence between ports and AUX > channels, let's give AUX channels their own enum. Makes it easier > to tell the apples from the oranges, and

[Intel-gfx] [PATCH 2/2] drm/i915/cnl: New power domain for AUX IO.

PSR on CNL requires AUX IO wells to be kept on and the existing AUX domain for AUX-A enables DC_OFF well too. This is not required, so add a new AUX_IO_A domain for AUX-A to allow DC states to remain enabled. Other AUX channels re-use the existing AUX domains as they do need power well 2. v2: Add

[Intel-gfx] [PATCH 1/2] drm/i915: Add enum aux_ch and clean up the aux init to use it

From: Ville Syrjälä Since we no longer have a 1:1 correspondence between ports and AUX channels, let's give AUX channels their own enum. Makes it easier to tell the apples from the oranges, and we get rid of the port E AUX power domain FIXME since we now derive the

Re: [Intel-gfx] [V4] drm/i915: Enable VBT based BL control for DP

Hi Ville, I already resubmit the patch https://patchwork.freedesktop.org/patch/205823/ diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 1868f73f730c..b9068bd1943f 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -655,18

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for ICL PLLs, DP/HDMI and misc display

== Series Details == Series: ICL PLLs, DP/HDMI and misc display URL : https://patchwork.freedesktop.org/series/38737/ State : warning == Summary == $ dim checkpatch origin/drm-tip 176365bcdda2 drm/i915/icl: add definitions for the ICL PLL registers -:87: CHECK: Prefer using the BIT macro #87:

[Intel-gfx] drm-intel-fixes issues on CI

Hi guys, looking at gem_eio_flight* for gen9 on: https://intel-gfx-ci.01.org/tree/drm-intel-fixes/shards.html run 246 x 247 pure v4.16-rc2 x our fixes would any of 2 patches explain: drm/i915: Clear the in-use marker on execbuf failure drm/i915: Fix rsvd2 mask when out-fence is returned

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/guc: Support engine busy stats (rev2)

== Series Details == Series: series starting with [1/2] drm/i915/guc: Support engine busy stats (rev2) URL : https://patchwork.freedesktop.org/series/38717/ State : warning == Summary == $ dim checkpatch origin/drm-tip 690dfe054013 drm/i915/guc: Support engine busy stats -:33: WARNING: line

Re: [Intel-gfx] [PATCH libdrm 1/2] intel: align reuse buffer's size on page size instead

On Wed, Feb 21, 2018 at 09:43:55PM +, Chris Wilson wrote: > Quoting James Xiong (2018-02-20 17:48:03) > > From: "Xiong, James" > > > > With gem_reuse enabled, when a buffer size is different than > > the sizes of buckets, it is aligned to the next bucket's size, > >

Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

> -Original Message- > From: Juha-Pekka Heikkila [mailto:juhapekka.heikk...@gmail.com] > Sent: Wednesday, February 21, 2018 7:52 PM > To: Srinivas, Vidya ; intel- > g...@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as

[Intel-gfx] ✗ Fi.CI.BAT: warning for ICL PLLs, DP/HDMI and misc display

== Series Details == Series: ICL PLLs, DP/HDMI and misc display URL : https://patchwork.freedesktop.org/series/38737/ State : warning == Summary == Series 38737v1 ICL PLLs, DP/HDMI and misc display https://patchwork.freedesktop.org/api/1.0/series/38737/revisions/1/mbox/ Test

[Intel-gfx] [PATCH 1/2] drm/i915/guc: Support engine busy stats

From: Tvrtko Ursulin Place context in/out hooks into the GuC backend, when contexts are assigned to ports, and removed from them, in order to be able to provide engine busy stats in GuC mode. Signed-off-by: Tvrtko Ursulin Testcase:

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add enum aux_ch and clean up the aux init to use it

On Tue, 2018-02-20 at 19:05 +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Since we no longer have a 1:1 correspondence between ports and AUX > channels, let's give AUX channels their own enum. Makes it easier > to tell the apples from the oranges, and we

Re: [Intel-gfx] [PATCH v9] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

Looks good to me. Few cosmetic changes suggested below. With those addressed: Reviewed-by: Sagar Arun Kamble On 2/22/2018 5:05 AM, Oscar Mateo wrote: In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the Video Enhancement engines (aka VEBOX, aka

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/guc: Support engine busy stats (rev2)

== Series Details == Series: series starting with [1/2] drm/i915/guc: Support engine busy stats (rev2) URL : https://patchwork.freedesktop.org/series/38717/ State : success == Summary == Series 38717v2 series starting with [1/2] drm/i915/guc: Support engine busy stats

Re: [Intel-gfx] [PULL] git-fixes for 4.16-rc2

On 2018.02.20 20:15:22 +, Chris Wilson wrote: > Quoting Zhenyu Wang (2018-02-14 05:28:27) > > > > Hi, here's current gvt-fixes pull for 4.16-rc2, as it is close for > > chinese new year, team would take one week off at least, so like to > > send this out before vacation. This has one to fix

[Intel-gfx] [PATCH 04/17] drm/i915/icl: compute the combo PHY (DPLL) DP registers

Just use the hardcoded tables provided by our spec. v2: Rebase. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 86 ++- 1 file changed, 85 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 07/17] drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake.

From: Manasi Navare These tables are used on voltage vswing sequence initialization on Icelake. The swing_sel on the spec's table is defined in a 4 bits binary like 1010. However the register bits are split in upper 1 bit swing_sel and lower 3 bits swing sel. In

[Intel-gfx] [PATCH 09/17] drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI

From: Manasi Navare On Icelake platform, MG PHY is used when operating in DP alternate mode or the legacy HDMI or DP modes. DDI Ports C, D, E, F are MG PHY DDI ports on ICL. This patch adds the necessary voltage swing programming related register definitions and

[Intel-gfx] [PATCH 06/17] drm/i915/icl: Add register definitions for Combo PHY vswing sequences.

From: Manasi Navare This patch defines register definitions required for ICL voltage vswing programming for Combo PHY DDI Ports. It uses the same bit definitions and macros as the CNL voltage swing sequences. v7: * Kill _MMIIO_PORT2_LN (Paulo) v6: * Replace some

[Intel-gfx] [PATCH 08/17] drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI

From: Manasi Navare This is an important part of the DDI initalization as well as for changing the voltage during DisplayPort link training. The Voltage swing seqeuence is similar to Cannonlake. However it has different register definitions and hence it makes sense to

[Intel-gfx] [PATCH 02/17] drm/i915/icl: add basic support for the ICL clocks

This commit introduces the definitions for the ICL clocks and adds the basic functions to the shared DPLL framework. It adds code for the Enable and Disable sequences for some PLLs, but it does not have the code to compute the actual PLL values, which are marked as TODO comments and should be

[Intel-gfx] [PATCH 03/17] drm/i915/icl: compute the combo PHY (DPLL) HDMI registers

HDMI mode DPLL programming on ICL is the same as CNL, so just reuse the CNL code. v2: - Properly detect HDMI crtcs. - Rebase after changes to the cnl function (clock * 1000). Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 34

[Intel-gfx] [PATCH 01/17] drm/i915/icl: add definitions for the ICL PLL registers

There's a lot of code for the PLL enabling, so let's first only introduce the register definitions in order to make patch reviewing a little easier. v2: Coding style (Jani). v3: Preparation for upstreaming. Signed-off-by: Paulo Zanoni ---

[Intel-gfx] [PATCH 10/17] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer

From: Manasi Navare This table is used for voltage swing programming sequence during DDI Buffer initialization for MG PHY DDI Buffers on Icelake. v2 (from Paulo): * Fix white space issues. Cc: Rodrigo Vivi Cc: Jani Nikula

[Intel-gfx] [PATCH 05/17] drm/i915/icl: compute the MG PLL registers

This implements the "MG PLL Programming" sequence from our spec. The biggest problem was that the spec assumes real numbers, so we had to adjust some numbers and alculations due to the fact that the Kernel prefers to deal with integers. I recommend grabbing some coffee, a pen and paper before

[Intel-gfx] [PATCH 00/17] ICL PLLs, DP/HDMI and misc display

Hello Here are some more ICL patches, now with the Combo & MG PLLs, some DP/HDMI initialization code and a few misc fixes. Again, the R-B tags already present in some of the patches (including those form me) were given a long time ago, so they need to be re-issued due to the rebasing. Thanks,

[Intel-gfx] [PATCH 14/17] drm/i915/icl: Calculate link clock using the new registers

From: Arkadiusz Hiler Start using the new registers for ICL and on. Cc: Manasi Navare Cc: Rodrigo Vivi Reviewed-by: Paulo Zanoni Signed-off-by: Arkadiusz Hiler

[Intel-gfx] [PATCH 12/17] drm/i915/icl: HPD pin for port F

From: Dhinakaran Pandiyan Extend enum hpd_pin to port F so that we can start using this for ICL. v2: Rebase. Cc: Rodrigo Vivi Cc: Paulo Zanoni Signed-off-by: Dhinakaran Pandiyan

[Intel-gfx] [PATCH 13/17] drm/i915/icl: Added 5k source scaling support for Gen11 platform

From: Nabendu Maiti Gen11 supports upto 5k source scaling v2: Re-factoring of code as per review v3: Corrected max Vertical size and indentation v4: Added max Vertical dst size in same patch Signed-off-by: Nabendu Maiti ---

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