Add Plane Degamma as a blob property and plane degamma size as
a range property.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from
mode_config to drm_plane. Created a helper function to instantiate
these properties and removed from drm_mode_create_standard_properties
Adde
Add plane gamma as blob property and size as a
range property.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from
mode_config to drm_plane. Created a helper function to instantiate
these properties and removed from drm_mode_create_standard_properties
Added property documen
Define helper function to enable Plane color features
to attach plane color properties to plane structure.
v2: Rebase
v3: Modiefied the function to use updated property names.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_plane.c | 42 ++
include/d
Add a blob property for plane CSC usage.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from
mode_config to drm_plane. Created a helper function to instantiate
these properties and removed from drm_mode_create_standard_properties
Added property documentation as suggested by
Enable and initialize plane color features.
v2: Rebase and some cleanup
v3: Updated intel_plane_color_init to call
drm_plane_color_create_prop function, which will
in turn create plane color properties.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers
Implement Plane Gamma feature for BDW and Gen9 platforms.
v2: Used newly added drm_color_lut_ext structure for enhanced
precision for Gamma LUT entries.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_pci.c | 5 +++-
drivers/gpu/drm/i915/i915_reg.h | 24 +++
driv
Load plane color luts as part of atomic plane updates.
This will be done only if the plane color luts are changed.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 4
drivers/gpu/drm/i915/intel_color.c| 8
drivers/gpu/drm/i915/intel_drv.h
== Series Details ==
Series: Add Plane Color Properties (rev3)
URL : https://patchwork.freedesktop.org/series/30875/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm: Add Enhanced Gamma LUT precision structure
+drivers/gpu/drm/drm_plane.c:433:10: warning: symbol
'drm_colo
== Series Details ==
Series: Add Plane Color Properties (rev3)
URL : https://patchwork.freedesktop.org/series/30875/
State : success
== Summary ==
Series 30875v3 Add Plane Color Properties
https://patchwork.freedesktop.org/api/1.0/series/30875/revisions/3/mbox/
Known issues:
Test kms_fr
On 09/03/18 01:53, Tvrtko Ursulin wrote:
On 08/03/2018 18:46, Daniele Ceraolo Spurio wrote:
On 08/03/18 01:31, Tvrtko Ursulin wrote:
On 07/03/2018 19:45, Daniele Ceraolo Spurio wrote:
The mmio bases we're currently storing in the intel_engines array are
only valid for a subset of gens, so
On 08/03/18 17:33, Chris Wilson wrote:
Give the compiler a helping hand in mapping (bank,bit) to our struct
intel_engine_cs by trading object code size for data cache:
add/remove: 2/0 grow/shrink: 0/1 up/down: 48/-135 (-87)
Function old new delta
bank1
On 08/03/18 17:03, Chris Wilson wrote:
Quoting Antonio Argenziano (2018-03-09 00:45:42)
On 08/03/18 09:13, Chris Wilson wrote:
Exercise some new API that allows applications to request that
individual contexts are executed within a desired frequency range.
v2: Split single/continuous set_f
On 09/03/2018 18:47, Daniele Ceraolo Spurio wrote:
On 09/03/18 01:53, Tvrtko Ursulin wrote:
On 08/03/2018 18:46, Daniele Ceraolo Spurio wrote:
On 08/03/18 01:31, Tvrtko Ursulin wrote:
On 07/03/2018 19:45, Daniele Ceraolo Spurio wrote:
The mmio bases we're currently storing in the intel_eng
== Series Details ==
Series: series starting with [v3,1/4] drm: Add drm_any_plane_has_format()
URL : https://patchwork.freedesktop.org/series/39700/
State : failure
== Summary ==
Possible new issues:
Test kms_busy:
Subgroup extended-pageflip-hang-oldfb-render-b:
p
On Fri, Mar 09, 2018 at 06:28:56PM +0530, Mahesh Kumar wrote:
> This patch creates a new macro to get PORT_TX register for any given DW.
> This will remove the need of defining register address for each port & DW.
please squash patches 1 and 2. I had to open both simultaneously to review it
what i
On Fri, Mar 09, 2018 at 06:28:58PM +0530, Mahesh Kumar wrote:
> This patch replaces use of remaining _MMIO_PORT6 macro and removes the
> macro.
Thanks... I hope that we don't need to bring it back for the ICL patches...
>
> Signed-off-by: Mahesh Kumar
Reviewed-by: Rodrigo Vivi
> ---
> drive
Quoting Antonio Argenziano (2018-03-09 19:15:45)
>
>
> On 08/03/18 17:03, Chris Wilson wrote:
> > Quoting Antonio Argenziano (2018-03-09 00:45:42)
> >>
> >>
> >> On 08/03/18 09:13, Chris Wilson wrote:
> >>> Exercise some new API that allows applications to request that
> >>> individual contexts a
Quoting Tvrtko Ursulin (2018-03-09 11:54:13)
> From: Tvrtko Ursulin
>
> We need to use absolute tolerance when asserting on percentages. Relative
> tolerance in this case is unfair and inaccurate since it's strictness
> varies with relative target busyness.
>
> v2:
> * Do not include spin batch
On Fri, Mar 09, 2018 at 11:55:47AM -0800, Rodrigo Vivi wrote:
> On Fri, Mar 09, 2018 at 06:28:56PM +0530, Mahesh Kumar wrote:
> > This patch creates a new macro to get PORT_TX register for any given DW.
> > This will remove the need of defining register address for each port & DW.
>
> please squas
Ville Syrjala writes:
> From: Ville Syrjälä
>
> Only create framebuffers with supported format/modifier combinations by
> checking that at least one plane supports the requested combination.
>
> Using drm_any_plane_has_format() is somewhat suboptimal for vc4 since
> the planes have (mostly) unif
== Series Details ==
Series: drm/i915/uc: Sanitize uC (rev2)
URL : https://patchwork.freedesktop.org/series/39634/
State : failure
== Summary ==
Possible new issues:
Test drv_missed_irq:
pass -> SKIP (shard-apl)
Test drv_selftest:
Subgroup live_guc:
Retraining MST is rather difficult. In order to do it properly while
guaranteeing that we'll never run into a spot where we commit a
physically impossible configuration, we have to do a lot of checks on
atomic commits which affect MST topologies. All of this work is going to
need to be repeated for
When a DP MST link needs retraining, sometimes the hub will detect that
the current link bw config is impossible and will update it's RX caps in
the DPCD to reflect the new maximum link rate. Currently, we make the
assumption that the RX caps in the dpcd will never change like this.
This means if t
Unlike SST, MST can have far more then a single display hooked up on a
single port. What this also means however, is that if the DisplayPort
link to the top-level MST branch device becomes unstable then every
single branch device also has an unstable link. Additionally, MST has a
few more steps tha
For a while we actually haven't had any way of retraining MST links with
fallback link parameters like we do with SST. While uncommon, certain
setups such as my Caldigit TS3 + EVGA MST hub require this since
otherwise, they end up getting stuck in an infinite MST retraining loop.
MST retraining is
While having the modeset_retry_work in intel_connector makes sense with
SST, this paradigm doesn't make a whole ton of sense when it comes to
MST since we have to deal with multiple connectors. In most cases, it's
more useful to just use the intel_dp struct since it indicates whether
or not we're d
Exercise some new API that allows applications to request that
individual contexts are executed within a desired frequency range.
v2: Split single/continuous set_freq subtests
v3: Do an up/down ramp for individual freq request, check nothing
changes after each invalid request
v4: Check the frequen
From: Anusha Srivatsa
Rework the rotate and reflect subtests by checking the
crtc supported properties against the ones that the
test is testing. Remove the hardcoded platform names in
igt_require()
v2: Make use of the property enums to get the supported rotations
Cc: Radhakrishna Sripada
Cc:
== Series Details ==
Series: igt: Add gem_ctx_freq to exercise requesting freq on a ctx (rev2)
URL : https://patchwork.freedesktop.org/series/39571/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
5d71d7782a830843c7231fbd72ab3edae19b48d7 igt/gem_fd_exhaustio
== Series Details ==
Series: drm/i915: misc fixes in headers (RESEND)
URL : https://patchwork.freedesktop.org/series/39589/
State : failure
== Summary ==
Possible new issues:
Test kms_cursor_legacy:
Subgroup short-flip-after-cursor-atomic-transitions:
pass -
Quoting Patchwork (2018-03-09 22:12:20)
> == Series Details ==
>
> Series: drm/i915: misc fixes in headers (RESEND)
> URL : https://patchwork.freedesktop.org/series/39589/
> State : failure
>
> == Summary ==
>
> Possible new issues:
>
> Test kms_cursor_legacy:
> Subgroup short-fl
Radiant P845 does not have LVDS, only VGA.
Signed-off-by: Ondrej Zary
---
drivers/gpu/drm/i915/intel_lvds.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index ef80499113ee..6939e63d8bae 100644
--- a/drivers/gpu
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/guc: Tidy guc_log_control
URL : https://patchwork.freedesktop.org/series/39710/
State : failure
== Summary ==
Possible new issues:
Test drv_missed_irq:
pass -> SKIP (shard-apl)
Test drv_selfte
== Series Details ==
Series: drm/i915: Disable LVDS on Radiant P845
URL : https://patchwork.freedesktop.org/series/39732/
State : success
== Summary ==
Series 39732v1 drm/i915: Disable LVDS on Radiant P845
https://patchwork.freedesktop.org/api/1.0/series/39732/revisions/1/mbox/
Known iss
== Series Details ==
Series: Add NV12 support
URL : https://patchwork.freedesktop.org/series/39670/
State : failure
== Summary ==
Possible new issues:
Test kms_chv_cursor_fail:
Subgroup pipe-a-128x128-left-edge:
fail -> PASS (shard-apl)
Test kms_color:
On Thu, 2018-03-08 at 09:22 +0200, Jani Nikula wrote:
> On Wed, 07 Mar 2018, matthew.s.atw...@intel.com wrote:
> >
> > From: Matt Atwood
> >
> > DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme
> > from 8
> > bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended
> >
On Fri, 2018-03-09 at 14:05 +0200, Jani Nikula wrote:
> On Thu, 08 Mar 2018, matthew.s.atw...@intel.com wrote:
> >
> > From: Matt Atwood
> >
> > Previously it was assumed that eDP panels would advertise the
> > lowest link
> > rate required for their singular mode to function. With the
> > intro
On 09/03/18 08:01, Michal Wajdeczko wrote:
Instead of dancing around uC on reset/suspend/resume scenarios,
explicitly sanitize uC when we sanitize GEM to force uC reload
and start from known beginning.
v2: don't forget about reset path (Daniele)
sanitize uc before gem initiated full reset
== Series Details ==
Series: Add Plane Color Properties (rev3)
URL : https://patchwork.freedesktop.org/series/30875/
State : failure
== Summary ==
Possible new issues:
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
pass -> DM
== Series Details ==
Series: igt: Add gem_ctx_freq to exercise requesting freq on a ctx (rev2)
URL : https://patchwork.freedesktop.org/series/39571/
State : failure
== Summary ==
Possible new issues:
Test kms_draw_crc:
Subgroup draw-method-xrgb2101010-mmap-gtt-xtiled:
== Series Details ==
Series: drm/i915: Disable LVDS on Radiant P845
URL : https://patchwork.freedesktop.org/series/39732/
State : success
== Summary ==
Possible new issues:
Test kms_cursor_crc:
Subgroup cursor-64x64-suspend:
skip -> PASS (shard-snb)
-
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