Re: [Intel-gfx] [PATCH v4] drm/i915/dp: Send DPCD ON for MST before phy_up

On Fri, 2018-04-06 at 14:52 -0400, Lyude Paul wrote: > When doing a modeset where the sink is transitioning from D3 to D0 , it > would sometimes be possible for the initial power_up_phy() to start > timing out. This would only be observed in the last action before the > sink went into D3 mode

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Send DPCD ON for MST before phy_up

== Series Details == Series: drm/i915/dp: Send DPCD ON for MST before phy_up URL : https://patchwork.freedesktop.org/series/41297/ State : success == Summary == Series 41297v1 drm/i915/dp: Send DPCD ON for MST before phy_up

Re: [Intel-gfx] [PATCH 7/7] drm/i915: Engine queues query

Quoting Lionel Landwerlin (2018-04-05 14:05:52) > On 05/04/18 13:39, Tvrtko Ursulin wrote: > > + > > + /** Number of requests with unresolved fences and dependencies. */ > > + __u32 queued; > > + > > + /** Number of ready requests waiting on a slot on GPU. */ > > + __u32 runnable;

[Intel-gfx] [PATCH 1/2] drm/i915/fbc/cnl: Add GLK and CNL+ hardware tracking size

Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_fbc.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 707d49c12638..573b034a02fd 100644 ---

[Intel-gfx] [PATCH 2/2] drm/i915/fbc: Resize CFB in non-full modeset paths

A simple page flip can cause the CFB required size to increase and if it is bigger than the currently allocated CFB it needs to be resized to activate FBC again. Until now this case was not being handled but CI is starting to get some of this errors. So here it will free the old CFB and a try to

Re: [Intel-gfx] [PATCH] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

And I thought we believed in presumption of innocence... On 4/6/2018 2:00 PM, Chris Wilson wrote: If we are resetting just one engine, we know it has stalled. So we can pass the stalled parameter directly to i915_gem_reset_engine(), which alleviates the necessity to poke at the generic

Re: [Intel-gfx] [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock

On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote: > Inside the psr work function, we want to wait for PSR to idle first > and > wish to do so without blocking the normal modeset path, so we do so > without holding the PSR lock. However, we first have to find which > pipe > PSR was enabled on,

Re: [Intel-gfx] [PATCH] drm/i915/psr: enable psr1 on psr2 panels

On Sat, 2018-04-07 at 00:12 +0530, vathsala nagaraju wrote: > From: Vathsala Nagaraju > > Adds force_psr1 mod parameter to enable psr1 on psr2 panels. > useful in cases where psr2 fails and user wants to enable > psr1 feature for power saving until a fix > is

Re: [Intel-gfx] [PATCH 6/7] drm/vmwgfx: Stop using plane->fb in atomic_enable()

> > From: Ville Syrjälä > > Instead of looking at the (soon to be deprecated) plane->fb we'll > examing plane->state->fb instead. We can do this because > vmw_du_crtc_atomic_check() prevents us from enabling a crtc > without the primary plane also being enabled. >

Re: [Intel-gfx] [PATCH 5/7] drm/vmwgfx: Stop updating plane->fb

This makes sense once we got rid of plane->fb Will this go to drm-next? Could you please CC me so that I can do some testing myself. Thanks. Reviewed-by: Deepak Rawat > > From: Ville Syrjälä > > We want to get rid of plane->fb on atomic

Re: [Intel-gfx] [PATCH v4] drm/i915/dp: Send DPCD ON for MST before phy_up

On Fri, 2018-04-06 at 12:48 -0700, Laura Abbott wrote: > On 04/06/2018 11:52 AM, Lyude Paul wrote: > > When doing a modeset where the sink is transitioning from D3 to D0 , it > > would sometimes be possible for the initial power_up_phy() to start > > timing out. This would only be observed in the

Re: [Intel-gfx] [PATCH 6/7] drm/i915/pmu: Add running counter

Quoting Tvrtko Ursulin (2018-04-05 13:39:22) > From: Tvrtko Ursulin > > We add a PMU counter to expose the number of requests currently executing > on the GPU. > > This is useful to analyze the overall load of the system. > > v2: > * Rebase. > * Drop floating point

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/fbc/cnl: Add GLK and CNL+ hardware tracking size

== Series Details == Series: series starting with [1/2] drm/i915/fbc/cnl: Add GLK and CNL+ hardware tracking size URL : https://patchwork.freedesktop.org/series/41303/ State : warning == Summary == $ dim checkpatch origin/drm-tip 51c1ab0d8ad0 drm/i915/fbc/cnl: Add GLK and CNL+ hardware

Re: [Intel-gfx] [PATCH 2/2] drm/i915/fbc: Resize CFB in non-full modeset paths

Quoting José Roberto de Souza (2018-04-06 21:53:49) > A simple page flip can cause the CFB required size to increase and > if it is bigger than the currently allocated CFB it needs to be > resized to activate FBC again. I would have expected the answer to be to plug into atomic. During the

[Intel-gfx] [PATCH] drm/i915/psr: enable psr1 on psr2 panels

From: Vathsala Nagaraju Adds force_psr1 mod parameter to enable psr1 on psr2 panels. useful in cases where psr2 fails and user wants to enable psr1 feature for power saving until a fix is provided for psr2. Cc: Rodrigo Vivi Cc: Dhinakaran

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Keep a count of requests waiting for a slot on GPU

Quoting Tvrtko Ursulin (2018-04-05 13:39:18) > From: Tvrtko Ursulin > > Keep a per-engine number of runnable (waiting for GPU time) requests. > > v2: > * Move queued increment from insert_request to execlist_submit_request to >avoid bumping when re-ordering for

Re: [Intel-gfx] [PATCH 3/7] drm/i915: Keep a count of requests submitted from userspace

Quoting Tvrtko Ursulin (2018-04-05 13:39:19) > From: Tvrtko Ursulin > > Keep a count of requests submitted from userspace and not yet runnable due > unresolved dependencies. > > v2: Rename and move under the container struct. (Chris Wilson) > v3: Rebase. > >

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Split out parking from the idle worker for reuse (rev2)

== Series Details == Series: drm/i915: Split out parking from the idle worker for reuse (rev2) URL : https://patchwork.freedesktop.org/series/41278/ State : success == Summary == Possible new issues: Test gem_mmap_gtt: Subgroup forked-medium-copy-odd: dmesg-warn

[Intel-gfx] ✗ Fi.CI.IGT: failure for Aspect ratio support in DRM layer (rev2)

== Series Details == Series: Aspect ratio support in DRM layer (rev2) URL : https://patchwork.freedesktop.org/series/39960/ State : failure == Summary == Possible new issues: Test gem_mmap_gtt: Subgroup forked-medium-copy-odd: dmesg-warn -> PASS (shard-hsw)

[Intel-gfx] [PATCH v4] drm/i915/dp: Send DPCD ON for MST before phy_up

When doing a modeset where the sink is transitioning from D3 to D0 , it would sometimes be possible for the initial power_up_phy() to start timing out. This would only be observed in the last action before the sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We originally thought

Re: [Intel-gfx] [PATCH 5/7] drm/i915/pmu: Add runnable counter

Quoting Tvrtko Ursulin (2018-04-05 13:39:21) > From: Tvrtko Ursulin > > We add a PMU counter to expose the number of requests with resolved > dependencies waiting for a slot on the GPU to run. > > This is useful to analyze the overall load of the system. > > v2: Don't

Re: [Intel-gfx] [PATCH 4/7] drm/vmwgfx: Stop using plane->fb in vmw_kms_update_implicit_fb()

Reviewed-by: Deepak Rawat > > From: Ville Syrjälä > > The only caller of vmw_kms_update_implicit_fb() is the page_flip > hook which itself gets called with the plane mutex already held. > Hence we can look at plane->state safely. Toss in a

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: enable psr1 on psr2 panels

== Series Details == Series: drm/i915/psr: enable psr1 on psr2 panels URL : https://patchwork.freedesktop.org/series/41294/ State : warning == Summary == $ dim checkpatch origin/drm-tip 768ed9ff8e29 drm/i915/psr: enable psr1 on psr2 panels -:28: CHECK:PARENTHESIS_ALIGNMENT: Alignment should

Re: [Intel-gfx] [PATCH] drm/i915/psr: enable psr1 on psr2 panels

On Fri, Apr 06, 2018 at 12:10:24PM -0700, Dhinakaran Pandiyan wrote: > > > > On Sat, 2018-04-07 at 00:12 +0530, vathsala nagaraju wrote: > > From: Vathsala Nagaraju > > > > Adds force_psr1 mod parameter to enable psr1 on psr2 panels. > > useful in cases where psr2

Re: [Intel-gfx] [PATCH v3] drm/i915: Split out parking from the idle worker for reuse

Quoting Michal Wajdeczko (2018-04-06 17:57:20) > On Fri, 06 Apr 2018 17:51:44 +0200, Chris Wilson > wrote: > > > We will want to park GEM before disengaging the drive^W^W^W unwedging. > > Since we already do the work for idling, expose the guts as a new > > function

Re: [Intel-gfx] [PATCH 5/7] drm/vmwgfx: Stop updating plane->fb

On Fri, Apr 06, 2018 at 07:14:51PM +, Deepak Singh Rawat wrote: > This makes sense once we got rid of plane->fb > > Will this go to drm-next? The plan is to push to drm-misc-next once we get all the ducks in a row. > Could you please CC > me so that I can do some testing myself. Thanks.

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Split out parking from the idle worker for reuse (rev2)

== Series Details == Series: drm/i915: Split out parking from the idle worker for reuse (rev2) URL : https://patchwork.freedesktop.org/series/41278/ State : success == Summary == Possible new issues: Test gem_mmap_gtt: Subgroup forked-medium-copy-odd: dmesg-warn

[Intel-gfx] [PATCH] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

If we are resetting just one engine, we know it has stalled. So we can pass the stalled parameter directly to i915_gem_reset_engine(), which alleviates the necessity to poke at the generic engine->hangcheck.stalled magic variable, leaving that under control of hangcheck as its name implies. Other

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: enable psr1 on psr2 panels

== Series Details == Series: drm/i915/psr: enable psr1 on psr2 panels URL : https://patchwork.freedesktop.org/series/41294/ State : success == Summary == Series 41294v1 drm/i915/psr: enable psr1 on psr2 panels https://patchwork.freedesktop.org/api/1.0/series/41294/revisions/1/mbox/

Re: [Intel-gfx] [PATCH 4/7] drm/i915/pmu: Add queued counter

Quoting Tvrtko Ursulin (2018-04-05 13:39:20) > From: Tvrtko Ursulin > > We add a PMU counter to expose the number of requests which have been > submitted from userspace but are not yet runnable due dependencies and > unsignaled fences. > > This is useful to analyze the

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/fbc/cnl: Add GLK and CNL+ hardware tracking size

== Series Details == Series: series starting with [1/2] drm/i915/fbc/cnl: Add GLK and CNL+ hardware tracking size URL : https://patchwork.freedesktop.org/series/41303/ State : warning == Summary == Series 41303v1 series starting with [1/2] drm/i915/fbc/cnl: Add GLK and CNL+ hardware

Re: [Intel-gfx] [PATCH v4] drm/i915/dp: Send DPCD ON for MST before phy_up

On Fri, Apr 06, 2018 at 12:28:30PM -0700, Dhinakaran Pandiyan wrote: > > > > On Fri, 2018-04-06 at 14:52 -0400, Lyude Paul wrote: > > When doing a modeset where the sink is transitioning from D3 to D0 , it > > would sometimes be possible for the initial power_up_phy() to start > > timing out.

Re: [Intel-gfx] [PATCH v4] drm/i915/dp: Send DPCD ON for MST before phy_up

On 04/06/2018 11:52 AM, Lyude Paul wrote: When doing a modeset where the sink is transitioning from D3 to D0 , it would sometimes be possible for the initial power_up_phy() to start timing out. This would only be observed in the last action before the sink went into D3 mode was

[Intel-gfx] [PATCH 12/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable

Required for TR-TT (Tiled Resource Translation Table) support. Do Linux UMDs make use of this? This change has been security reviewed and the whitelisting approved. Virtualization of other OSes could certainly use it. v2: For whatever reason, this ended up in KBL (??!!) Cc: Mika Kuoppala

[Intel-gfx] [PATCH 14/22] drm/i915/icl: WaEnableStateCacheRedirectToCS

Redirects the state cache to the CS Command buffer section for performance reasons. v2: Rebased Cc: Mika Kuoppala Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_reg.h| 1 + drivers/gpu/drm/i915/intel_engine_cs.c | 4

[Intel-gfx] [PATCH 21/22] drm/i915/icl: WaForwardProgressSoftReset

Avoids a hang during soft reset. Cc: Mika Kuoppala Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_reg.h | 5 + drivers/gpu/drm/i915/intel_pm.c | 8 2 files changed, 13 insertions(+) diff --git

[Intel-gfx] [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing

Revert to an L3 non-hash model, for performance reasons. v2: - Place the WA name above the actual change - Improve the register naming v3: - Rebased - Renamed to Wa_1604223664 Cc: Mika Kuoppala Signed-off-by: Oscar Mateo ---

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

== Series Details == Series: series starting with [1/2] drm/i915: Treat i915_reset_engine() as guilty until proven innocent URL : https://patchwork.freedesktop.org/series/41308/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2957aaafaf83 drm/i915: Treat i915_reset_engine() as

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

== Series Details == Series: series starting with [1/2] drm/i915: Treat i915_reset_engine() as guilty until proven innocent URL : https://patchwork.freedesktop.org/series/41308/ State : success == Summary == Series 41308v1 series starting with [1/2] drm/i915: Treat i915_reset_engine() as

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds

== Series Details == Series: series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds URL : https://patchwork.freedesktop.org/series/41311/ State : success == Summary == Series 41311v1 series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds

Re: [Intel-gfx] [PATCH] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

Quoting Michel Thierry (2018-04-06 22:23:21) > And I thought we believed in presumption of innocence... > > On 4/6/2018 2:00 PM, Chris Wilson wrote: > > If we are resetting just one engine, we know it has stalled. So we can > > pass the stalled parameter directly to i915_gem_reset_engine(), which

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/psr: vbt change for psr

== Series Details == Series: drm/i915/psr: vbt change for psr URL : https://patchwork.freedesktop.org/series/41289/ State : failure == Summary == Possible new issues: Test drm_read: Subgroup invalid-buffer: pass -> FAIL (shard-snb) Test gem_mmap_gtt:

Re: [Intel-gfx] [PATCH] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

Quoting Michel Thierry (2018-04-06 22:44:34) > On 4/6/2018 2:30 PM, Chris Wilson wrote: > > Quoting Michel Thierry (2018-04-06 22:23:21) > >> And I thought we believed in presumption of innocence... > >> > >> On 4/6/2018 2:00 PM, Chris Wilson wrote: > >>> If we are resetting just one engine, we

[Intel-gfx] [PATCH 20/22] drm/i915/icl: Wa_1406838659

Disable CGPSF unit clock gating to prevent an issue. Cc: Mika Kuoppala Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_reg.h | 13 - drivers/gpu/drm/i915/intel_pm.c | 6 ++ 2 files changed, 14 insertions(+), 5

[Intel-gfx] [PATCH 06/22] drm/i915/icl: WaDisableImprovedTdlClkGating

Revert to the legacy implementation. v2: GEN7_ROW_CHICKEN2 is masked v3: - Rebased - Renamed to Wa_2006611047 - A0 and B0 only v4: - Add spaces around '<<' (and fix the surrounding code as well) - Mark the WA as pre-prod Cc: Mika Kuoppala Signed-off-by:

[Intel-gfx] [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

This workarounds an issue with insufficient storage for the CL2 and SF units. v2: Renamed to Wa_1405766107 v3: Wrapped the commit message Cc: Mika Kuoppala Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_reg.h | 4

[Intel-gfx] [PATCH 16/22] drm/i915/icl: Wa_1405779004

Disable MSC clock gating to prevent data corruption. BSpec: 19257 Cc: Mika Kuoppala Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 6 ++ 2 files changed, 7 insertions(+) diff

[Intel-gfx] [PATCH 17/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410

Disable GWL clock gating to prevent two different issues that might cause hangs. Please notice that one of the issues is pre-production only. Cc: Mika Kuoppala Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/intel_pm.c | 6 ++ 1

[Intel-gfx] [PATCH 22/22] drm/i915/icl: WaEnableFloatBlendOptimization

Enables blend optimization for floating point RTs Cc: Mika Kuoppala Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_reg.h| 3 +++ drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++ 2 files changed, 6 insertions(+) diff --git

[Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

Inherit workarounds from previous platforms that are still valid for Icelake. v2: GEN7_ROW_CHICKEN2 is masked v3: - Since it has been fixed already in upstream, removed the TODO comment about WA_SET_BIT for WaInPlaceDecompressionHang. - Squashed with this patch: drm/i915/icl: add

[Intel-gfx] [PATCH 13/22] drm/i915/icl: WaAllowUMDToModifySamplerMode

Required for Bindless samplers. Do Linux UMDs make use of this? This change has been security reviewed and the whitelisting approved. Virtualization of other OSes could certainly use it. Cc: Mika Kuoppala Signed-off-by: Oscar Mateo ---

[Intel-gfx] [PATCH 08/22] drm/i915/icl: WaDisCtxReload

Revert to the legacy implementation to avoid a system hang. v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG v3: Renamed to Wa_220166154 Cc: Mika Kuoppala Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_reg.h | 3 +++

[Intel-gfx] [PATCH 10/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2

Required to dinamically set 'Small PL Lossless Fix Enable' Do Linux UMDs make use of this? This change has been security reviewed and the whitelisting approved. Virtualization of other OSes could certainly use it. v2: For whatever reason, this ended up in KBL (??!!) Cc: Mika Kuoppala

[Intel-gfx] [PATCH 11/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7

Required to dinamically set 'Trilinear Filter Quality Mode' Do Linux UMDs make use of this? This change has been security reviewed and the whitelisting approved. Virtualization of other OSes could certainly use it. v2: For whatever reason, this ended up in KBL (??!!) Cc: Mika Kuoppala

[Intel-gfx] [PATCH 02/22] drm/i915/icl: WaGAPZPriorityScheme

The default GAPZ arbitrer priority value at power-on has been found to be incorrect. v2: Now renamed to Wa_1405543622 Cc: Mika Kuoppala Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_reg.h | 5 +++--

[Intel-gfx] [PATCH 15/22] drm/i915/icl: Enable Sampler DFR

Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler power by dynamically changing its clock frequency in low-throughput conditions. This patches enables it by default on Gen11. v2: Wrong operation to clear the bit (Praveen) Cc: Sagar Arun Kamble Cc:

[Intel-gfx] [PATCH 18/22] drm/i915/icl: Wa_1604302699

Disable I2M Write for performance reasons. Cc: Mika Kuoppala Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_reg.h | 4 +++- drivers/gpu/drm/i915/intel_pm.c | 5 + 2 files changed, 8 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 09/22] drm/i915/icl: WaSendPushConstantsFromMMIO

Allows UMDs to set 'Disable Gather at Set Shader Common Slice'. Do Linux UMDs make use of this? This change has been security reviewed and the whitelisting approved. Virtualization of other OSes could certainly use it... v2: Rebased Cc: Mika Kuoppala

[Intel-gfx] [PATCH 05/22] drm/i915/icl: WaDisableCleanEvicts

Avoids an undefined LLC behavior. BSpec: 9613 v2: Renamed to Wa_1405733216 v3: Spaces around '<<' and fix surrounding code Cc: Mika Kuoppala Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_reg.h | 5 +++--

[Intel-gfx] [PATCH 03/22] drm/i915/icl: WaModifyGamTlbPartitioning

Adjust default GAM TLB partitioning for performance reasons. v2: Only touch the bits that we really need Cc: Mika Kuoppala Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_reg.h | 5 + drivers/gpu/drm/i915/intel_pm.c | 5 +

[Intel-gfx] [PATCH 19/22] drm/i915/icl: Wa_2006665173

Disable blend embellishment in RCC. Cc: Mika Kuoppala Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_reg.h| 18 +++--- drivers/gpu/drm/i915/intel_engine_cs.c | 5 + 2 files changed, 16 insertions(+), 7

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/debugfs: Print sink PSR status

On Mon, 2018-04-02 at 15:38 -0700, Pandiyan, Dhinakaran wrote: > On Mon, 2018-04-02 at 13:51 -0700, José Roberto de Souza wrote: > > IGT tests could be improved with sink status, knowing for sure that > > hardware have activate or exit PSR. > > > > Reviewed-by: Dhinakaran Pandiyan

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dp: Send DPCD ON for MST before phy_up

== Series Details == Series: drm/i915/dp: Send DPCD ON for MST before phy_up URL : https://patchwork.freedesktop.org/series/41297/ State : failure == Summary == Possible new issues: Test gem_pwrite: Subgroup big-gtt-backwards: pass -> SKIP (shard-apl)

Re: [Intel-gfx] [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock

On Fri, Apr 06, 2018 at 11:12:27AM -0700, Souza, Jose wrote: > On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote: > > Inside the psr work function, we want to wait for PSR to idle first > > and > > wish to do so without blocking the normal modeset path, so we do so > > without holding the PSR

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Pass the set of guilty engines to i915_reset()

On 4/6/2018 3:03 PM, Chris Wilson wrote: Currently, we rely on inspecting the hangcheck state from within the i915_reset() routines to determine which engines were guilty of the hang. This is problematic for cases where we want to run i915_handle_error() and call i915_reset() independently of

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Pass the set of guilty engines to i915_reset()

Quoting Michel Thierry (2018-04-06 23:35:43) > I would s/BIT()/ENGINE_MASK()/g, but it's not like we enforce it > (engine_struck has BIT(engine->id)). Done. ENGINE_MASK looks more semantically consistent with calling it "stalled_mask, the set of guilty engines". -Chris

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/psr: enable psr1 on psr2 panels

== Series Details == Series: drm/i915/psr: enable psr1 on psr2 panels URL : https://patchwork.freedesktop.org/series/41294/ State : warning == Summary == Possible new issues: Test gem_mmap_gtt: Subgroup forked-medium-copy-odd: dmesg-warn -> PASS (shard-hsw)

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/debugfs: Print sink PSR status

On Fri, 2018-04-06 at 16:36 -0700, José Roberto de Souza wrote: > On Mon, 2018-04-02 at 15:38 -0700, Pandiyan, Dhinakaran wrote: > > On Mon, 2018-04-02 at 13:51 -0700, José Roberto de Souza wrote: > > > IGT tests could be improved with sink status, knowing for sure > > > that > > > hardware have

Re: [Intel-gfx] [PATCH] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

On 4/6/2018 2:30 PM, Chris Wilson wrote: Quoting Michel Thierry (2018-04-06 22:23:21) And I thought we believed in presumption of innocence... On 4/6/2018 2:00 PM, Chris Wilson wrote: If we are resetting just one engine, we know it has stalled. So we can pass the stalled parameter directly to

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds

== Series Details == Series: series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds URL : https://patchwork.freedesktop.org/series/41311/ State : warning == Summary == $ dim checkpatch origin/drm-tip 080bab08b911 drm/i915/icl: Introduce initial Icelake Workarounds

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Pass the set of guilty engines to i915_reset()

Quoting Michel Thierry (2018-04-06 23:35:43) > On 4/6/2018 3:03 PM, Chris Wilson wrote: > > -static u32 fake_hangcheck(struct i915_request *rq) > > +static u32 fake_hangcheck(struct i915_request *rq, u32 mask) > > { > > - u32 reset_count; > > + struct i915_gpu_error *error =

[Intel-gfx] [PATCH v5] drm/i915/dp: Send DPCD ON for MST before phy_up

When doing a modeset where the sink is transitioning from D3 to D0 , it would sometimes be possible for the initial power_up_phy() to start timing out. This would only be observed in the last action before the sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We originally thought

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Send DPCD ON for MST before phy_up (rev2)

== Series Details == Series: drm/i915/dp: Send DPCD ON for MST before phy_up (rev2) URL : https://patchwork.freedesktop.org/series/41297/ State : success == Summary == Series 41297v2 drm/i915/dp: Send DPCD ON for MST before phy_up

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Treat i915_reset_engine() as guilty until proven innocent

== Series Details == Series: drm/i915: Treat i915_reset_engine() as guilty until proven innocent URL : https://patchwork.freedesktop.org/series/41305/ State : warning == Summary == Possible new issues: Test kms_atomic_transition: Subgroup plane-all-transition-fencing:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Treat i915_reset_engine() as guilty until proven innocent

== Series Details == Series: drm/i915: Treat i915_reset_engine() as guilty until proven innocent URL : https://patchwork.freedesktop.org/series/41305/ State : success == Summary == Series 41305v1 drm/i915: Treat i915_reset_engine() as guilty until proven innocent

[Intel-gfx] [PATCH 1/2] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

If we are resetting just one engine, we know it has stalled. So we can pass the stalled parameter directly to i915_gem_reset_engine(), which alleviates the necessity to poke at the generic engine->hangcheck.stalled magic variable, leaving that under control of hangcheck as its name implies. Other

[Intel-gfx] [PATCH 2/2] drm/i915: Pass the set of guilty engines to i915_reset()

Currently, we rely on inspecting the hangcheck state from within the i915_reset() routines to determine which engines were guilty of the hang. This is problematic for cases where we want to run i915_handle_error() and call i915_reset() independently of hangcheck. Instead of relying on the indirect

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/debugfs: Print sink PSR status

On Sat, 2018-04-07 at 00:49 +, Souza, Jose wrote: > On Fri, 2018-04-06 at 16:36 -0700, José Roberto de Souza wrote: > > On Mon, 2018-04-02 at 15:38 -0700, Pandiyan, Dhinakaran wrote: > > > On Mon, 2018-04-02 at 13:51 -0700, José Roberto de Souza wrote: > > > > IGT tests could be improved

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

== Series Details == Series: series starting with [1/2] drm/i915: Treat i915_reset_engine() as guilty until proven innocent URL : https://patchwork.freedesktop.org/series/41308/ State : failure == Summary == Possible new issues: Test kms_atomic_transition: Subgroup

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: Send DPCD ON for MST before phy_up (rev2)

== Series Details == Series: drm/i915/dp: Send DPCD ON for MST before phy_up (rev2) URL : https://patchwork.freedesktop.org/series/41297/ State : success == Summary == Possible new issues: Test kms_atomic_transition: Subgroup plane-all-transition-fencing: fail

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds

== Series Details == Series: series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds URL : https://patchwork.freedesktop.org/series/41311/ State : failure == Summary == Possible new issues: Test kms_atomic_transition: Subgroup

Re: [Intel-gfx] [PATCH 11/13] drm/omapdrm: Nuke omap_framebuffer_get_next_connector()

On 05/04/18 19:50, Daniel Vetter wrote: > On Thu, Apr 05, 2018 at 06:13:58PM +0300, Ville Syrjala wrote: >> From: Ville Syrjälä >> >> omap_framebuffer_get_next_connector() uses plane->fb which we want to >> deprecate for atomic drivers. As

Re: [Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/7] drm/arc: Stop consulting plane->fb (rev2)

HI, > -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of > Patchwork > Sent: perjantai 6. huhtikuuta 2018 1.51 > To: Ville Syrjala > Cc: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] ✗ Fi.CI.IGT:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Rename wait_for_hang() to wait_until_running()

== Series Details == Series: drm/i915/selftests: Rename wait_for_hang() to wait_until_running() URL : https://patchwork.freedesktop.org/series/41264/ State : success == Summary == Series 41264v1 drm/i915/selftests: Rename wait_for_hang() to wait_until_running()

[Intel-gfx] [PATCH v20 01/18] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

From: Mahesh Kumar skl_wm_values struct contains values of pipe/plane DDB only. so rename it for better readability of code. Similarly skl_copy_wm_for_pipe copies DDB values. s/skl_wm_values/skl_ddb_values s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe Changes since V1:

[Intel-gfx] [PATCH v20 03/18] drm/i915/skl+: add NV12 in skl_format_to_fourcc

From: Mahesh Kumar Add support of recognizing DRM_FORMAT_NV12 from plane_format register value. v2: Added reviewed by tag from Mika Kahola v3: Added reviewed by from Juha-Pekka Heikkila v4: Rebased the series Reviewed-by: Juha-Pekka Heikkila

[Intel-gfx] [PATCH v20 13/18] drm/i915: Update format_is_yuv() to include NV12

From: Chandra Konduru This patch adds NV12 to format_is_yuv() function for sprite planes. v2: -Use intel_ prefix for format_is_yuv (Ville) v3: Rebased (me) v4: Rebased and addressed review comments from Clinton A Taylor. "static function in intel_sprite.c is not

[Intel-gfx] [PATCH v20 17/18] drm/i915: Add NV12 support to intel_framebuffer_init

From: Chandra Konduru This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (Chandra Konduru) v3: rebased (me) v4: Review comments by Ville addressed Added platform check for NV12 in

[Intel-gfx] [PATCH v20 11/18] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

If the fb format is YUV, enable the plane CSC mode bits for the conversion. v2: Addressed review comments from Shashank Sharma Alignment issue fixed in i915_reg.h v3: Adding Reviewed By from Shashank Sharma v4: Rebased the patch. As part of rebasing, re-using the color series defines which are

[Intel-gfx] [PATCH v20 14/18] drm/i915: Upscale scaler max scale for NV12

From: Chandra Konduru This patch updates scaler max limit support for NV12 v2: Rebased (me) v3: Rebased (me) v4: Missed the Tested-by/Reviewed-by in the previous series Adding the same to commit message in this version. v5: Addressed review comments from Ville and

[Intel-gfx] [PATCH v20 18/18] drm/i915: Do not do fb src adjustments for NV12

We skip src trunction/adjustments for NV12 case and handle the sizes directly. Without this, pipe fifo underruns are seen on APL/KBL. Credits-to: Maarten Lankhorst Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_sprite.c

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Park before resetting the submission backend

Quoting Sagar Arun Kamble (2018-04-05 12:54:38) > > > On 4/5/2018 4:32 PM, Chris Wilson wrote: > > As different backends may have different park/unpark callbacks, we > > should only ever switch backends (reset_default_submission on wedge > > recovery, or on enabling the guc) while parked. > > >

[Intel-gfx] [PATCH v20 08/18] drm/i915/skl+: nv12 workaround disable WM level 1-7

From: Mahesh Kumar Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A) Hardware sometimes fails to wake memory from pkg C states fetching the last few lines of planar YUV 420 (NV12) planes. This causes intermittent underflow and corruption. WA: Disable package C

[Intel-gfx] [PATCH v20 02/18] drm/i915/skl+: refactor WM calculation for NV12

From: Mahesh Kumar Current code calculates DDB for planar formats in such a way that we store DDB of plane-0 in plane 1 & vice-versa. In order to make this clean this patch refactors WM/DDB calculation for NV12 planar formats. v2: Addressed review comments by Maarten

[Intel-gfx] [PATCH v20 10/18] drm/i915: Display WA 827

Display WA 827 applies to GEN9 (excluede GLK) and CNL. Switching the plane format from NV12 to RGB and leaving system idle results in display underrun and corruption. WA: Set the bit 15 & bit 19 to 1b in the CLKGATE_DIS_PSL register for the pipe in which NV12 plane is enabled. v2: Addressed

[Intel-gfx] [PATCH v20 05/18] drm/i915/skl+: NV12 related changes for WM

From: Mahesh Kumar NV12 requires WM calculation for UV plane as well. UV plane WM should also fulfill all the WM related restrictions. v2: Addressed review comments from Shashank Sharma. v3: Addressed review comments from Shashank Sharma Changed plane_num to plane_id

[Intel-gfx] [PATCH v20 06/18] drm/i915/skl+: pass skl_wm_level struct to wm compute func

From: Mahesh Kumar This patch passes skl_wm_level structure itself to watermark computation function skl_compute_plane_wm function (instead of its internal parameters). It reduces number of arguments required to be passed. v2: Addressed review comments by Shashank

[Intel-gfx] [PATCH v20 15/18] drm/i915: Add NV12 as supported format for primary plane

From: Chandra Konduru This patch adds NV12 to list of supported formats for primary plane v2: Rebased (Chandra Konduru) v3: Rebased (me) v4: Review comments by Ville addressed Removed the skl_primary_formats_with_nv12 and added NV12 case in existing

[Intel-gfx] [PATCH v20 07/18] drm/i915/skl+: make sure higher latency level has higher wm value

From: Mahesh Kumar DDB allocation optimization algorithm requires/assumes ddb allocation for any memory C-state level DDB value to be as high as level below the current level. Render decompression requires level WM to be as high as wm level-0. This patch fulfils both the

[Intel-gfx] [PATCH v20 16/18] drm/i915: Add NV12 as supported format for sprite plane

From: Chandra Konduru This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed - Removed skl_plane_formats_with_nv12 and added NV12 case in existing skl_plane_formats - Added the 10bpc RGB formats

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