[Intel-gfx] [PATCH v7 2/6] drm/i915: Enable Display WA 0528

From: "Srinivas, Vidya" Possible hang with NV12 plane surface formats. WA: When the plane source pixel format is NV12, the CHICKEN_PIPESL_* register bit 22 must be set to 1 and the render decompression must not be enabled on any of the planes in that pipe. v2: removed

[Intel-gfx] [PATCH v7 1/6] drm/i915: Enable display workaround 827 for all planes, v2.

From: Maarten Lankhorst The workaround was applied only to the primary plane, but is required on all planes. Iterate over all planes in the crtc atomic check to see if the workaround is enabled, and only perform the actual toggling in the pre/post plane update

[Intel-gfx] [PATCH v7 3/6] drm/i915: Add skl_check_nv12_surface for NV12

From: Maarten Lankhorst We skip src trunction/adjustments for NV12 case and handle the sizes directly. Without this, pipe fifo underruns are seen on APL/KBL. v2: For NV12, making the src coordinates multiplier of 4 v3: Moving all the src coords handling code

[Intel-gfx] [PATCH v7 0/6] Enable NV12 support

Enabling NV12 support: - Framebuffer creation - Primary and Sprite plane support Patch series depend on Enable display workaround 827 patch mentioned below submitted by Maarten Removed BXT support for NV12 due to WA826 Changes from prev version: Fixed a checkpatch warning in patch 1 of series

[Intel-gfx] [PATCH v7 6/6] drm/i915: Add NV12 as supported format for sprite plane

From: Chandra Konduru This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed - Removed skl_plane_formats_with_nv12 and added NV12 case in existing skl_plane_formats - Added the 10bpc RGB formats

[Intel-gfx] [PATCH v7 4/6] drm/i915: Add NV12 support to intel_framebuffer_init

From: Chandra Konduru This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (Chandra Konduru) v3: rebased (me) v4: Review comments by Ville addressed Added platform check for NV12 in

[Intel-gfx] [PATCH v7 5/6] drm/i915: Add NV12 as supported format for primary plane

From: Chandra Konduru This patch adds NV12 to list of supported formats for primary plane v2: Rebased (Chandra Konduru) v3: Rebased (me) v4: Review comments by Ville addressed Removed the skl_primary_formats_with_nv12 and added NV12 case in existing

Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: Add NV12 as supported format for sprite plane

Op 07-05-18 om 10:29 schreef Srinivas, Vidya: > >> -Original Message- >> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com] >> Sent: Monday, May 7, 2018 1:55 PM >> To: Srinivas, Vidya ; intel- >> g...@lists.freedesktop.org >> Subject: Re:

Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: Add NV12 as supported format for sprite plane

> -Original Message- > From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com] > Sent: Monday, May 7, 2018 1:55 PM > To: Srinivas, Vidya ; intel- > g...@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: Add NV12 as supported >

Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: Add NV12 as supported format for sprite plane

Op 07-05-18 om 10:20 schreef Srinivas, Vidya: > >> -Original Message- >> From: Srinivas, Vidya >> Sent: Monday, May 7, 2018 1:46 PM >> To: 'Maarten Lankhorst' ; intel- >> g...@lists.freedesktop.org >> Subject: RE: [Intel-gfx] [PATCH v6 6/6] drm/i915: Add

Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: Add NV12 as supported format for sprite plane

> -Original Message- > From: Srinivas, Vidya > Sent: Monday, May 7, 2018 1:46 PM > To: 'Maarten Lankhorst' ; intel- > g...@lists.freedesktop.org > Subject: RE: [Intel-gfx] [PATCH v6 6/6] drm/i915: Add NV12 as supported > format for sprite plane > > >

Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: Add NV12 as supported format for sprite plane

> -Original Message- > From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com] > Sent: Monday, May 7, 2018 1:44 PM > To: Srinivas, Vidya ; intel- > g...@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: Add NV12 as supported >

Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: Add NV12 as supported format for sprite plane

Op 07-05-18 om 10:11 schreef Srinivas, Vidya: > >> -Original Message- >> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com] >> Sent: Monday, May 7, 2018 1:38 PM >> To: Srinivas, Vidya ; intel- >> g...@lists.freedesktop.org >> Subject: Re:

Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: Add NV12 as supported format for sprite plane

> -Original Message- > From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com] > Sent: Monday, May 7, 2018 1:38 PM > To: Srinivas, Vidya ; intel- > g...@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: Add NV12 as supported >

Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: Add NV12 as supported format for sprite plane

Op 06-05-18 om 19:44 schreef Vidya Srinivas: > From: Chandra Konduru > > This patch adds NV12 to list of supported formats for sprite plane. > > v2: Rebased (me) > > v3: Review comments by Ville addressed > - Removed skl_plane_formats_with_nv12 and added > NV12 case in

Re: [Intel-gfx] [PATCH] drm/i915: Don't request a bug report for unsafe module parameters

Quoting Chris Wilson (2018-05-06 21:31:47) > Unsafe module parameters are just that, unsafe. If the user is foolish > enough to try them and the kernel breaks, they get to keep both pieces. > Don't ask them to file a bug report if they broke it themselves. > > References:

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gvt: Add huge gtt shadowing

== Series Details == Series: drm/i915/gvt: Add huge gtt shadowing URL : https://patchwork.freedesktop.org/series/42794/ State : failure == Summary == Applying: drm/i915/gvt: Add new 64K entry type Applying: drm/i915/gvt: Add PTE IPS bit operations Applying: drm/i915/gvt: Handle MMIO

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority (rev2)

== Series Details == Series: series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority (rev2) URL : https://patchwork.freedesktop.org/series/42783/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4150 -> Patchwork_8920 = == Summary - SUCCESS ==

[Intel-gfx] [PATCH v5 12/14] drm/i915/gvt: Handle special sequence on PDE IPS bit

From: Changbin Du If the guest update the 64K gtt entry before changing IPS bit of PDE, we need to re-shadow the whole page table. Because we have ignored all updates to unused entries. Signed-off-by: Changbin Du --- drivers/gpu/drm/i915/gvt/gtt.c

[Intel-gfx] [PATCH v5 13/14] drm/i915/gvt: Fix error handling in ppgtt_populate_spt_by_guest_entry

From: Changbin Du Don't forget to free allocated spt if shadowing failed. Signed-off-by: Changbin Du --- drivers/gpu/drm/i915/gvt/gtt.c | 33 + 1 file changed, 21 insertions(+), 12 deletions(-) diff --git

[Intel-gfx] [PATCH v5 11/14] drm/i915/gvt: Add 2M huge gtt support

From: Changbin Du This add 2M huge gtt support for GVTg. Unlike 64K gtt entry, we can shadow 2M guest entry with real huge gtt. But before that, we have to check memory physical continuous, alignment and if it is supported on the host. We can get all supported page sizes

[Intel-gfx] [PATCH v5 05/14] drm/i915/gvt: Add software PTE flag to mark special 64K splited entry

From: Changbin Du This add a software PTE flag on the Ignored bit of PTE. It will be used to identify splited 64K shadow entries. v2: fix mask definition. Signed-off-by: Changbin Du --- drivers/gpu/drm/i915/gvt/gtt.c | 21 +

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority (rev2)

== Series Details == Series: series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority (rev2) URL : https://patchwork.freedesktop.org/series/42783/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Flush submission tasklet after bumping

[Intel-gfx] [PATCH v5 14/14] drm/i915: Enable platform support for vGPU huge gtt pages

From: Changbin Du Now GVTg supports shadowing both 2M/64K huge gtt pages. So this is to remove the restriction on guest side. To be compatible with old host kernel, we defined a new cap info bit VGT_CAPS_HUGE_GTT. Cc: Zhenyu Wang Signed-off-by:

[Intel-gfx] [PATCH v5 08/14] drm/i915/gvt: Make PTE iterator 64K entry aware

From: Changbin Du 64K PTE is special, only PTE#0, PTE#16, PTE#32, ... PTE#496 are used in the page table. Signed-off-by: Changbin Du --- drivers/gpu/drm/i915/gvt/gtt.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git

[Intel-gfx] [PATCH v5 10/14] drm/i915/kvmgt: Support setting dma map for huge pages

From: Changbin Du To support huge gtt, we need to support huge pages in kvmgt first. This patch adds a 'size' param to the intel_gvt_mpt::dma_map_guest_page API and implements it in kvmgt. v2: rebase. Signed-off-by: Changbin Du ---

[Intel-gfx] [PATCH v5 07/14] drm/i915/gvt: Split ppgtt_alloc_spt into two parts

From: Changbin Du We need a interface to allocate a pure shadow page which doesn't have a guest page associated with. Such shadow page is used to shadow 2M huge gtt entry. Signed-off-by: Changbin Du --- drivers/gpu/drm/i915/gvt/gtt.c | 62

[Intel-gfx] [PATCH v5 06/14] drm/i915/gvt: Add GTT clear_pse operation

From: Changbin Du Add clear_pse operation in case we need to split huge gtt into small pages. v2: correct description. Signed-off-by: Changbin Du --- drivers/gpu/drm/i915/gvt/gtt.c | 19 +++ drivers/gpu/drm/i915/gvt/gtt.h | 1 +

[Intel-gfx] [PATCH v5 01/14] drm/i915/gvt: Add new 64K entry type

From: Changbin Du Add a new entry type GTT_TYPE_PPGTT_PTE_64K_ENTRY. 64K entry is very different from 2M/1G entry. 64K entry is controlled by IPS bit in upper PDE. To leverage the current logic, I take IPS bit as 'PSE' for PTE level. Which means, 64K entries can also

[Intel-gfx] [PATCH v5 04/14] drm/i915/gvt: Detect 64K gtt entry by IPS bit of PDE

From: Changbin Du This change help us detect the real entry type per PSE and IPS setting. For 64K entry, we also need to check reg GEN8_GAMW_ECO_DEV_RW_IA. Signed-off-by: Changbin Du --- drivers/gpu/drm/i915/gvt/gtt.c | 68

[Intel-gfx] [PATCH v5 03/14] drm/i915/gvt: Handle MMIO GEN8_GAMW_ECO_DEV_RW_IA for 64K GTT

From: Changbin Du The register RENDER_HWS_PGA_GEN7 is renamed to GEN8_GAMW_ECO_DEV_RW_IA from GEN8 which can control IPS enabling. v2: IPS of all engines must be enabled together for gen9. Signed-off-by: Changbin Du ---

[Intel-gfx] [PATCH v5 02/14] drm/i915/gvt: Add PTE IPS bit operations

From: Changbin Du Add three IPS operation functions to test/set/clear IPS in PDE. Signed-off-by: Changbin Du --- drivers/gpu/drm/i915/gvt/gtt.c | 18 ++ drivers/gpu/drm/i915/gvt/gtt.h | 2 ++ 2 files changed, 20 insertions(+)

[Intel-gfx] [PATCH v5 00/14] drm/i915/gvt: Add huge gtt shadowing

From: Changbin Du Add huge gtt shadowing for GVT. This will alow huge gtt feature turned on for vGPU. v5: o IPS of all engines must be enabled together for gen9. o Coding style improvment. v4: o Make first patch bisectable. v3: o rebase. v2: o fix comments from

[Intel-gfx] [PATCH v5 09/14] drm/i915/gvt: Add 64K huge gtt support

From: Changbin Du Finally, this add the first huge gtt support for GVTg - 64K pages. Since 64K page and 4K page cannot be mixed on the same page table, so we always split a 64K entry into small 4K page. And when unshadow guest 64K entry, we need ensure all the shadowed

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority (rev2)

== Series Details == Series: series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority (rev2) URL : https://patchwork.freedesktop.org/series/42783/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5b9b411b4a48 drm/i915: Flush submission tasklet after

[Intel-gfx] [PATCH v2] drm/i915/execlists: Direct submit onto idle engines

Bypass using the tasklet to submit the first request to HW, as the tasklet may be deferred unto ksoftirqd and at a minimum will add in excess of 10us (and maybe tens of milliseconds) to our execution latency. This latency reduction is most notable when execution flows between engines.

Re: [Intel-gfx] [PATCH] drm/i915: Don't request a bug report for unsafe module parameters

On Sun, 06 May 2018, Chris Wilson wrote: > Unsafe module parameters are just that, unsafe. If the user is foolish > enough to try them and the kernel breaks, they get to keep both pieces. > Don't ask them to file a bug report if they broke it themselves. > > References:

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