Defines the HDCP specific ME FW interfaces such as Request CMDs,
payload structure for CMDs and their response status codes.
This patch defines payload size(Excluding the Header)for each WIRED
HDCP2.2 CMDs.
v2:
Rebased.
v3:
Extra comments are removed.
v4:
%s/\/\*\*/\/\*
v5:
Extra lines
Provides Pairing info to ME to store.
Pairing is a process to fast track the subsequent authentication
with the same HDCP sink.
On Success, received HDCP pairing info is stored in non-volatile
memory of ME.
v2:
Rebased.
v3:
cldev is passed as first parameter [Tomas]
Redundant comments and
Request to ME to verify the LPrime received from HDCP sink.
On Success, ME FW will verify the received Lprime by calculating and
comparing with L.
This represents the completion of Locality Check.
v2:
Rebased.
v3:
cldev is passed as first parameter [Tomas]
Redundant comments and cast are
Request the ME to terminate the HDCP2.2 session for a port.
On Success, ME FW will mark the intel port as Deauthenticated and
terminate the wired HDCP2.2 Tx session started due to the cmd
WIRED_INITIATE_HDCP2_SESSION.
v2:
Rebased.
v3:
cldev is passed as first parameter [Tomas]
Redundant
Request to ME to verify the M_Prime received from the HDCP sink.
ME FW will calculate the M and compare with M_prime received
as part of RepeaterAuth_Stream_Ready, which is HDCP2.2 protocol msg.
On successful completion of this stage, downstream propagation of
the stream management info is
Request to ME to prepare the encrypted session key.
On Success, ME provides Encrypted session key. Function populates
the HDCP2.2 authentication msg SKE_Send_Eks.
v2:
Rebased.
v3:
cldev is passed as first parameter [Tomas]
Redundant comments and cast are removed [Tomas]
v4:
%zd for
Request to ME to configure a port as authenticated.
On Success, ME FW will mark the port as authenticated and provides
HDCP cipher with the encryption keys.
Enabling the Authentication can be requested once all stages of
HDCP2.2 authentication is completed by interacting with ME FW.
Only after
Request ME to verify the downstream topology information received.
ME FW will validate the Repeaters receiver id list and
downstream topology.
On Success ME FW will provide the Least Significant
128bits of VPrime, which forms the repeater ack.
v2:
Rebased.
v3:
cldev is passed as first
== Series Details ==
Series: drm/i915: Implement HDCP2.2 (rev8)
URL : https://patchwork.freedesktop.org/series/38254/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1656b0942fab drm: hdcp2.2 authentication msg definitions
ffcfc502c0d2 drm: HDMI and DP specific HDCP2.2 defines
Limit the link training clock recovery loop to 10 failed attempts at
LANEx_CR_DONE per DP 1.4 spec section 3.5.1.2.2. Some USB-C MST hubs
cause us to get stuck in this loop indefinitely requesting
voltage swing: 0, pre-emphasis level: 2
voltage swing: 1, pre-emphasis level: 2
voltage
== Series Details ==
Series: drm/i915/dp: Give up link training clock recovery after 10 failed
attempts (rev2)
URL : https://patchwork.freedesktop.org/series/46506/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4488 -> Patchwork_9655 =
== Summary - SUCCESS ==
No
If all the components associated to a component master is not added
to the component framework due to the HW capability or Kconfig
selection, component_match will be NULL at
component_master_add_with_match().
To avoid this, component_match_alloc() is added to the framework,
to allcoate the struct
Initialize HDCP2.2 support. This includes the mei interface
initialization along with required component registration.
v2:
mei interface handle is protected with mutex. [Chris Wilson]
v3:
Notifiers are used for the mei interface state.
v4:
Poll for mei client device state
Error msg for
This patch defines the hdcp2.2 protocol messages for authentication.
v2:
bit_fields are removed. Instead bitmasking used. [Tomas and Jani]
prefix HDCP_2_2_ is added to the macros. [Tomas]
v3:
No Changes.
v4:
Style and spellings are fixed [Uma]
v5:
Fix for macros.
v6:
comment for Type
The sequence for HDCP2.2 authentication and encryption is implemented
in I915. Encoder specific implementations are moved into hdcp_shim.
Intel HWs supports HDCP2.2 through ME FW. Hence this series
introduces a client driver for mei bus, so that for HDCP2.2
authentication, HDCP2.2 stack in I915
From: Tomas Winkler
Whitelist HDCP client for in kernel drm use
v2:
Rebased.
v3:
No changes.
v4:
No changes.
v5:
No changes.
v6:
No changes
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/bus-fixup.c | 16
1 file changed, 16 insertions(+)
diff --git
Data structures and Enum for the I915-MEI_HDCP interface are defined
at
v2:
Rebased.
v3:
mei_cl_device is removed from mei_hdcp_data [Tomas]
v4:
Comment style and typo fixed [Uma]
v5:
Rebased.
v6:
No changes.
Signed-off-by: Ramalingam C
---
include/linux/mei_hdcp.h | 100
This patch adds HDCP register definitions for HDMI and DP HDCP
adaptations.
HDMI specific HDCP2.2 register definitions are added into drm_hdcp.h,
where as HDCP2.2 register offsets in DPCD offsets are defined at
drm_dp_helper.h.
v2:
bit_field definitions are replaced by macros. [Tomas and Jani]
Considering significant number of HDCP specific variables, it will
be clean to have separate struct for HDCP.
New structure called intel_hdcp is added within intel_connector.
v2:
struct hdcp statically allocated. [Sean Paul]
enable and disable function parameters are retained.[Sean Paul]
v3:
A generic component master is added to hold the i915 registration
until all required kernel modules are up and active.
This is achieved through following steps:
- moving the i915 driver registration to the component master's
bind call
- all required kernel modules
Intel HDCP2.2 registers are defined with addr offsets and bit details.
v2:
Replaced the arith calc with _PICK [Sean Paul]
v3:
No changes.
v4:
%s/HDCP2_CTR_DDI/HDCP2_CTL_DDI [Uma]
v5:
Added parentheses for the parameters of macro.
v6:
No changes
Signed-off-by: Ramalingam C
Reviewed-by:
== Series Details ==
Series: drm/i915: Implement HDCP2.2 (rev8)
URL : https://patchwork.freedesktop.org/series/38254/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4488 -> Patchwork_9656 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_9656
Considering that HDCP2.2 is more secure than HDCP1.4, When a setup
supports HDCP2.2 and HDCP1.4, HDCP2.2 will be enabled.
When HDCP2.2 enabling fails and HDCP1.4 is supported, HDCP1.4 is
enabled.
This change implements a sequence of enabling and disabling of
HDCP2.2 authentication and HDCP2.2
For reusability purpose, this patch implements the hdcp1.4 bksv's
read and validation as a functions.
For detecting the HDMI panel's HDCP capability this fucntions will be
used.
v2:
Rebased.
v3:
No Changes.
v4:
inline tag is removed with modified error msg.
v5:
No Changes.
v6:
No
Implements the HDCP2.2 repeaters authentication steps such as verifying
the downstream topology and sending stream management information.
v2:
Rebased.
v3:
No Changes.
v4:
-EINVAL is returned for topology error and rollover scenario.
Endianness conversion func from drm_hdcp.h is used
Implements HDCP2.2 authentication for hdcp2.2 receivers, with
following steps:
Authentication and Key exchange (AKE).
Locality Check (LC).
Session Key Exchange(SKE).
DP Errata for stream type configuration for receivers.
At AKE, the HDCP Receiver’s public key
Implements the link integrity check once in 500mSec.
Once encryption is enabled, an ongoing Link Integrity Check is
performed by the HDCP Receiver to check that cipher synchronization
is maintained between the HDCP Transmitter and the HDCP Receiver.
On the detection of synchronization lost, the
HDCP check link is invoked only on CP_IRQ detection, instead of all
short pulses.
v3:
No Changes.
v4:
Added sean in cc and collected the reviewed-by received.
v5:
No Change.
v6:
No Change.
Signed-off-by: Ramalingam C
cc: Sean Paul
Reviewed-by: Uma Shankar
Reviewed-by: Sean Paul
---
When repeater notifies a downstream topology change, this patch
reauthenticate the repeater alone without disabling the hdcp
encryption. If that fails then complete reauthentication is executed.
v2:
Rebased.
v3:
No Changes.
v4:
Typo in commit msg is fixed [Uma]
v5:
Rebased as part of
On DP HDCP1.4 and 2.2, when CP_IRQ is received, start the link
integrity check for the HDCP version that is enabled.
v2:
Rebased. Function name is changed.
v3:
No Changes.
v4:
No Changes.
v5:
No Changes.
v6:
%s/_in_force/_in_use [Sean Paul]
Signed-off-by: Ramalingam C
cc: Sean Paul
Mei hdcp driver is designed as component slave for the I915 component
master.
v2:
Rebased.
v3:
Notifier chain is adopted for cldev state update [Tomas]
v4:
Made static dummy functions as inline in mei_hdcp.h
API for polling client device status
IS_ENABLED used in header, for config
Implements the DP adaptation specific HDCP2.2 functions.
These functions perform the DPCD read and write for communicating the
HDCP2.2 auth message back and forth.
Note: Chris Wilson suggested alternate method for waiting for CP_IRQ,
than completions concept. WIP to understand and implement
Implements the HDMI adaptation specific HDCP2.2 operations.
Basically these are DDC read and write for authenticating through
HDCP2.2 messages.
v2:
Rebased.
v3:
No Changes.
v4:
No more special handling of Gmbus burst read for AKE_SEND_CERT.
Style fixed with few naming. [Uma]
Request ME FW to start the HDCP2.2 session for an intel port.
Prepares payloads for command WIRED_INITIATE_HDCP2_SESSION and sends
to ME FW.
On Success, ME FW will start a HDCP2.2 session for the port and
provides the content for HDCP2.2 AKE_Init message.
v2:
Rebased.
v3:
cldev is add as a
ME FW is contributes a vital role in HDCP2.2 authentication.
HDCP2.2 driver needs to communicate to ME FW for each step of the
HDCP2.2 authentication.
ME FW prepare and HDCP2.2 authentication parameters and encrypt them
as per spec. With such parameter Driver prepares HDCP2.2 auth messages
and
Requests for verification for receiver certification and also the
preparation for next AKE auth message with km.
On Success ME FW validate the HDCP2.2 receivers certificate and do the
revocation check on the receiver ID. AKE_Stored_Km will be prepared if
the receiver is already paired, else
Requests for the verification of AKE_Send_H_prime.
ME will calculate the H and comparing it with received H_Prime.
The result will be returned as status.
Here AKE_Send_H_prime is a HDCP2.2 Authentication msg.
v2:
Rebased.
v3:
cldev is passed as first parameter [Tomas]
Redundant comments
On HDMI connector init, intel_hdcp_init is passed with a flag for hdcp2.2
support based on the platform capability.
v2:
Rebased.
v3:
No Changes.
v4:
Collected the reviewed-by received.
v5:
No change.
v6:
No change.
Signed-off-by: Ramalingam C
Reviewed-by: Uma Shankar
---
On DP connector init, intel_hdcp_init is passed with a flag for hdcp2.2
support based on the platform capability.
v2:
Rebased.
v3:
No Changes.
v4:
Collected the reviewed-by received.
v5:
No change.
v6:
No change.
Signed-off-by: Ramalingam C
Reviewed-by: Uma Shankar
---
Requests ME to start the second stage of HDCP2.2 authentication,
called Locality Check.
On Success, ME FW will provide LC_Init message to send to hdcp sink.
v2:
Rebased.
v3:
cldev is passed as first parameter [Tomas]
Redundant comments and cast are removed [Tomas]
v4:
%zd used for
== Series Details ==
Series: drm/i915: Implement HDCP2.2 (rev8)
URL : https://patchwork.freedesktop.org/series/38254/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm: hdcp2.2 authentication msg definitions
Okay!
Commit: drm: HDMI and DP specific HDCP2.2 defines
Okay!
== Series Details ==
Series: series starting with [v3] drm/i915/icl: Add remaining registers and
bitfields for MG PHY DDI (rev3)
URL : https://patchwork.freedesktop.org/series/45623/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4488 -> Patchwork_9652 =
== Summary -
With the new CSB processing code, we are not vulnerable to delayed
delivery of a pre-reset interrupt as we use the CSB status pointers in
the HWSP to decide if we need to parse any CSB events and no longer need
to wait for the first post-reset interrupt to be assured that the CSB
mmio registers
Knowing the boundary of each subtest can be instrumental in digesting
the voluminous trace output and finding the critical piece of
information.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_selftest.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
Inside intel_engine_is_idle(), we flush the tasklet to ensure that is
being run in a timely fashion (ksoftirqd has taught us to expect the
worst). However, if we are in the middle of reset, the HW may not yet be
ready to execute the submission tasklet and so we must respect the
disable flag.
Check that reset_in_progress() is true when we process the reset.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 35d37af0cb9a..dd9f9219d7f1 100644
---
With the new CSB processing code, we are not vulnerable to delayed
delivery of a pre-reset interrupt as we use the CSB status pointers in
the HWSP to decide if we need to parse any CSB events and no longer need
to wait for the first post-reset interrupt to be assured that the CSB
mmio registers
Knowing the boundary of each subtest can be instrumental in digesting
the voluminous trace output and finding the critical piece of
information.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_selftest.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
Inside intel_engine_is_idle(), we flush the tasklet to ensure that is
being run in a timely fashion (ksoftirqd has taught us to expect the
worst). However, if we are in the middle of reset, the HW may not yet be
ready to execute the submission tasklet and so we must respect the
disable flag.
On 7/13/2018 1:41 PM, Chris Wilson wrote:
Quoting Chris Wilson (2018-07-13 21:35:28)
Inside intel_engine_is_idle(), we flush the tasklet to ensure that is
being run in a timely fashion (ksoftirqd has taught us to expect the
worst). However, if we are in the middle of reset, the HW may not yet
On Fri, Jul 13, 2018 at 10:32:15AM -0700, Nathan Ciobanu wrote:
> Limit the link training clock recovery loop to 10 failed attempts at
> LANEx_CR_DONE per DP 1.4 spec.
Where exactly in the spec?
> Some USB-C MST hubs cause us to get
> stuck in this loop on hot-plugging indefinitely as
>
On Fri, 2018-07-13 at 14:22 -0700, Rodrigo Vivi wrote:
> On Fri, Jul 13, 2018 at 10:32:15AM -0700, Nathan Ciobanu wrote:
> >
> > Limit the link training clock recovery loop to 10 failed attempts
> > at
> > LANEx_CR_DONE per DP 1.4 spec.
> Where exactly in the spec?
>
> >
> > Some USB-C MST hubs
On Fri, Jul 13, 2018 at 02:22:03PM -0700, Rodrigo Vivi wrote:
> On Fri, Jul 13, 2018 at 10:32:15AM -0700, Nathan Ciobanu wrote:
> > Limit the link training clock recovery loop to 10 failed attempts at
> > LANEx_CR_DONE per DP 1.4 spec.
>
> Where exactly in the spec?
I'll add the section number to
Em Sex, 2018-07-13 às 14:08 -0700, Rodrigo Vivi escreveu:
> On Wed, Jul 11, 2018 at 02:59:02PM -0700, Paulo Zanoni wrote:
> > Use the hardcoded tables provided by our spec.
> >
> > v2:
> > - SSC stays disabled.
> > - Use intel_port_is_tc().
> >
> > Cc: Anusha Srivatsa
> > Signed-off-by:
On Fri, Jul 13, 2018 at 03:18:32PM -0700, Manasi Navare wrote:
> On Fri, Jul 13, 2018 at 03:23:41PM -0700, Dhinakaran Pandiyan wrote:
> > On Fri, 2018-07-13 at 14:22 -0700, Rodrigo Vivi wrote:
> > > On Fri, Jul 13, 2018 at 10:32:15AM -0700, Nathan Ciobanu wrote:
> > > >
> > > > Limit the link
On 7/13/2018 2:56 AM, Tvrtko Ursulin wrote:
From: John Harrison
Improve the timeline legend to show actual context colours.
v2: (Tvrtko Ursulin)
* Commit msg.
* Tweak layout for more compactness and more readability.
v3:
* Limit number of shown contexts in the legend. (John Harrison)
On Wed, Jul 11, 2018 at 12:09:55AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/glk: Add Quirk for GLK NUC HDMI port issues. (rev5)
> URL : https://patchwork.freedesktop.org/series/6/
> State : failure
>
> == Summary ==
>
> = CI Bug Log - changes from
== Series Details ==
Series: HAX drm/amdgpu: Disallow suspending
URL : https://patchwork.freedesktop.org/series/46467/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ab2911e9ede6 HAX drm/amdgpu: Disallow suspending
-:35: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)
== Series Details ==
Series: HAX drm/amdgpu: Disallow suspending
URL : https://patchwork.freedesktop.org/series/46467/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4485 -> Patchwork_9645 =
== Summary - SUCCESS ==
No regressions found.
External URL:
n Fri, Jul 13, 2018 at 10:48:02AM +0200, Daniel Vetter wrote:
> On Thu, Jul 12, 2018 at 08:23:05PM +0300, Ville Syrjälä wrote:
> > On Thu, Jul 12, 2018 at 07:03:58PM +0200, Daniel Vetter wrote:
> > > On Thu, Jul 12, 2018 at 6:24 PM, Lucas De Marchi
> > > wrote:
> > > > On Thu, Jul 12, 2018 at
From: Tvrtko Ursulin
It is possible to customize the axis display so change it to display
timestamps in seconds on the major axis (with six decimal spaces) and
millisecond offsets on the minor axis.
v2:
* Give up on broken relative timestamps.
Signed-off-by: Tvrtko Ursulin
Suggested-by:
From: Tvrtko Ursulin
vis library has a limited precision compared to our trace data which
prevents zooming into the timeline and seeing the fine detail.
Scale the HTML view by a thousand to work around it.
v2: Rebase for time axis changes.
v3: Another tweak for time axis changes.
From: John Harrison
Improve the timeline legend to show actual context colours.
v2: (Tvrtko Ursulin)
* Commit msg.
* Tweak layout for more compactness and more readability.
v3:
* Limit number of shown contexts in the legend. (John Harrison)
Signed-off-by: John Harrison
Signed-off-by:
From: Antonio Argenziano
An hanging batch is nothing more than a spinning batch that never gets
stopped, so re-use the routines implemented in dummyload.c.
v2:
- Let caller decide spin loop size
- Now builds with meson.
v3:
- Only use loose loops for hangs (Chris)
v4:
Currently we indirectly try to evict the test buffers by mmaping enough
bo that should fill the aperture. However, this assumes that the kernel
is trying to fill the aperture and does not use random replacement
(which it does) or use small partials to avoid mmaping the whole object
(which it
From: Tvrtko Ursulin
vis library has a limited precision compared to our trace data which
prevents zooming into the timeline and seeing the fine detail.
Scale the HTML view by a thousand to work around it.
v2: Rebase for time axis changes.
v3: Another tweak for time axis changes.
From: Antonio Argenziano
An hanging batch is nothing more than a spinning batch that never gets
stopped, so re-use the routines implemented in dummyload.c.
v2: Let caller decide spin loop size
v3: Only use loose loops for hangs (Chris)
v4: No requires
v5: Free the spinner
v6: Chamelium exists.
On 12/07/2018 16:10, Tomasz Lis wrote:
The patch adds a parameter to control the data port coherency functionality
on a per-context level. When the IOCTL is called, a command to switch data
port coherency state is added to the ordered list. All prior requests are
executed on old coherency
Quoting Daniel Vetter (2018-07-12 13:58:11)
> On Thu, Jul 12, 2018 at 09:41:07AM +0100, Chris Wilson wrote:
> > Quoting Chris Wilson (2018-07-12 09:36:33)
> > > Signed-off-by: Chris Wilson
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.c | 5 +
> > > drivers/gpu/drm/i915/i915_drv.h
> -Original Message-
> From: Chris Wilson
> Sent: Friday, July 13, 2018 1:06 AM
> To: Bloomfield, Jon ; Zhenyu Wang
>
> Cc: intel-gfx@lists.freedesktop.org; Zhenyu Wang
> ; Joonas Lahtinen
> ; Matthew Auld
>
> Subject: Re: [PATCH 3/6] drm/i915/gtt: Disable read-only support under GVT
>
Our kbl-g in the CI farm very rarely recovers from suspend, and when it
does it innundated with DMAR errors for the VegaM. This is just a quick
hack to allow testing to continue.
Cc: Tomi Sarvela
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
Setup a userptr object that only has a read-only mapping back to a file
store (memfd). Then attempt to write into that mapping using the GPU and
assert that those writes do not land (while also writing via a writable
userptr mapping into the same memfd to verify that the GPU is working!)
v2: Pull
On Wed, Jul 11, 2018 at 02:59:04PM -0700, Paulo Zanoni wrote:
> The type is detected based on the interrupt ISR bit. Once detected,
> it's not supposed to be changed, so we have some sanity checks for
> that.
>
> Cc: Animesh Manna
> Signed-off-by: Paulo Zanoni
> Signed-off-by: Rodrigo Vivi
>
Hi Dave,
Things are still calm, but I'd like to add the GVT fix to this week
pull for 4.18.
Here goes drm-intel-fixes-2018-07-12:
- GVT fix for KBL vGPU hang to update virtual register from LRI.
- Fix hotplug irq ack on i965/g4x (Ville)
There's a silent conflict with gvt-fixes and gvt-next,
Hi Dave,
A single fix for building sun4i for v4.18-rc5.
drm-misc-fixes-2018-07-13:
Fixes for v4.18-rc5:
- Single fix for a build error when the driver is builtin,
but the backend is a loadable module.
The following changes since commit 44f9a4b0dc7563669772198e5b226cab58a00167:
On 7/12/2018 3:59 AM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Incomplete requests (no notify, no context complete) have to be corrected
by looking at the engine timeline, and not the sorted-by-start-time view
as was previously used.
Per-engine timelines are generated on demand and cached
On Wed, Jul 11, 2018 at 11:08:17PM -0700, Dhinakaran Pandiyan wrote:
> On Wed, 2018-07-11 at 22:27 -0700, Rodrigo Vivi wrote:
> > Reduce the module parameter to enable or disable.
> >
> > The link stand by vs full link off was used only once.
> >
> > And it was actually masking another bug fixed
On Wed, Jul 11, 2018 at 10:04:00PM +, Souza, Jose wrote:
> On Wed, 2018-07-11 at 15:00 -0700, Rodrigo Vivi wrote:
> > PSR is no longer supported on VLV/CHV so this is just dead code.
> >
>
> Reviewed-by: José Roberto de Souza
pushed to dinq, thanks
> > Cc: Dhinakaran Pandiyan
> >
== Series Details ==
Series: drm-intel-fixes
URL : https://patchwork.freedesktop.org/series/46451/
State : failure
== Summary ==
Applying: drm-intel-fixes
error: corrupt patch at line 13
error: could not build fake ancestor
Patch failed at 0001 drm-intel-fixes
Use 'git am
From: Antonio Argenziano
An hanging batch is nothing more than a spinning batch that never gets
stopped, so re-use the routines implemented in dummyload.c.
v2:
- Let caller decide spin loop size
- Now builds with meson.
v3:
- Only use loose loops for hangs (Chris)
v4:
On Thu, Jul 12, 2018 at 04:48:42PM -0700, Rodrigo Vivi wrote:
> On Thu, Jul 12, 2018 at 11:28:25PM +, De Marchi, Lucas wrote:
> > On Thu, 2018-07-12 at 16:06 -0700, Rodrigo Vivi wrote:
> > > On Thu, Jul 12, 2018 at 02:02:51PM -0700, Lucas De Marchi wrote:
> > > > After disabling resource
On Mon, Jul 09, 2018 at 05:06:58PM -0700, Lucas De Marchi wrote:
> After disabling resource streamer on ICL (due to it actually not
> existing there), I got feedback that there have been some experimental
> patches for mesa to use it, but nothing ever landed nor shipped.
>
> This is a tentative
Quoting Chris Wilson (2018-07-13 09:14:53)
> From: Antonio Argenziano
>
> An hanging batch is nothing more than a spinning batch that never gets
> stopped, so re-use the routines implemented in dummyload.c.
>
> v2:
> - Let caller decide spin loop size
> - Now builds with meson.
Quoting Rodrigo Vivi (2018-07-13 00:02:36)
> On Thu, Jul 12, 2018 at 09:20:27PM +0100, Chris Wilson wrote:
> > After aborting a module load, we may try and disable guc before we have
> > finished setting it. Long term plan is to ensure perfect onion unwind,
> > but in the short term we want to fix
Quoting Oscar Mateo (2018-04-24 22:39:55)
> Interrupt handling in Gen11 is quite different from previous platforms.
>
> v2: Rebased (Michel)
> v3: Rebased with wiggle
> v4: Rebased, remove TODO warning correctly (Daniele)
> v5: Rebased, made gen11_gtiir const while at it (Michel)
> v6: Rebased
>
With the new CSB processing code, we are not vulnerable to delayed
delivery of a pre-reset interrupt as we use the CSB status pointers in
the HWSP to decide if we need to parse any CSB events and no longer need
to wait for the first post-reset interrupt to be assured that the CSB
mmio registers
== Series Details ==
Series: drm/i915/execlists: Drop clear_gtiir() on GPU reset
URL : https://patchwork.freedesktop.org/series/46460/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4483 -> Patchwork_9644 =
== Summary - SUCCESS ==
No regressions found.
External URL:
Enjoy!
The following changes since commit ce397d215ccd07b8ae3f71db689aedb85d56ab40:
Linux 4.18-rc1 (2018-06-17 08:04:49 +0900)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git
ib-mfd-i915-media-platform-v4.19
for you to fetch changes up to
Quoting Zhenyu Wang (2018-07-13 03:03:10)
> On 2018.07.12 20:36:03 +, Bloomfield, Jon wrote:
> > > -Original Message-
> > > From: Chris Wilson
> > > Sent: Thursday, July 12, 2018 11:53 AM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Chris Wilson ; Zhenyu Wang
> > > ;
On Thu, Jul 12, 2018 at 08:23:05PM +0300, Ville Syrjälä wrote:
> On Thu, Jul 12, 2018 at 07:03:58PM +0200, Daniel Vetter wrote:
> > On Thu, Jul 12, 2018 at 6:24 PM, Lucas De Marchi
> > wrote:
> > > On Thu, Jul 12, 2018 at 05:04:03PM +0200, Daniel Vetter wrote:
> > >> On Mon, Jul 09, 2018 at
== Series Details ==
Series: drm/i915/execlists: Drop clear_gtiir() on GPU reset
URL : https://patchwork.freedesktop.org/series/46460/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3f6a21834ad0 drm/i915/execlists: Drop clear_gtiir() on GPU reset
-:153: ERROR:GIT_COMMIT_ID:
On 07/12/2018 08:45 AM, Joe Perches wrote:
> On Wed, 2018-07-11 at 20:50 +0200, Daniel Vetter wrote:
>> On Wed, Jul 11, 2018 at 8:30 PM, Jens Axboe wrote:
>>> On 7/11/18 10:45 AM, Tejun Heo wrote:
On Wed, Jul 11, 2018 at 09:40:58AM -0700, Tejun Heo wrote:
> On Mon, Jul 09, 2018 at
This patch implements get_crc_sources callback, which returns list of
all the crc sources supported by driver in current platform.
Changes Since V1:
- move sources list per-crtc
- init sources-list only for gen3
Signed-off-by: Mahesh Kumar
Cc: Laurent Pinchart
---
This patch make changes to allocate crc-entries buffer before
enabling CRC generation.
It moves all the failure check early in the function before setting
the source or memory allocation.
Now set_crc_source takes only two variable inputs, values_cnt we
already gets as part of verify_crc_source.
This patch implements "verify_crc_source" callback function for
rcar drm driver.
Changes Since V1:
- avoid duplication of code
Changes Since V2:
- further optimize the code
Signed-off-by: Mahesh Kumar
Cc: dri-de...@lists.freedesktop.org
Cc: Laurent Pinchart
Reviewed-by: Maarten Lankhorst
This patch implements "verify_crc_source" callback function for
AMD drm driver.
Signed-off-by: Mahesh Kumar
Cc: dri-de...@lists.freedesktop.org
Reviewed-by: Maarten Lankhorst
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
This patch adds support to decode system memory bandwidth and other
parameters for skylake and Gen9+ platforms, which will be used for
arbitrated display memory bandwidth calculation in GEN9 based
platforms and WM latency level-0 Work-around calculation on GEN9+.
Signed-off-by: Mahesh Kumar
---
This series adds support to calculate system memdev parameters and calculate
total system memory bandwidth. This parameters and BW will be used to enable
WM level-0 latency workaround and display memory bandwidth related WA for gen9.
Mahesh Kumar (3):
drm/i915/bxt: Decode memory bandwidth and
This patch adds support to decode system memory bandwidth and other
parameters for broxton platform, which will be used for arbitrated
display memory bandwidth calculation in GEN9 based platforms and
WM latency level-0 Work-around calculation on GEN9+ platforms.
Signed-off-by: Mahesh Kumar
---
Memory with 16GB dimms require an increase of 1us in level-0 latency.
This patch implements the same.
Bspec: 4381
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/i915_drv.c | 35 +--
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c |
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