[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gvt: Use after free in intel_vgpu_destroy_ggtt_mm()
== Series Details == Series: drm/i915/gvt: Use after free in intel_vgpu_destroy_ggtt_mm() URL : https://patchwork.freedesktop.org/series/52910/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5194 -> Patchwork_10892 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52910/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10892 that come from known issues: === IGT changes === Issues hit igt@gem_ctx_create@basic-files: fi-bsw-n3050: PASS -> FAIL (fdo#108656) fi-icl-u2: PASS -> DMESG-WARN (fdo#107724) igt@gem_exec_suspend@basic-s4-devices: fi-bsw-kefka: PASS -> DMESG-WARN (fdo#108041) igt@i915_selftest@live_hangcheck: fi-kbl-7560u: PASS -> INCOMPLETE (fdo#108044) Possible fixes igt@gem_exec_suspend@basic-s3: fi-icl-u2: DMESG-WARN (fdo#107724) -> PASS igt@i915_module_load@reload: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724 fdo#108041 https://bugs.freedesktop.org/show_bug.cgi?id=108041 fdo#108044 https://bugs.freedesktop.org/show_bug.cgi?id=108044 fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656 == Participating hosts (48 -> 42) == Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u3 fi-icl-y == Build changes == * Linux: CI_DRM_5194 -> Patchwork_10892 CI_DRM_5194: 59472c09fbb08ec6d312690b23057064d34069eb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4725: 9dc7c41d1c600133d6e3e63f1941c2e75d23bd3b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10892: a74710452c2cdafcccea5f8412d1a92c7df1f516 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a74710452c2c drm/i915/gvt: Use after free in intel_vgpu_destroy_ggtt_mm() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10892/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gvt: Use after free in intel_vgpu_destroy_ggtt_mm()
On 2018.11.23 10:22:19 +0300, Dan Carpenter wrote:
> We need to use the _safe() version of this macro so that we don't
> dereference "pos" when it is freed.
>
Thanks, Dan.
I've already merged one same fix from Chris for this found by smatch.
> Fixes: bc0686ff5fad ("drm/i915/gvt: support inconsecutive partial gtt entry
> write")
> Signed-off-by: Dan Carpenter
> ---
> drivers/gpu/drm/i915/gvt/gtt.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index 58e166effa45..3f416341ae5f 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -2447,9 +2447,9 @@ static void intel_vgpu_destroy_all_ppgtt_mm(struct
> intel_vgpu *vgpu)
>
> static void intel_vgpu_destroy_ggtt_mm(struct intel_vgpu *vgpu)
> {
> - struct intel_gvt_partial_pte *pos;
> + struct intel_gvt_partial_pte *pos, *n;
>
> - list_for_each_entry(pos,
> + list_for_each_entry_safe(pos, n,
> >gtt.ggtt_mm->ggtt_mm.partial_pte_list, list) {
> gvt_dbg_mm("partial PTE update on hold 0x%lx : 0x%llx\n",
> pos->offset, pos->data);
> --
> 2.11.0
>
--
Open Source Technology Center, Intel ltd.
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gvt: Use after free in intel_vgpu_destroy_ggtt_mm()
== Series Details ==
Series: drm/i915/gvt: Use after free in intel_vgpu_destroy_ggtt_mm()
URL : https://patchwork.freedesktop.org/series/52910/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a74710452c2c drm/i915/gvt: Use after free in intel_vgpu_destroy_ggtt_mm()
-:25: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#25: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2453:
+ list_for_each_entry_safe(pos, n,
>gtt.ggtt_mm->ggtt_mm.partial_pte_list, list) {
total: 0 errors, 0 warnings, 1 checks, 11 lines checked
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[Intel-gfx] [PATCH] drm/i915/gvt: Use after free in intel_vgpu_destroy_ggtt_mm()
We need to use the _safe() version of this macro so that we don't
dereference "pos" when it is freed.
Fixes: bc0686ff5fad ("drm/i915/gvt: support inconsecutive partial gtt entry
write")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/i915/gvt/gtt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 58e166effa45..3f416341ae5f 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -2447,9 +2447,9 @@ static void intel_vgpu_destroy_all_ppgtt_mm(struct
intel_vgpu *vgpu)
static void intel_vgpu_destroy_ggtt_mm(struct intel_vgpu *vgpu)
{
- struct intel_gvt_partial_pte *pos;
+ struct intel_gvt_partial_pte *pos, *n;
- list_for_each_entry(pos,
+ list_for_each_entry_safe(pos, n,
>gtt.ggtt_mm->ggtt_mm.partial_pte_list, list) {
gvt_dbg_mm("partial PTE update on hold 0x%lx : 0x%llx\n",
pos->offset, pos->data);
--
2.11.0
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[Intel-gfx] ✗ Fi.CI.IGT: failure for RFC: mmu notifier debug checks
== Series Details ==
Series: RFC: mmu notifier debug checks
URL : https://patchwork.freedesktop.org/series/52890/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5191_full -> Patchwork_10888_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10888_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10888_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in
Patchwork_10888_full:
=== IGT changes ===
Possible regressions
igt@gem_userptr_blits@dmabuf-sync:
{shard-iclb}: PASS -> DMESG-WARN +4
shard-kbl: PASS -> DMESG-WARN +9
igt@gem_userptr_blits@map-fixed-invalidate-busy:
shard-skl: NOTRUN -> DMESG-WARN +1
igt@gem_userptr_blits@map-fixed-invalidate-gup:
shard-apl: PASS -> DMESG-WARN +5
igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
shard-hsw: PASS -> DMESG-WARN +4
igt@gem_userptr_blits@map-fixed-invalidate-overlap-gup:
shard-skl: PASS -> DMESG-WARN +6
shard-glk: PASS -> DMESG-WARN +4
igt@gem_userptr_blits@sync-unmap-cycles:
shard-snb: PASS -> DMESG-WARN +9
igt@pm_rpm@modeset-non-lpsp-stress:
{shard-iclb}: SKIP -> INCOMPLETE
{igt@runner@aborted}:
shard-glk: NOTRUN -> FAIL
shard-hsw: NOTRUN -> FAIL
shard-snb: NOTRUN -> ( 3 FAIL )
shard-kbl: NOTRUN -> ( 3 FAIL )
shard-skl: NOTRUN -> ( 3 FAIL )
{shard-iclb}: NOTRUN -> ( 2 FAIL )
Warnings
igt@perf_pmu@rc6:
shard-kbl: SKIP -> PASS
igt@tools_test@tools_test:
shard-hsw: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_10888_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@gem_cpu_reloc@full:
shard-skl: PASS -> INCOMPLETE (fdo#108073)
igt@kms_available_modes_crc@available_mode_test_crc:
shard-apl: PASS -> FAIL (fdo#106641)
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
shard-skl: NOTRUN -> DMESG-WARN (fdo#107956)
igt@kms_cursor_crc@cursor-128x128-suspend:
shard-glk: PASS -> FAIL (fdo#103232) +3
igt@kms_cursor_crc@cursor-256x256-random:
shard-apl: PASS -> FAIL (fdo#103232) +4
igt@kms_fbcon_fbt@fbc-suspend:
shard-apl: PASS -> INCOMPLETE (fdo#103927)
igt@kms_fbcon_fbt@psr-suspend:
shard-skl: NOTRUN -> FAIL (fdo#107882)
igt@kms_flip@flip-vs-expired-vblank:
shard-glk: PASS -> FAIL (fdo#105363)
igt@kms_flip@modeset-vs-vblank-race-interruptible:
shard-glk: PASS -> FAIL (fdo#103060)
igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu:
shard-skl: PASS -> FAIL (fdo#105682)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
shard-apl: PASS -> FAIL (fdo#103167) +2
igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
shard-glk: PASS -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
{shard-iclb}: PASS -> FAIL (fdo#103167) +4
igt@kms_plane@pixel-format-pipe-b-planes:
shard-skl: NOTRUN -> DMESG-WARN (fdo#106885)
igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
shard-skl: PASS -> FAIL (fdo#108145, fdo#107815)
igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
shard-skl: NOTRUN -> FAIL (fdo#107815)
igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
shard-glk: PASS -> FAIL (fdo#103166)
igt@kms_universal_plane@universal-plane-pipe-a-functional:
shard-apl: PASS -> FAIL (fdo#103166)
igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#107773)
igt@pm_rpm@gem-mmap-gtt:
shard-skl: PASS -> INCOMPLETE (fdo#107807)
Possible fixes
igt@kms_busy@extended-pageflip-hang-newfb-render-b:
shard-glk: DMESG-WARN (fdo#107956) -> PASS
igt@kms_cursor_crc@cursor-128x128-suspend:
shard-apl: FAIL (fdo#103232, fdo#103191) -> PASS
igt@kms_cursor_crc@cursor-256x85-sliding:
shard-apl: FAIL (fdo#103232) -> PASS +2
igt@kms_cursor_crc@cursor-64x64-offscreen:
shard-skl: FAIL (fdo#103232) -> PASS
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-skl: FAIL (fdo#105363) -> PASS
shard-apl: FAIL (fdo#102887, fdo#105363) -> PASS
[Intel-gfx] linux-next: manual merge of the drm-misc tree with the drm tree
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/Makefile
between commit:
2bb42410b1bd ("drm: Remove drm_global.{c,h} v2")
from the drm tree and commit:
c6fdea6e1a19 ("drm: Merge drm_info.c into drm_debugfs.c")
from the drm-misc tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc drivers/gpu/drm/Makefile
index 7f3be3506057,7c88f12096c5..
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@@ -10,8 -10,8 +10,8 @@@ drm-y :=drm_auth.o drm_bufs.o dr
drm_scatter.o drm_pci.o \
drm_sysfs.o drm_hashtab.o drm_mm.o \
drm_crtc.o drm_fourcc.o drm_modes.o drm_edid.o \
- drm_info.o drm_encoder_slave.o \
+ drm_encoder_slave.o \
- drm_trace_points.o drm_global.o drm_prime.o \
+ drm_trace_points.o drm_prime.o \
drm_rect.o drm_vma_manager.o drm_flip_work.o \
drm_modeset_lock.o drm_atomic.o drm_bridge.o \
drm_framebuffer.o drm_connector.o drm_blend.o \
pgppzNZhyjLgf.pgp
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v5,1/6] drm/i915: Avoid a full port detection in the first eDP short pulse
Merged to drm-intel-next-queued, thanks for the reviews Ville and Rodrigo. On Thu, 2018-11-22 at 03:23 +, Patchwork wrote: > == Series Details == > > Series: series starting with [v5,1/6] drm/i915: Avoid a full port > detection in the first eDP short pulse > URL : https://patchwork.freedesktop.org/series/52848/ > State : success > > == Summary == > > = CI Bug Log - changes from CI_DRM_5183_full -> Patchwork_10883_full > = > > == Summary - WARNING == > > Minor unknown changes coming with Patchwork_10883_full need to be > verified > manually. > > If you think the reported changes have nothing to do with the > changes > introduced in Patchwork_10883_full, please notify your bug team to > allow them > to document this new failure mode, which will reduce false > positives in CI. > > > > == Possible new issues == > > Here are the unknown changes that may have been introduced in > Patchwork_10883_full: > > === IGT changes === > > Warnings > > igt@kms_universal_plane@disable-primary-vs-flip-pipe-b: > shard-snb: SKIP -> PASS +9 > > igt@perf_pmu@rc6-runtime-pm-long: > shard-kbl: PASS -> SKIP > > igt@tools_test@tools_test: > shard-apl: PASS -> SKIP > > > == Known issues == > > Here are the changes found in Patchwork_10883_full that come from > known issues: > > === IGT changes === > > Issues hit > > igt@gem_cpu_reloc@full: > shard-skl: NOTRUN -> INCOMPLETE (fdo#108073) > > igt@gem_exec_schedule@pi-ringfull-vebox: > shard-skl: NOTRUN -> FAIL (fdo#103158) > > igt@gem_mmap_gtt@forked-big-copy-odd: > shard-apl: PASS -> INCOMPLETE (fdo#103927) > > igt@kms_busy@extended-modeset-hang-newfb-render-a: > shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +4 > > igt@kms_color@pipe-b-degamma: > shard-skl: PASS -> FAIL (fdo#104782) > > igt@kms_cursor_crc@cursor-128x42-sliding: > shard-glk: PASS -> FAIL (fdo#103232) > > igt@kms_cursor_crc@cursor-64x21-random: > shard-apl: PASS -> FAIL (fdo#103232) +2 > > igt@kms_flip@flip-vs-expired-vblank-interruptible: > shard-glk: PASS -> FAIL (fdo#102887, fdo#105363) > > igt@kms_flip@plain-flip-ts-check: > shard-kbl: PASS -> DMESG-WARN (fdo#103558, fdo#105602, > fdo#103313) +4 > > igt@kms_frontbuffer_tracking@fbc-1p-rte: > shard-kbl: PASS -> DMESG-WARN (fdo#103558, fdo#103313) > > igt@kms > _frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu: > shard-glk: PASS -> FAIL (fdo#103167) +3 > > igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render: > shard-skl: PASS -> FAIL (fdo#103167) > > igt@kms_frontbuffer_tracking@fbcpsr-stridechange: > shard-skl: NOTRUN -> FAIL (fdo#105683) > > igt@kms > _frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite: > shard-skl: NOTRUN -> FAIL (fdo#103167) > > igt@kms_plane@pixel-format-pipe-b-planes: > shard-skl: NOTRUN -> DMESG-WARN (fdo#106885) > > igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb: > shard-skl: NOTRUN -> FAIL (fdo#108145) +1 > > igt@kms_plane_multiple@atomic-pipe-a-tiling-y: > shard-apl: PASS -> FAIL (fdo#103166) +1 > > igt@kms_plane_multiple@atomic-pipe-b-tiling-x: > shard-glk: PASS -> FAIL (fdo#103166) +1 > > igt@kms_rotation_crc@primary-rotation-90: > shard-skl: PASS -> FAIL (fdo#107815, fdo#103925) > > > Possible fixes > > igt@gem_exec_schedule@preemptive-hang-render: > shard-apl: INCOMPLETE (fdo#103927) -> PASS > > igt@kms_cursor_crc@cursor-256x256-onscreen: > shard-glk: FAIL (fdo#103232) -> PASS +1 > > igt@kms_cursor_crc@cursor-64x21-sliding: > shard-apl: FAIL (fdo#103232) -> PASS +3 > > igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled: > shard-glk: FAIL (fdo#103184) -> PASS > > igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff: > shard-glk: FAIL (fdo#103167) -> PASS +1 > > igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: > shard-glk: INCOMPLETE (fdo#103359, k.org#198133) -> > PASS > > igt@kms_plane@plane-position-covered-pipe-c-planes: > shard-apl: FAIL (fdo#103166) -> PASS > > igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: > shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS > +4 > > igt@pm_rpm@universal-planes-dpms: > shard-skl: INCOMPLETE (fdo#107807) -> PASS +1 > > > Warnings > > igt@i915_suspend@shrink: > shard-skl: DMESG-WARN (fdo#108784) -> INCOMPLETE > (fdo#106886) > > igt@kms_plane@pixel-format-pipe-a-planes: > shard-skl:
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/selftests: Flush the test object on creation (rev4)
== Series Details == Series: series starting with [1/3] drm/i915/selftests: Flush the test object on creation (rev4) URL : https://patchwork.freedesktop.org/series/52887/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5191 -> Patchwork_10891 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10891 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10891, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/52887/revisions/4/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10891: === IGT changes === Possible regressions igt@i915_selftest@live_coherency: fi-skl-6770hq: PASS -> DMESG-FAIL fi-byt-n2820: PASS -> DMESG-FAIL fi-skl-6700k2: PASS -> DMESG-FAIL fi-elk-e7500: PASS -> DMESG-FAIL fi-skl-iommu: PASS -> DMESG-FAIL +1 fi-skl-gvtdvm: PASS -> DMESG-FAIL +1 fi-hsw-peppy: PASS -> DMESG-FAIL fi-bdw-gvtdvm: PASS -> DMESG-FAIL fi-bxt-j4205: PASS -> DMESG-FAIL fi-skl-guc: PASS -> DMESG-FAIL fi-cnl-u: PASS -> DMESG-FAIL fi-bxt-dsi: PASS -> DMESG-FAIL fi-cfl-8700k: PASS -> DMESG-FAIL fi-ilk-650: PASS -> DMESG-FAIL fi-bsw-n3050: PASS -> DMESG-FAIL fi-hsw-4770:PASS -> DMESG-FAIL fi-glk-dsi: PASS -> DMESG-FAIL fi-ivb-3770:PASS -> DMESG-FAIL fi-skl-6700hq: PASS -> DMESG-FAIL fi-hsw-4770r: PASS -> DMESG-FAIL fi-bsw-kefka: PASS -> DMESG-FAIL fi-glk-j4005: PASS -> DMESG-FAIL fi-byt-clapper: PASS -> DMESG-FAIL fi-apl-guc: PASS -> DMESG-FAIL fi-skl-6600u: PASS -> DMESG-FAIL igt@i915_selftest@live_contexts: fi-bdw-5557u: PASS -> DMESG-FAIL +1 == Known issues == Here are the changes found in Patchwork_10891 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-icl-u2: PASS -> DMESG-WARN (fdo#107724) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) +1 igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) Possible fixes igt@gem_ctx_create@basic-files: fi-icl-u2: DMESG-WARN (fdo#107724) -> PASS igt@i915_selftest@live_hangcheck: fi-bwr-2160:DMESG-FAIL (fdo#108735) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724 fdo#108735 https://bugs.freedesktop.org/show_bug.cgi?id=108735 == Participating hosts (51 -> 42) == Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-u3 fi-kbl-r == Build changes == * Linux: CI_DRM_5191 -> Patchwork_10891 CI_DRM_5191: cdb3ce838d4020951ea12c11cf952c6f2419dd36 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4725: 9dc7c41d1c600133d6e3e63f1941c2e75d23bd3b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10891: 0e5c8d6ae8b914d15019ae72a5b17ab7bf4b2460 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0e5c8d6ae8b9 drm/i915: Avoid using MI_STORE_DWORD_IMM on vecs eb145c3815b6 drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency 821c90f3f442 drm/i915/selftests: Flush the test object on creation == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10891/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/selftests: Flush the test object on creation (rev4)
== Series Details == Series: series starting with [1/3] drm/i915/selftests: Flush the test object on creation (rev4) URL : https://patchwork.freedesktop.org/series/52887/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/selftests: Flush the test object on creation Okay! Commit: drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency +drivers/gpu/drm/i915/selftests/i915_gem_coherency.c:834:33: warning: expression using sizeof(void) Commit: drm/i915: Avoid using MI_STORE_DWORD_IMM on vecs Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/selftests: Flush the test object on creation (rev4)
== Series Details ==
Series: series starting with [1/3] drm/i915/selftests: Flush the test object on
creation (rev4)
URL : https://patchwork.freedesktop.org/series/52887/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
821c90f3f442 drm/i915/selftests: Flush the test object on creation
eb145c3815b6 drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency
-:440: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#440: FILE: drivers/gpu/drm/i915/selftests/i915_gem_coherency.c:798:
+ obj = create_test_object(i915, npages,
+ file, );
-:452: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#452: FILE: drivers/gpu/drm/i915/selftests/i915_gem_coherency.c:810:
+ pr_err("Failed to fill dword %lu [%lu]
with gpu (%s), err=%d\n",
+ ndwords, dw,
engine->name, err);
-:469: WARNING:LONG_LINE: line over 100 characters
#469: FILE: drivers/gpu/drm/i915/selftests/i915_gem_coherency.c:827:
+ pr_info("Submitted %lu/%lu dwords (across %lu engines) in %lu
jiffies\n", ndwords, width, dw, timeout);
total: 0 errors, 1 warnings, 2 checks, 483 lines checked
0e5c8d6ae8b9 drm/i915: Avoid using MI_STORE_DWORD_IMM on vecs
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/selftests: Flush the test object on creation (rev3)
== Series Details == Series: series starting with [1/3] drm/i915/selftests: Flush the test object on creation (rev3) URL : https://patchwork.freedesktop.org/series/52887/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5191 -> Patchwork_10890 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10890 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10890, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/52887/revisions/3/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10890: === IGT changes === Possible regressions igt@i915_selftest@live_coherency: fi-skl-6770hq: PASS -> DMESG-FAIL fi-skl-6700k2: PASS -> DMESG-FAIL fi-kbl-x1275: PASS -> DMESG-FAIL fi-skl-guc: PASS -> DMESG-FAIL fi-cfl-8700k: PASS -> DMESG-FAIL fi-hsw-4770:PASS -> DMESG-FAIL fi-cfl-guc: PASS -> DMESG-FAIL fi-ivb-3770:PASS -> DMESG-FAIL fi-skl-6700hq: PASS -> DMESG-FAIL fi-hsw-4770r: PASS -> DMESG-FAIL fi-kbl-guc: PASS -> DMESG-FAIL fi-skl-6600u: PASS -> DMESG-FAIL igt@i915_selftest@live_contexts: fi-bxt-j4205: PASS -> DMESG-FAIL fi-bdw-5557u: PASS -> DMESG-FAIL +1 fi-skl-iommu: PASS -> DMESG-FAIL fi-apl-guc: PASS -> DMESG-FAIL == Known issues == Here are the changes found in Patchwork_10890 that come from known issues: === IGT changes === Issues hit igt@gem_ctx_create@basic-files: fi-bsw-kefka: PASS -> FAIL (fdo#108656) igt@gem_ctx_switch@basic-default: fi-icl-u2: PASS -> DMESG-WARN (fdo#107724) igt@i915_selftest@live_contexts: fi-glk-j4005: PASS -> DMESG-FAIL (fdo#107830) igt@kms_pipe_crc_basic@read-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#107362) Possible fixes igt@gem_ctx_create@basic-files: fi-icl-u2: DMESG-WARN (fdo#107724) -> PASS igt@i915_selftest@live_hangcheck: fi-bwr-2160:DMESG-FAIL (fdo#108735) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724 fdo#107830 https://bugs.freedesktop.org/show_bug.cgi?id=107830 fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656 fdo#108735 https://bugs.freedesktop.org/show_bug.cgi?id=108735 == Participating hosts (51 -> 43) == Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-u3 fi-kbl-r == Build changes == * Linux: CI_DRM_5191 -> Patchwork_10890 CI_DRM_5191: cdb3ce838d4020951ea12c11cf952c6f2419dd36 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4725: 9dc7c41d1c600133d6e3e63f1941c2e75d23bd3b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10890: f4a1572efe1af911ee6b8536c09c6bcfb1bcd2db @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f4a1572efe1a drm/i915: Avoid using MI_STORE_DWORD_IMM on vecs c741eb757e0c drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency d8c8001692a3 drm/i915/selftests: Flush the test object on creation == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10890/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4] drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency
We use MI_STORE_DWORD_IMM internally (e.g. for gpu relocations) and so
require that its are writes flushed to memory on demand. Verify this with
a selftest.
v2: Use variable lengths of submission queues as the delay between
submit and checking is also crucially important for error detection.
v3: Keep a ref to avoid the shrinker stealing our objects
Signed-off-by: Chris Wilson
---
.../drm/i915/selftests/i915_gem_coherency.c | 467 ++
1 file changed, 467 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
index f7392c1ffe75..791cdbffae05 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
@@ -26,6 +26,7 @@
#include "../i915_selftest.h"
#include "i915_random.h"
+#include "igt_flush_test.h"
static int cpu_set(struct drm_i915_gem_object *obj,
unsigned long offset,
@@ -386,10 +387,476 @@ static int igt_gem_coherency(void *arg)
goto unlock;
}
+#define DW_PER_PAGE (PAGE_SIZE / sizeof(u32))
+
+struct live_test {
+ struct drm_i915_private *i915;
+ const char *func;
+ const char *name;
+
+ unsigned int reset_global;
+ unsigned int reset_engine[I915_NUM_ENGINES];
+};
+
+static int begin_live_test(struct live_test *t,
+ struct drm_i915_private *i915,
+ const char *func,
+ const char *name)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err;
+
+ t->i915 = i915;
+ t->func = func;
+ t->name = name;
+
+ err = i915_gem_wait_for_idle(i915,
+I915_WAIT_LOCKED,
+MAX_SCHEDULE_TIMEOUT);
+ if (err) {
+ pr_err("%s(%s): failed to idle before, with err=%d!",
+ func, name, err);
+ return err;
+ }
+
+ i915->gpu_error.missed_irq_rings = 0;
+ t->reset_global = i915_reset_count(>gpu_error);
+
+ for_each_engine(engine, i915, id)
+ t->reset_engine[id] =
+ i915_reset_engine_count(>gpu_error, engine);
+
+ return 0;
+}
+
+static int end_live_test(struct live_test *t)
+{
+ struct drm_i915_private *i915 = t->i915;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ if (igt_flush_test(i915, I915_WAIT_LOCKED))
+ return -EIO;
+
+ if (t->reset_global != i915_reset_count(>gpu_error)) {
+ pr_err("%s(%s): GPU was reset %d times!\n",
+ t->func, t->name,
+ i915_reset_count(>gpu_error) - t->reset_global);
+ return -EIO;
+ }
+
+ for_each_engine(engine, i915, id) {
+ if (t->reset_engine[id] ==
+ i915_reset_engine_count(>gpu_error, engine))
+ continue;
+
+ pr_err("%s(%s): engine '%s' was reset %d times!\n",
+ t->func, t->name, engine->name,
+ i915_reset_engine_count(>gpu_error, engine) -
+ t->reset_engine[id]);
+ return -EIO;
+ }
+
+ if (i915->gpu_error.missed_irq_rings) {
+ pr_err("%s(%s): Missed interrupts on engines %lx\n",
+ t->func, t->name, i915->gpu_error.missed_irq_rings);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int cpu_fill(struct drm_i915_gem_object *obj, u32 value)
+{
+ const bool has_llc = HAS_LLC(to_i915(obj->base.dev));
+ unsigned int n, need_flush;
+ int err;
+
+ err = i915_gem_obj_prepare_shmem_write(obj, _flush);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; n++) {
+ u32 *map;
+
+ map = kmap_atomic(i915_gem_object_get_page(obj, n));
+ memset32(map, value, DW_PER_PAGE);
+ if (!has_llc)
+ drm_clflush_virt_range(map, PAGE_SIZE);
+ kunmap_atomic(map);
+ }
+
+ i915_gem_obj_finish_shmem_access(obj);
+ obj->read_domains = I915_GEM_DOMAIN_GTT | I915_GEM_DOMAIN_CPU;
+ obj->write_domain = 0;
+ return 0;
+}
+
+static int file_add_object(struct drm_file *file,
+ struct drm_i915_gem_object *obj)
+{
+ int err;
+
+ GEM_BUG_ON(obj->base.handle_count);
+
+ /* tie the object to the drm_file for easy reaping */
+ err = idr_alloc(>object_idr, >base, 1, 0, GFP_KERNEL);
+ if (err < 0)
+ return err;
+
+ i915_gem_object_get(obj);
+ obj->base.handle_count++;
+ return 0;
+}
+
+static struct drm_i915_gem_object *
+create_test_object(struct drm_i915_private *i915,
+ unsigned int num_pages,
+ struct drm_file *file,
+
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/selftests: Flush the test object on creation (rev3)
== Series Details == Series: series starting with [1/3] drm/i915/selftests: Flush the test object on creation (rev3) URL : https://patchwork.freedesktop.org/series/52887/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/selftests: Flush the test object on creation Okay! Commit: drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency +drivers/gpu/drm/i915/selftests/i915_gem_coherency.c:828:33: warning: expression using sizeof(void) Commit: drm/i915: Avoid using MI_STORE_DWORD_IMM on vecs Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/selftests: Flush the test object on creation (rev3)
== Series Details ==
Series: series starting with [1/3] drm/i915/selftests: Flush the test object on
creation (rev3)
URL : https://patchwork.freedesktop.org/series/52887/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d8c8001692a3 drm/i915/selftests: Flush the test object on creation
c741eb757e0c drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency
-:436: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#436: FILE: drivers/gpu/drm/i915/selftests/i915_gem_coherency.c:795:
+ obj = create_test_object(i915, npages,
+ file, );
-:448: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#448: FILE: drivers/gpu/drm/i915/selftests/i915_gem_coherency.c:807:
+ pr_err("Failed to fill dword %lu [%lu]
with gpu (%s), err=%d\n",
+ ndwords, dw,
engine->name, err);
-:463: WARNING:LONG_LINE: line over 100 characters
#463: FILE: drivers/gpu/drm/i915/selftests/i915_gem_coherency.c:822:
+ pr_info("Submitted %lu dwords (across %lu engines) in %lu
jiffies\n", ndwords, dw, timeout);
total: 0 errors, 1 warnings, 2 checks, 476 lines checked
f4a1572efe1a drm/i915: Avoid using MI_STORE_DWORD_IMM on vecs
___
Intel-gfx mailing list
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[Intel-gfx] [PATCH v3] drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency
We use MI_STORE_DWORD_IMM internally (e.g. for gpu relocations) and so
require that its are writes flushed to memory on demand. Verify this with
a selftest.
v2: Use variable lengths of submission queues as the delay between
submit and checking is also crucially important for error detection.
Signed-off-by: Chris Wilson
---
.../drm/i915/selftests/i915_gem_coherency.c | 460 ++
1 file changed, 460 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
index f7392c1ffe75..48224eee0e5d 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
@@ -26,6 +26,7 @@
#include "../i915_selftest.h"
#include "i915_random.h"
+#include "igt_flush_test.h"
static int cpu_set(struct drm_i915_gem_object *obj,
unsigned long offset,
@@ -386,10 +387,469 @@ static int igt_gem_coherency(void *arg)
goto unlock;
}
+#define DW_PER_PAGE (PAGE_SIZE / sizeof(u32))
+
+struct live_test {
+ struct drm_i915_private *i915;
+ const char *func;
+ const char *name;
+
+ unsigned int reset_global;
+ unsigned int reset_engine[I915_NUM_ENGINES];
+};
+
+static int begin_live_test(struct live_test *t,
+ struct drm_i915_private *i915,
+ const char *func,
+ const char *name)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err;
+
+ t->i915 = i915;
+ t->func = func;
+ t->name = name;
+
+ err = i915_gem_wait_for_idle(i915,
+I915_WAIT_LOCKED,
+MAX_SCHEDULE_TIMEOUT);
+ if (err) {
+ pr_err("%s(%s): failed to idle before, with err=%d!",
+ func, name, err);
+ return err;
+ }
+
+ i915->gpu_error.missed_irq_rings = 0;
+ t->reset_global = i915_reset_count(>gpu_error);
+
+ for_each_engine(engine, i915, id)
+ t->reset_engine[id] =
+ i915_reset_engine_count(>gpu_error, engine);
+
+ return 0;
+}
+
+static int end_live_test(struct live_test *t)
+{
+ struct drm_i915_private *i915 = t->i915;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ if (igt_flush_test(i915, I915_WAIT_LOCKED))
+ return -EIO;
+
+ if (t->reset_global != i915_reset_count(>gpu_error)) {
+ pr_err("%s(%s): GPU was reset %d times!\n",
+ t->func, t->name,
+ i915_reset_count(>gpu_error) - t->reset_global);
+ return -EIO;
+ }
+
+ for_each_engine(engine, i915, id) {
+ if (t->reset_engine[id] ==
+ i915_reset_engine_count(>gpu_error, engine))
+ continue;
+
+ pr_err("%s(%s): engine '%s' was reset %d times!\n",
+ t->func, t->name, engine->name,
+ i915_reset_engine_count(>gpu_error, engine) -
+ t->reset_engine[id]);
+ return -EIO;
+ }
+
+ if (i915->gpu_error.missed_irq_rings) {
+ pr_err("%s(%s): Missed interrupts on engines %lx\n",
+ t->func, t->name, i915->gpu_error.missed_irq_rings);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int cpu_fill(struct drm_i915_gem_object *obj, u32 value)
+{
+ const bool has_llc = HAS_LLC(to_i915(obj->base.dev));
+ unsigned int n, need_flush;
+ int err;
+
+ err = i915_gem_obj_prepare_shmem_write(obj, _flush);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; n++) {
+ u32 *map;
+
+ map = kmap_atomic(i915_gem_object_get_page(obj, n));
+ memset32(map, value, DW_PER_PAGE);
+ if (!has_llc)
+ drm_clflush_virt_range(map, PAGE_SIZE);
+ kunmap_atomic(map);
+ }
+
+ i915_gem_obj_finish_shmem_access(obj);
+ obj->read_domains = I915_GEM_DOMAIN_GTT | I915_GEM_DOMAIN_CPU;
+ obj->write_domain = 0;
+ return 0;
+}
+
+static int file_add_object(struct drm_file *file,
+ struct drm_i915_gem_object *obj)
+{
+ int err;
+
+ GEM_BUG_ON(obj->base.handle_count);
+
+ /* tie the object to the drm_file for easy reaping */
+ err = idr_alloc(>object_idr, >base, 1, 0, GFP_KERNEL);
+ if (err < 0)
+ return err;
+
+ i915_gem_object_get(obj);
+ obj->base.handle_count++;
+ return 0;
+}
+
+static struct drm_i915_gem_object *
+create_test_object(struct drm_i915_private *i915,
+ unsigned int num_pages,
+ struct drm_file *file,
+ struct list_head *objects)
+{
+ struct
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/selftests: Flush the test object on creation (rev2)
== Series Details ==
Series: series starting with [1/3] drm/i915/selftests: Flush the test object on
creation (rev2)
URL : https://patchwork.freedesktop.org/series/52887/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5191 -> Patchwork_10889 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10889 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10889, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/52887/revisions/2/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10889:
=== IGT changes ===
Possible regressions
igt@i915_selftest@live_coherency:
fi-skl-6770hq: PASS -> INCOMPLETE
fi-byt-n2820: PASS -> DMESG-FAIL
fi-skl-6700k2: PASS -> DMESG-FAIL
fi-skl-iommu: PASS -> INCOMPLETE
fi-skl-gvtdvm: PASS -> DMESG-FAIL
fi-hsw-peppy: PASS -> DMESG-FAIL
fi-kbl-x1275: PASS -> DMESG-FAIL
fi-bdw-gvtdvm: PASS -> DMESG-FAIL +1
fi-bwr-2160:PASS -> DMESG-FAIL
fi-skl-guc: PASS -> DMESG-FAIL
fi-snb-2520m: PASS -> DMESG-FAIL
fi-bxt-dsi: PASS -> DMESG-FAIL
fi-cfl-8700k: PASS -> DMESG-FAIL
fi-cfl-guc: PASS -> DMESG-FAIL
fi-glk-dsi: PASS -> DMESG-FAIL
fi-ivb-3770:PASS -> DMESG-FAIL
fi-skl-6700hq: PASS -> DMESG-FAIL
{fi-kbl-7500u}: PASS -> DMESG-FAIL
fi-hsw-4770r: PASS -> INCOMPLETE
fi-kbl-guc: PASS -> DMESG-FAIL
fi-bsw-kefka: PASS -> INCOMPLETE
{fi-kbl-7567u}: PASS -> DMESG-FAIL
fi-cfl-8109u: PASS -> DMESG-FAIL
fi-skl-6600u: PASS -> DMESG-FAIL
fi-byt-j1900: PASS -> DMESG-FAIL
igt@i915_selftest@live_contexts:
fi-bdw-5557u: PASS -> DMESG-FAIL
== Known issues ==
Here are the changes found in Patchwork_10889 that come from known issues:
=== IGT changes ===
Issues hit
igt@gem_ctx_create@basic-files:
fi-bsw-kefka: PASS -> FAIL (fdo#108656)
igt@gem_exec_suspend@basic-s3:
fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718)
igt@i915_selftest@live_coherency:
fi-bxt-j4205: PASS -> INCOMPLETE (fdo#103927)
igt@i915_selftest@live_contexts:
fi-glk-j4005: PASS -> DMESG-FAIL (fdo#107830)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-byt-clapper: PASS -> INCOMPLETE (fdo#102657)
Possible fixes
igt@i915_selftest@live_hangcheck:
fi-bwr-2160:DMESG-FAIL (fdo#108735) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#102657 https://bugs.freedesktop.org/show_bug.cgi?id=102657
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#107830 https://bugs.freedesktop.org/show_bug.cgi?id=107830
fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656
fdo#108735 https://bugs.freedesktop.org/show_bug.cgi?id=108735
== Participating hosts (51 -> 42) ==
Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-icl-u3 fi-icl-y fi-kbl-r
== Build changes ==
* Linux: CI_DRM_5191 -> Patchwork_10889
CI_DRM_5191: cdb3ce838d4020951ea12c11cf952c6f2419dd36 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4725: 9dc7c41d1c600133d6e3e63f1941c2e75d23bd3b @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10889: 3cce3ff72ec996821948088974af2db9cf7b0410 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3cce3ff72ec9 drm/i915: Avoid using MI_STORE_DWORD_IMM on vecs
344bf7277e31 drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency
309ac28a36a0 drm/i915/selftests: Flush the test object on creation
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10889/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/selftests: Flush the test object on creation (rev2)
== Series Details == Series: series starting with [1/3] drm/i915/selftests: Flush the test object on creation (rev2) URL : https://patchwork.freedesktop.org/series/52887/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/selftests: Flush the test object on creation Okay! Commit: drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency +drivers/gpu/drm/i915/selftests/i915_gem_coherency.c:826:33: warning: expression using sizeof(void) Commit: drm/i915: Avoid using MI_STORE_DWORD_IMM on vecs Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/selftests: Flush the test object on creation (rev2)
== Series Details ==
Series: series starting with [1/3] drm/i915/selftests: Flush the test object on
creation (rev2)
URL : https://patchwork.freedesktop.org/series/52887/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
309ac28a36a0 drm/i915/selftests: Flush the test object on creation
344bf7277e31 drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency
-:434: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#434: FILE: drivers/gpu/drm/i915/selftests/i915_gem_coherency.c:793:
+ obj = create_test_object(i915, npages,
+ file, );
-:446: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#446: FILE: drivers/gpu/drm/i915/selftests/i915_gem_coherency.c:805:
+ pr_err("Failed to fill dword %lu [%lu]
with gpu (%s), err=%d\n",
+ ndwords, dw,
engine->name, err);
-:461: WARNING:LONG_LINE: line over 100 characters
#461: FILE: drivers/gpu/drm/i915/selftests/i915_gem_coherency.c:820:
+ pr_info("Submitted %lu dwords (across %lu engines) in %lu
jiffies\n", ndwords, dw, timeout);
total: 0 errors, 1 warnings, 2 checks, 474 lines checked
3cce3ff72ec9 drm/i915: Avoid using MI_STORE_DWORD_IMM on vecs
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/atomic-helper: Complete fake_commit->flip_done potentially earlier
== Series Details ==
Series: series starting with [1/2] drm/atomic-helper: Complete
fake_commit->flip_done potentially earlier
URL : https://patchwork.freedesktop.org/series/52882/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5189_full -> Patchwork_10885_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the changes found in Patchwork_10885_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@gem_cpu_reloc@full:
shard-skl: PASS -> INCOMPLETE (fdo#108073)
igt@gem_ctx_isolation@vecs0-s3:
shard-skl: NOTRUN -> INCOMPLETE (fdo#104108, fdo#107773)
igt@gem_exec_schedule@pi-ringfull-bsd:
shard-skl: NOTRUN -> FAIL (fdo#103158)
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-skl: NOTRUN -> TIMEOUT (fdo#108039)
igt@gem_softpin@noreloc-s3:
shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#107773)
igt@gem_userptr_blits@readonly-unsync:
{shard-iclb}: PASS -> INCOMPLETE (fdo#108342)
igt@kms_chv_cursor_fail@pipe-a-128x128-left-edge:
shard-skl: PASS -> FAIL (fdo#104671)
igt@kms_chv_cursor_fail@pipe-c-64x64-right-edge:
shard-skl: NOTRUN -> FAIL (fdo#104671)
igt@kms_color@pipe-a-ctm-blue-to-red:
shard-kbl: PASS -> DMESG-WARN (fdo#103558, fdo#105602) +26
igt@kms_color@pipe-a-ctm-negative:
shard-skl: PASS -> FAIL (fdo#107361)
igt@kms_cursor_crc@cursor-128x42-random:
shard-glk: PASS -> FAIL (fdo#103232) +2
igt@kms_cursor_crc@cursor-256x256-random:
{shard-iclb}: NOTRUN -> FAIL (fdo#103232)
igt@kms_cursor_crc@cursor-256x256-sliding:
shard-skl: NOTRUN -> FAIL (fdo#103232)
igt@kms_cursor_crc@cursor-256x256-suspend:
shard-apl: PASS -> FAIL (fdo#103191, fdo#103232)
igt@kms_cursor_crc@cursor-64x21-random:
shard-apl: PASS -> FAIL (fdo#103232) +3
igt@kms_fbcon_fbt@psr-suspend:
shard-skl: NOTRUN -> FAIL (fdo#107882)
igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
shard-glk: PASS -> FAIL (fdo#105363)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
shard-apl: PASS -> FAIL (fdo#103167) +1
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
{shard-iclb}: PASS -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
shard-glk: PASS -> FAIL (fdo#103167) +4
igt@kms_frontbuffer_tracking@fbc-farfromfence:
shard-skl: NOTRUN -> FAIL (fdo#105682) +1
igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc:
shard-skl: PASS -> FAIL (fdo#105682)
igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
shard-skl: NOTRUN -> FAIL (fdo#103167) +2
igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render:
{shard-iclb}: NOTRUN -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc:
shard-skl: PASS -> FAIL (fdo#103167) +2
igt@kms_plane@pixel-format-pipe-b-planes:
shard-skl: NOTRUN -> DMESG-WARN (fdo#106885)
igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#108145)
igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
shard-skl: NOTRUN -> FAIL (fdo#108145) +1
igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
shard-skl: PASS -> FAIL (fdo#107815)
igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
shard-apl: PASS -> FAIL (fdo#103166)
igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#103166)
igt@kms_psr@no_drrs:
{shard-iclb}: PASS -> FAIL (fdo#108341)
igt@kms_rotation_crc@primary-rotation-180:
shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#103925)
igt@kms_setmode@basic:
shard-hsw: PASS -> FAIL (fdo#99912)
igt@pm_rpm@fences-dpms:
shard-skl: PASS -> INCOMPLETE (fdo#107807)
igt@pm_rps@waitboost:
shard-skl: PASS -> FAIL (fdo#102250)
Possible fixes
igt@gem_exec_schedule@preempt-hang-render:
shard-apl: INCOMPLETE (fdo#103927) -> PASS
igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
shard-glk: FAIL (fdo#108145) -> PASS
igt@kms_cursor_crc@cursor-128x128-suspend:
shard-glk: FAIL (fdo#103232) -> PASS +3
igt@kms_cursor_crc@cursor-256x256-random:
shard-apl: FAIL (fdo#103232) -> PASS +5
igt@kms_cursor_crc@cursor-64x64-suspend:
shard-apl: FAIL (fdo#103191, fdo#103232) -> PASS
igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
shard-glk: FAIL (fdo#106509, fdo#105454) -> PASS
[Intel-gfx] [PATCH v2] drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency
We use MI_STORE_DWORD_IMM internally (e.g. for gpu relocations) and so
require that its are writes flushed to memory on demand. Verify this with
a selftest.
v2: Use variable lengths of submission queues as the delay between
submit and checking is also crucially important for error detection.
Signed-off-by: Chris Wilson
---
.../drm/i915/selftests/i915_gem_coherency.c | 458 ++
1 file changed, 458 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
index f7392c1ffe75..6f87a65db2e6 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
@@ -26,6 +26,7 @@
#include "../i915_selftest.h"
#include "i915_random.h"
+#include "igt_flush_test.h"
static int cpu_set(struct drm_i915_gem_object *obj,
unsigned long offset,
@@ -386,10 +387,467 @@ static int igt_gem_coherency(void *arg)
goto unlock;
}
+#define DW_PER_PAGE (PAGE_SIZE / sizeof(u32))
+
+struct live_test {
+ struct drm_i915_private *i915;
+ const char *func;
+ const char *name;
+
+ unsigned int reset_global;
+ unsigned int reset_engine[I915_NUM_ENGINES];
+};
+
+static int begin_live_test(struct live_test *t,
+ struct drm_i915_private *i915,
+ const char *func,
+ const char *name)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err;
+
+ t->i915 = i915;
+ t->func = func;
+ t->name = name;
+
+ err = i915_gem_wait_for_idle(i915,
+I915_WAIT_LOCKED,
+MAX_SCHEDULE_TIMEOUT);
+ if (err) {
+ pr_err("%s(%s): failed to idle before, with err=%d!",
+ func, name, err);
+ return err;
+ }
+
+ i915->gpu_error.missed_irq_rings = 0;
+ t->reset_global = i915_reset_count(>gpu_error);
+
+ for_each_engine(engine, i915, id)
+ t->reset_engine[id] =
+ i915_reset_engine_count(>gpu_error, engine);
+
+ return 0;
+}
+
+static int end_live_test(struct live_test *t)
+{
+ struct drm_i915_private *i915 = t->i915;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ if (igt_flush_test(i915, I915_WAIT_LOCKED))
+ return -EIO;
+
+ if (t->reset_global != i915_reset_count(>gpu_error)) {
+ pr_err("%s(%s): GPU was reset %d times!\n",
+ t->func, t->name,
+ i915_reset_count(>gpu_error) - t->reset_global);
+ return -EIO;
+ }
+
+ for_each_engine(engine, i915, id) {
+ if (t->reset_engine[id] ==
+ i915_reset_engine_count(>gpu_error, engine))
+ continue;
+
+ pr_err("%s(%s): engine '%s' was reset %d times!\n",
+ t->func, t->name, engine->name,
+ i915_reset_engine_count(>gpu_error, engine) -
+ t->reset_engine[id]);
+ return -EIO;
+ }
+
+ if (i915->gpu_error.missed_irq_rings) {
+ pr_err("%s(%s): Missed interrupts on engines %lx\n",
+ t->func, t->name, i915->gpu_error.missed_irq_rings);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int cpu_fill(struct drm_i915_gem_object *obj, u32 value)
+{
+ const bool has_llc = HAS_LLC(to_i915(obj->base.dev));
+ unsigned int n, need_flush;
+ int err;
+
+ err = i915_gem_obj_prepare_shmem_write(obj, _flush);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; n++) {
+ u32 *map;
+
+ map = kmap_atomic(i915_gem_object_get_page(obj, n));
+ memset32(map, value, DW_PER_PAGE);
+ if (!has_llc)
+ drm_clflush_virt_range(map, PAGE_SIZE);
+ kunmap_atomic(map);
+ }
+
+ i915_gem_obj_finish_shmem_access(obj);
+ obj->read_domains = I915_GEM_DOMAIN_GTT | I915_GEM_DOMAIN_CPU;
+ obj->write_domain = 0;
+ return 0;
+}
+
+static int file_add_object(struct drm_file *file,
+ struct drm_i915_gem_object *obj)
+{
+ int err;
+
+ GEM_BUG_ON(obj->base.handle_count);
+
+ /* tie the object to the drm_file for easy reaping */
+ err = idr_alloc(>object_idr, >base, 1, 0, GFP_KERNEL);
+ if (err < 0)
+ return err;
+
+ i915_gem_object_get(obj);
+ obj->base.handle_count++;
+ return 0;
+}
+
+static struct drm_i915_gem_object *
+create_test_object(struct drm_i915_private *i915,
+ unsigned int num_pages,
+ struct drm_file *file,
+ struct list_head *objects)
+{
+ struct
Re: [Intel-gfx] [PATCH 2/3] mm, notifier: Catch sleeping/blocking for !blockable
Am 22.11.18 um 17:51 schrieb Daniel Vetter:
> We need to make sure implementations don't cheat and don't have a
> possible schedule/blocking point deeply burried where review can't
> catch it.
>
> I'm not sure whether this is the best way to make sure all the
> might_sleep() callsites trigger, and it's a bit ugly in the code flow.
> But it gets the job done.
>
> Cc: Andrew Morton
> Cc: Michal Hocko
> Cc: David Rientjes
> Cc: "Christian König"
> Cc: Daniel Vetter
> Cc: "Jérôme Glisse"
> Cc: linux...@kvack.org
> Signed-off-by: Daniel Vetter
> ---
> mm/mmu_notifier.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c
> index 59e102589a25..4d282cfb296e 100644
> --- a/mm/mmu_notifier.c
> +++ b/mm/mmu_notifier.c
> @@ -185,7 +185,13 @@ int __mmu_notifier_invalidate_range_start(struct
> mm_struct *mm,
> id = srcu_read_lock();
> hlist_for_each_entry_rcu(mn, >mmu_notifier_mm->list, hlist) {
> if (mn->ops->invalidate_range_start) {
> - int _ret = mn->ops->invalidate_range_start(mn, mm,
> start, end, blockable);
> + int _ret;
> +
> + if (IS_ENABLED(CONFIG_DEBUG_ATOMIC_SLEEP) && !blockable)
> + preempt_disable();
> + _ret = mn->ops->invalidate_range_start(mn, mm, start,
> end, blockable);
> + if (IS_ENABLED(CONFIG_DEBUG_ATOMIC_SLEEP) && !blockable)
> + preempt_enable();
Just for the sake of better documenting this how about adding this to
include/linux/kernel.h right next to might_sleep():
#define disallow_sleeping_if(cond) for((cond) ? preempt_disable() :
(void)0; (cond); preempt_disable())
(Just from the back of my head, might contain peanuts and/or hints of
errors).
Christian.
> if (_ret) {
> pr_info("%pS callback failed with %d in
> %sblockable context.\n",
>
> mn->ops->invalidate_range_start, _ret,
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Re: [Intel-gfx] [PATCH 1/3] mm: Check if mmu notifier callbacks are allowed to fail
Am 22.11.18 um 17:51 schrieb Daniel Vetter:
> Just a bit of paranoia, since if we start pushing this deep into
> callchains it's hard to spot all places where an mmu notifier
> implementation might fail when it's not allowed to.
>
> Cc: Andrew Morton
> Cc: Michal Hocko
> Cc: "Christian König"
> Cc: David Rientjes
> Cc: Daniel Vetter
> Cc: "Jérôme Glisse"
> Cc: linux...@kvack.org
> Cc: Paolo Bonzini
> Signed-off-by: Daniel Vetter
Acked-by: Christian König
> ---
> mm/mmu_notifier.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c
> index 5119ff846769..59e102589a25 100644
> --- a/mm/mmu_notifier.c
> +++ b/mm/mmu_notifier.c
> @@ -190,6 +190,8 @@ int __mmu_notifier_invalidate_range_start(struct
> mm_struct *mm,
> pr_info("%pS callback failed with %d in
> %sblockable context.\n",
>
> mn->ops->invalidate_range_start, _ret,
> !blockable ? "non-" : "");
> + WARN(blockable,"%pS callback failure not
> allowed\n",
> + mn->ops->invalidate_range_start);
> ret = _ret;
> }
> }
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[Intel-gfx] ✓ Fi.CI.BAT: success for RFC: mmu notifier debug checks
== Series Details == Series: RFC: mmu notifier debug checks URL : https://patchwork.freedesktop.org/series/52890/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5191 -> Patchwork_10888 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52890/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10888 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-icl-u2: PASS -> DMESG-WARN (fdo#107724) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) Possible fixes igt@gem_ctx_create@basic-files: fi-icl-u2: DMESG-WARN (fdo#107724) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724 == Participating hosts (51 -> 43) == Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-u3 fi-icl-y == Build changes == * Linux: CI_DRM_5191 -> Patchwork_10888 CI_DRM_5191: cdb3ce838d4020951ea12c11cf952c6f2419dd36 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4725: 9dc7c41d1c600133d6e3e63f1941c2e75d23bd3b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10888: ce8340ade10348ec9c52eded1b5383f5b18f6a6d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ce8340ade103 mm, notifier: Add a lockdep map for invalidate_range_start b4c01a0e0d06 mm, notifier: Catch sleeping/blocking for !blockable a2676e3168ac mm: Check if mmu notifier callbacks are allowed to fail == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10888/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for RFC: mmu notifier debug checks
== Series Details == Series: RFC: mmu notifier debug checks URL : https://patchwork.freedesktop.org/series/52890/ State : warning == Summary == $ dim checkpatch origin/drm-tip a2676e3168ac mm: Check if mmu notifier callbacks are allowed to fail -:31: ERROR:SPACING: space required after that ',' (ctx:VxV) #31: FILE: mm/mmu_notifier.c:193: + WARN(blockable,"%pS callback failure not allowed\n", ^ -:35: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter ' total: 1 errors, 1 warnings, 0 checks, 8 lines checked b4c01a0e0d06 mm, notifier: Catch sleeping/blocking for !blockable -:44: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 14 lines checked ce8340ade103 mm, notifier: Add a lockdep map for invalidate_range_start -:85: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 34 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/selftests: Flush the test object on creation
== Series Details ==
Series: series starting with [1/3] drm/i915/selftests: Flush the test object on
creation
URL : https://patchwork.freedesktop.org/series/52887/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5189 -> Patchwork_10887 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10887 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10887, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/52887/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10887:
=== IGT changes ===
Possible regressions
igt@i915_selftest@live_contexts:
fi-apl-guc: PASS -> DMESG-FAIL
== Known issues ==
Here are the changes found in Patchwork_10887 that come from known issues:
=== IGT changes ===
Issues hit
igt@gem_mmap_gtt@basic-small-bo-tiledx:
fi-glk-dsi: PASS -> INCOMPLETE (k.org#198133, fdo#103359)
igt@i915_selftest@live_contexts:
fi-glk-j4005: PASS -> DMESG-FAIL (fdo#107830)
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) +1
igt@pm_rpm@module-reload:
fi-skl-6770hq: PASS -> DMESG-WARN (fdo#105541)
{igt@runner@aborted}:
{fi-icl-y}: NOTRUN -> FAIL (fdo#108070)
Possible fixes
igt@i915_module_load@reload:
fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#105541 https://bugs.freedesktop.org/show_bug.cgi?id=105541
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#107830 https://bugs.freedesktop.org/show_bug.cgi?id=107830
fdo#108070 https://bugs.freedesktop.org/show_bug.cgi?id=108070
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (50 -> 44) ==
Additional (1): fi-icl-y
Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-icl-u3
== Build changes ==
* Linux: CI_DRM_5189 -> Patchwork_10887
CI_DRM_5189: 98966a91be483a9a681adc3a110877fe7ced049e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4725: 9dc7c41d1c600133d6e3e63f1941c2e75d23bd3b @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10887: 354c913304b1b0bdeb77bbe546880ff2e4a23142 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
354c913304b1 drm/i915: Avoid using MI_STORE_DWORD_IMM on vecs
5cda61eedcb1 drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency
3ca097048a16 drm/i915/selftests: Flush the test object on creation
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10887/issues.html
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/selftests: Flush the test object on creation
== Series Details == Series: series starting with [1/3] drm/i915/selftests: Flush the test object on creation URL : https://patchwork.freedesktop.org/series/52887/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/selftests: Flush the test object on creation Okay! Commit: drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency +drivers/gpu/drm/i915/selftests/i915_gem_coherency.c:823:25: warning: expression using sizeof(void) Commit: drm/i915: Avoid using MI_STORE_DWORD_IMM on vecs Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/selftests: Flush the test object on creation
== Series Details == Series: series starting with [1/3] drm/i915/selftests: Flush the test object on creation URL : https://patchwork.freedesktop.org/series/52887/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3ca097048a16 drm/i915/selftests: Flush the test object on creation 5cda61eedcb1 drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency -:388: WARNING:LINE_SPACING: Missing a blank line after declarations #388: FILE: drivers/gpu/drm/i915/selftests/i915_gem_coherency.c:750: + struct drm_file *file; + IGT_TIMEOUT(end_time); total: 0 errors, 1 warnings, 0 checks, 470 lines checked 354c913304b1 drm/i915: Avoid using MI_STORE_DWORD_IMM on vecs ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] mm: Check if mmu notifier callbacks are allowed to fail
Quoting Daniel Vetter (2018-11-22 16:51:04) > Just a bit of paranoia, since if we start pushing this deep into > callchains it's hard to spot all places where an mmu notifier > implementation might fail when it's not allowed to. Most callers could handle the failure correctly. It looks like the failure was not propagated for convenience. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] mm, notifier: Catch sleeping/blocking for !blockable
We need to make sure implementations don't cheat and don't have a
possible schedule/blocking point deeply burried where review can't
catch it.
I'm not sure whether this is the best way to make sure all the
might_sleep() callsites trigger, and it's a bit ugly in the code flow.
But it gets the job done.
Cc: Andrew Morton
Cc: Michal Hocko
Cc: David Rientjes
Cc: "Christian König"
Cc: Daniel Vetter
Cc: "Jérôme Glisse"
Cc: linux...@kvack.org
Signed-off-by: Daniel Vetter
---
mm/mmu_notifier.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c
index 59e102589a25..4d282cfb296e 100644
--- a/mm/mmu_notifier.c
+++ b/mm/mmu_notifier.c
@@ -185,7 +185,13 @@ int __mmu_notifier_invalidate_range_start(struct mm_struct
*mm,
id = srcu_read_lock();
hlist_for_each_entry_rcu(mn, >mmu_notifier_mm->list, hlist) {
if (mn->ops->invalidate_range_start) {
- int _ret = mn->ops->invalidate_range_start(mn, mm,
start, end, blockable);
+ int _ret;
+
+ if (IS_ENABLED(CONFIG_DEBUG_ATOMIC_SLEEP) && !blockable)
+ preempt_disable();
+ _ret = mn->ops->invalidate_range_start(mn, mm, start,
end, blockable);
+ if (IS_ENABLED(CONFIG_DEBUG_ATOMIC_SLEEP) && !blockable)
+ preempt_enable();
if (_ret) {
pr_info("%pS callback failed with %d in
%sblockable context.\n",
mn->ops->invalidate_range_start, _ret,
--
2.19.1
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[Intel-gfx] [PATCH 3/3] mm, notifier: Add a lockdep map for invalidate_range_start
This is a similar idea to the fs_reclaim fake lockdep lock. It's
fairly easy to provoke a specific notifier to be run on a specific
range: Just prep it, and then munmap() it.
A bit harder, but still doable, is to provoke the mmu notifiers for
all the various callchains that might lead to them. But both at the
same time is really hard to reliable hit, especially when you want to
exercise paths like direct reclaim or compaction, where it's not
easy to control what exactly will be unmapped.
By introducing a lockdep map to tie them all together we allow lockdep
to see a lot more dependencies, without having to actually hit them
in a single challchain while testing.
Aside: Since I typed this to test i915 mmu notifiers I've only rolled
this out for the invaliate_range_start callback. If there's
interest, we should probably roll this out to all of them. But my
undestanding of core mm is seriously lacking, and I'm not clear on
whether we need a lockdep map for each callback, or whether some can
be shared.
Cc: Andrew Morton
Cc: David Rientjes
Cc: "Jérôme Glisse"
Cc: Michal Hocko
Cc: "Christian König"
Cc: Greg Kroah-Hartman
Cc: Daniel Vetter
Cc: Mike Rapoport
Cc: linux...@kvack.org
Signed-off-by: Daniel Vetter
---
include/linux/mmu_notifier.h | 7 +++
mm/mmu_notifier.c| 7 +++
2 files changed, 14 insertions(+)
diff --git a/include/linux/mmu_notifier.h b/include/linux/mmu_notifier.h
index 9893a6432adf..a39ba218dbbe 100644
--- a/include/linux/mmu_notifier.h
+++ b/include/linux/mmu_notifier.h
@@ -12,6 +12,10 @@ struct mmu_notifier_ops;
#ifdef CONFIG_MMU_NOTIFIER
+#ifdef CONFIG_LOCKDEP
+extern struct lockdep_map __mmu_notifier_invalidate_range_start_map;
+#endif
+
/*
* The mmu notifier_mm structure is allocated and installed in
* mm->mmu_notifier_mm inside the mm_take_all_locks() protected
@@ -267,8 +271,11 @@ static inline void mmu_notifier_change_pte(struct
mm_struct *mm,
static inline void mmu_notifier_invalidate_range_start(struct mm_struct *mm,
unsigned long start, unsigned long end)
{
+ mutex_acquire(&__mmu_notifier_invalidate_range_start_map, 0, 0,
+ _RET_IP_);
if (mm_has_notifiers(mm))
__mmu_notifier_invalidate_range_start(mm, start, end, true);
+ mutex_release(&__mmu_notifier_invalidate_range_start_map, 1, _RET_IP_);
}
static inline int mmu_notifier_invalidate_range_start_nonblock(struct
mm_struct *mm,
diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c
index 4d282cfb296e..c6e797927376 100644
--- a/mm/mmu_notifier.c
+++ b/mm/mmu_notifier.c
@@ -23,6 +23,13 @@
/* global SRCU for all MMs */
DEFINE_STATIC_SRCU(srcu);
+#ifdef CONFIG_LOCKDEP
+struct lockdep_map __mmu_notifier_invalidate_range_start_map = {
+ .name = "mmu_notifier_invalidate_range_start"
+};
+EXPORT_SYMBOL_GPL(__mmu_notifier_invalidate_range_start_map);
+#endif
+
/*
* This function allows mmu_notifier::release callback to delay a call to
* a function that will free appropriate resources. The function must be
--
2.19.1
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[Intel-gfx] [PATCH 1/3] mm: Check if mmu notifier callbacks are allowed to fail
Just a bit of paranoia, since if we start pushing this deep into
callchains it's hard to spot all places where an mmu notifier
implementation might fail when it's not allowed to.
Cc: Andrew Morton
Cc: Michal Hocko
Cc: "Christian König"
Cc: David Rientjes
Cc: Daniel Vetter
Cc: "Jérôme Glisse"
Cc: linux...@kvack.org
Cc: Paolo Bonzini
Signed-off-by: Daniel Vetter
---
mm/mmu_notifier.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c
index 5119ff846769..59e102589a25 100644
--- a/mm/mmu_notifier.c
+++ b/mm/mmu_notifier.c
@@ -190,6 +190,8 @@ int __mmu_notifier_invalidate_range_start(struct mm_struct
*mm,
pr_info("%pS callback failed with %d in
%sblockable context.\n",
mn->ops->invalidate_range_start, _ret,
!blockable ? "non-" : "");
+ WARN(blockable,"%pS callback failure not
allowed\n",
+mn->ops->invalidate_range_start);
ret = _ret;
}
}
--
2.19.1
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[Intel-gfx] [PATCH 0/3] RFC: mmu notifier debug checks
Hi all, We're having some good fun with the i915 mmu notifier (it deadlocks), and I think it'd be very useful to have a bunch more runtime debug checks to catch screw-ups. I'm also working on some lockdep improvements in gpu code (better annotations and stuff like that). Together with this series here this seems to catch a lot of bugs pretty much instantly, which previously took hours/days of CI workloads to reproduce. Plus now you get nice backtraces and the kernel keeps working, whereas without this it's real deadlocks with piles of stuck processes (the deadlock needed at least 3 processes, but generally it took more to close the loop, plus everyone piling in on top). If this looks like a good idea I'm happy to polish it for merging. Thanks, Daniel Daniel Vetter (3): mm: Check if mmu notifier callbacks are allowed to fail mm, notifier: Catch sleeping/blocking for !blockable mm, notifier: Add a lockdep map for invalidate_range_start include/linux/mmu_notifier.h | 7 +++ mm/mmu_notifier.c| 17 - 2 files changed, 23 insertions(+), 1 deletion(-) -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915: Avoid using MI_STORE_DWORD_IMM on vecs
It turns out that our MI_FLUSH_DW we perform after each batch is not sufficient to flush MI_STORE_DWORD_IMM to memory. Of course, this raises the concern that MI_FLUSH_DW may not be flushing anything on vecs, but for the moment we have to neuter our own use of store-dw. I have tried: 8x MI_FLUSH_DW (with post-op sync) 8x MI_STORE_DWORD_IMM 8x MI_STORE_REG_MEM + MI_LOAD_REG_MEM with no lasting effect; they only appear to add some extra delay on the flush which partially masks the issue but not solve it. Testcase: igt/i915_selftest/live_coherency Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala --- drivers/gpu/drm/i915/intel_engine_cs.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 759c0fd58f8c..117667cfbda1 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1195,10 +1195,14 @@ bool intel_engine_can_store_dword(struct intel_engine_cs *engine) case 3: /* maybe only uses physical not virtual addresses */ return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915)); + case 4: + case 5: + /* no known limitations */ + return true; case 6: return engine->class != VIDEO_DECODE_CLASS; /* b0rked */ default: - return true; + return engine->class != VIDEO_ENHANCEMENT_CLASS;/* incoherent */ } } -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency
We use MI_STORE_DWORD_IMM internally (e.g. for gpu relocations) and so
require that its are writes flushed to memory on demand. Verify this with
a selftest.
Signed-off-by: Chris Wilson
---
.../drm/i915/selftests/i915_gem_coherency.c | 454 ++
1 file changed, 454 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
index f7392c1ffe75..c6ed9f67f91f 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
@@ -26,6 +26,7 @@
#include "../i915_selftest.h"
#include "i915_random.h"
+#include "igt_flush_test.h"
static int cpu_set(struct drm_i915_gem_object *obj,
unsigned long offset,
@@ -386,10 +387,463 @@ static int igt_gem_coherency(void *arg)
goto unlock;
}
+#define DW_PER_PAGE (PAGE_SIZE / sizeof(u32))
+
+struct live_test {
+ struct drm_i915_private *i915;
+ const char *func;
+ const char *name;
+
+ unsigned int reset_global;
+ unsigned int reset_engine[I915_NUM_ENGINES];
+};
+
+static int begin_live_test(struct live_test *t,
+ struct drm_i915_private *i915,
+ const char *func,
+ const char *name)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err;
+
+ t->i915 = i915;
+ t->func = func;
+ t->name = name;
+
+ err = i915_gem_wait_for_idle(i915,
+I915_WAIT_LOCKED,
+MAX_SCHEDULE_TIMEOUT);
+ if (err) {
+ pr_err("%s(%s): failed to idle before, with err=%d!",
+ func, name, err);
+ return err;
+ }
+
+ i915->gpu_error.missed_irq_rings = 0;
+ t->reset_global = i915_reset_count(>gpu_error);
+
+ for_each_engine(engine, i915, id)
+ t->reset_engine[id] =
+ i915_reset_engine_count(>gpu_error, engine);
+
+ return 0;
+}
+
+static int end_live_test(struct live_test *t)
+{
+ struct drm_i915_private *i915 = t->i915;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ if (igt_flush_test(i915, I915_WAIT_LOCKED))
+ return -EIO;
+
+ if (t->reset_global != i915_reset_count(>gpu_error)) {
+ pr_err("%s(%s): GPU was reset %d times!\n",
+ t->func, t->name,
+ i915_reset_count(>gpu_error) - t->reset_global);
+ return -EIO;
+ }
+
+ for_each_engine(engine, i915, id) {
+ if (t->reset_engine[id] ==
+ i915_reset_engine_count(>gpu_error, engine))
+ continue;
+
+ pr_err("%s(%s): engine '%s' was reset %d times!\n",
+ t->func, t->name, engine->name,
+ i915_reset_engine_count(>gpu_error, engine) -
+ t->reset_engine[id]);
+ return -EIO;
+ }
+
+ if (i915->gpu_error.missed_irq_rings) {
+ pr_err("%s(%s): Missed interrupts on engines %lx\n",
+ t->func, t->name, i915->gpu_error.missed_irq_rings);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int cpu_fill(struct drm_i915_gem_object *obj, u32 value)
+{
+ const bool has_llc = HAS_LLC(to_i915(obj->base.dev));
+ unsigned int n, need_flush;
+ int err;
+
+ err = i915_gem_obj_prepare_shmem_write(obj, _flush);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; n++) {
+ u32 *map;
+
+ map = kmap_atomic(i915_gem_object_get_page(obj, n));
+ memset32(map, value, DW_PER_PAGE);
+ if (!has_llc)
+ drm_clflush_virt_range(map, PAGE_SIZE);
+ kunmap_atomic(map);
+ }
+
+ i915_gem_obj_finish_shmem_access(obj);
+ obj->read_domains = I915_GEM_DOMAIN_GTT | I915_GEM_DOMAIN_CPU;
+ obj->write_domain = 0;
+ return 0;
+}
+
+static int file_add_object(struct drm_file *file,
+ struct drm_i915_gem_object *obj)
+{
+ int err;
+
+ GEM_BUG_ON(obj->base.handle_count);
+
+ /* tie the object to the drm_file for easy reaping */
+ err = idr_alloc(>object_idr, >base, 1, 0, GFP_KERNEL);
+ if (err < 0)
+ return err;
+
+ i915_gem_object_get(obj);
+ obj->base.handle_count++;
+ return 0;
+}
+
+static struct drm_i915_gem_object *
+create_test_object(struct drm_i915_private *i915,
+ unsigned int num_pages,
+ struct drm_file *file,
+ struct list_head *objects)
+{
+ struct drm_i915_gem_object *obj;
+ int err;
+
+ obj = i915_gem_object_create_internal(i915, num_pages << PAGE_SHIFT);
+ if (IS_ERR(obj))
+
[Intel-gfx] [PATCH 1/3] drm/i915/selftests: Flush the test object on creation
Move the flush from before emitting the gpu_fill request to the object's
creation to avoid forcing a stall on each write. The only stall should
now be after all the writes have been queued and we want to read the
results.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/selftests/i915_gem_context.c | 23 ++-
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 7d82043aff10..625762de7743 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -347,15 +347,12 @@ static int gpu_fill(struct drm_i915_gem_object *obj,
if (IS_ERR(vma))
return PTR_ERR(vma);
- err = i915_gem_object_set_to_gtt_domain(obj, false);
- if (err)
- return err;
-
err = i915_vma_pin(vma, 0, 0, PIN_HIGH | PIN_USER);
if (err)
return err;
- /* Within the GTT the huge objects maps every page onto
+ /*
+* Within the GTT the huge objects maps every page onto
* its 1024 real pages (using phys_pfn = dma_pfn % 1024).
* We set the nth dword within the page using the nth
* mapping via the GTT - this should exercise the GTT mapping
@@ -396,14 +393,15 @@ static int gpu_fill(struct drm_i915_gem_object *obj,
if (err)
goto skip_request;
+ i915_gem_chipset_flush(vm->i915);
+ i915_request_add(rq);
+
i915_gem_object_set_active_reference(batch->obj);
i915_vma_unpin(batch);
i915_vma_close(batch);
i915_vma_unpin(vma);
- i915_request_add(rq);
-
return 0;
skip_request:
@@ -531,11 +529,14 @@ create_test_object(struct i915_gem_context *ctx,
err = cpu_fill(obj, STACK_MAGIC);
if (err) {
- pr_err("Failed to fill object with cpu, err=%d\n",
- err);
+ pr_err("Failed to fill object with cpu, err=%d\n", err);
return ERR_PTR(err);
}
+ err = i915_gem_object_set_to_gtt_domain(obj, false);
+ if (err)
+ return ERR_PTR(err);
+
list_add_tail(>st_link, objects);
return obj;
}
@@ -843,11 +844,11 @@ static int write_to_scratch(struct i915_gem_context *ctx,
goto skip_request;
i915_gem_object_set_active_reference(obj);
+ i915_request_add(rq);
+
i915_vma_unpin(vma);
i915_vma_close(vma);
- i915_request_add(rq);
-
return 0;
skip_request:
--
2.19.1
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/13] locking/lockdep: restore cross-release checks (rev4)
== Series Details ==
Series: series starting with [01/13] locking/lockdep: restore cross-release
checks (rev4)
URL : https://patchwork.freedesktop.org/series/52167/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
CC kernel/locking/lockdep.o
kernel/locking/lockdep.c: In function ‘add_xhlock’:
kernel/locking/lockdep.c:4849:19: error: ‘trace’ undeclared (first use in this
function); did you mean ‘tracer’?
for (i = 0; i < trace->nr_entries; i++) {
^
tracer
kernel/locking/lockdep.c:4849:19: note: each undeclared identifier is reported
only once for each function it appears in
scripts/Makefile.build:293: recipe for target 'kernel/locking/lockdep.o' failed
make[2]: *** [kernel/locking/lockdep.o] Error 1
scripts/Makefile.build:518: recipe for target 'kernel/locking' failed
make[1]: *** [kernel/locking] Error 2
Makefile:1060: recipe for target 'kernel' failed
make: *** [kernel] Error 2
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[Intel-gfx] [PATCH] HAX FOR CI: Enable cross-release
Only way to convince our CI to enable stuff that's new and defaulting
to off. Obviously not for merging.
v2: Also enable fullstack backtraces.
v3: Try to chase this elusive stack trace corruption CI is seeing.
Signed-off-by: Daniel Vetter
---
kernel/locking/lockdep.c | 13 +
lib/Kconfig.debug| 3 ++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/kernel/locking/lockdep.c b/kernel/locking/lockdep.c
index e74add63f317..d8937d05acc4 100644
--- a/kernel/locking/lockdep.c
+++ b/kernel/locking/lockdep.c
@@ -4841,8 +4841,15 @@ static void add_xhlock(struct held_lock *hlock)
xhlock->trace.entries = xhlock->trace_entries;
if (crossrelease_fullstack) {
+ int i;
+
xhlock->trace.skip = 3;
save_stack_trace(>trace);
+
+ for (i = 0; i < trace->nr_entries; i++) {
+ if (trace->entries[i] == 0x6b6b6b6b6b6b6b6bUL)
+ print_lockdep_off("BUG: list poison in
add_xlock!");
+ }
} else {
xhlock->trace.nr_entries = 1;
xhlock->trace.entries[0] = hlock->acquire_ip;
@@ -4950,12 +4957,18 @@ static int copy_trace(struct stack_trace *trace)
unsigned long *buf = stack_trace + nr_stack_trace_entries;
unsigned int max_nr = MAX_STACK_TRACE_ENTRIES - nr_stack_trace_entries;
unsigned int nr = min(max_nr, trace->nr_entries);
+ int i;
trace->nr_entries = nr;
memcpy(buf, trace->entries, nr * sizeof(trace->entries[0]));
trace->entries = buf;
nr_stack_trace_entries += nr;
+ for (i = 0; i < trace->nr_entries; i++) {
+ if (trace->entries[i] == 0x6b6b6b6b6b6b6b6bUL)
+ print_lockdep_off("BUG: list poison in copy_trace!");
+ }
+
if (nr_stack_trace_entries >= MAX_STACK_TRACE_ENTRIES-1) {
if (!debug_locks_off_graph_unlock())
return 0;
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index 6074fa3463ac..8e1c30e3face 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -1095,6 +1095,7 @@ config LOCKDEP_CROSSRELEASE
bool "Enable cross-release checking"
depends on PROVE_LOCKING
select LOCKDEP_COMPLETIONS
+ default y
help
This makes lockdep work for crosslock which is a lock allowed to
be released in a different context from the acquisition context.
@@ -1208,7 +1209,7 @@ config LOCKDEP_COMPLETIONS
config BOOTPARAM_LOCKDEP_CROSSRELEASE_FULLSTACK
bool "Enable the boot parameter, crossrelease_fullstack"
depends on LOCKDEP_CROSSRELEASE
- default n
+ default y
help
The lockdep "cross-release" feature needs to record stack traces
(of calling functions) for all acquisitions, for eventual later
--
2.19.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/atomic-helper: Complete fake_commit->flip_done potentially earlier
== Series Details ==
Series: series starting with [1/2] drm/atomic-helper: Complete
fake_commit->flip_done potentially earlier
URL : https://patchwork.freedesktop.org/series/52882/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5189 -> Patchwork_10885 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/52882/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10885 that come from known issues:
=== IGT changes ===
Issues hit
igt@gem_ctx_create@basic-files:
fi-bsw-n3050: PASS -> FAIL (fdo#108656)
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: PASS -> DMESG-WARN (fdo#102614)
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362)
igt@pm_rpm@module-reload:
fi-skl-6600u: PASS -> INCOMPLETE (fdo#107807)
{igt@runner@aborted}:
{fi-icl-y}: NOTRUN -> FAIL (fdo#108070)
Possible fixes
igt@i915_module_load@reload:
fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS
igt@i915_selftest@live_coherency:
fi-gdg-551: DMESG-FAIL (fdo#107164) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
fdo#108070 https://bugs.freedesktop.org/show_bug.cgi?id=108070
fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656
== Participating hosts (50 -> 44) ==
Additional (1): fi-icl-y
Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-icl-u3
== Build changes ==
* Linux: CI_DRM_5189 -> Patchwork_10885
CI_DRM_5189: 98966a91be483a9a681adc3a110877fe7ced049e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4725: 9dc7c41d1c600133d6e3e63f1941c2e75d23bd3b @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10885: b67b3a1e1d92c9a6198b2e4756432822c86ab6c9 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b67b3a1e1d92 drm/atomic-helper: WARN if fake_commit->hw_done is not completed
as expected
384656c5015e drm/atomic-helper: Complete fake_commit->flip_done potentially
earlier
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10885/issues.html
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[Intel-gfx] Updated drm-intel-testing
Hi all, It may be about time we update the process around drm-intel-testing, but here goes anyway... The following changes tagged drm-intel-testing-2018-11-22: drm-intel-next-2018-11-22: Changes outside i915: - Connector property to limit max bpc (Radhakrishna) - Fix LPE audio runtime PM and deinit (Ville) - DP FEC prep work (Anusha) - Mark pinned shmemfs pages as unevictable (Kuo-Hsin) - Backmerge drm-next (Jani) Inside i915: - Revert OA UAPI change that lacks userspace (Joonas) - Register macro cleanup (Jani) - 32-bit build fixes on pin flags (Chris) - Fix MG DP mode and PHY gating for HDMI (Imre) - DP MST race, hpd and irq fixes (Lyude) - Combo PHY fixes and cleanup (Imre, Lucas) - Move display init and cleanup under modeset init and cleanup (José) - PSR fixes (José) - Subslice size fixes (Daniele) - Abstract and clean up fixed point helpers (Jani) - Plane input CSC for YUV to RGB conversion (Uma) - Break long iterations for get/put shmemfs pages (Chris) - Improve DDI encoder hw state readout sanity checks (Imre) - Fix power well leaks for MST (José) - Scaler fixes (Ville) - Watermark fixes (Ville) - Fix VLV/CHV DSI panel orientation readout (Ville) - ICL rawclock fixes (Paulo) - Workaround DMC power well request issues (Imre) - Plane allocation fix (Maarten) - Transcoder enum value/ordering robustness fixes (Imre) - UTS_RELEASE build dependency fix (Hans Holmberg) BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/atomic-helper: Complete fake_commit->flip_done potentially earlier
Op 22-11-18 om 15:34 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> Consider the following scenario:
> 1. nonblocking enable crtc
> 2. wait for the event
> 3. nonblocking disable crtc
>
> On i915 this can lead to a spurious -EBUSY from step 3 on
> account of non-enabled planes getting the fake_commit in step 1
> and we don't complete the fake_commit-> flip_done until
> drm_atomic_helper_commit_hw_done() which can happen a long
> time after the flip event was sent out.
>
> This will become somewhat easy to hit on SKL+ once we start
> to add all the planes for the crtc to every modeset commit
> for the purposes of forcing a watermark register programming
> [1].
>
> To make the race a little less pronounced let's complete
> fake_commit->flip_done after drm_atomic_helper_wait_for_flip_done().
> For the single crtc case this should make the race quite
> theoretical, assuming drm_atomic_helper_wait_for_flip_done()
> actually has to wait for the real commit flip_done. In case
> the real commit flip_done gets completed singificantly before
> drm_atomic_helper_wait_for_flip_done(), or we are dealing with
> multiple crtcs whose vblanks don't line up nicely the race still
> exists.
>
> [1] https://patchwork.freedesktop.org/patch/262670/
>
> Cc: Maarten Lankhorst
> Fixes: 080de2e5be2d ("drm/atomic: Check for busy planes/connectors before
> setting the commit")
> Testcase: igt/kms_cursor_legacy/*nonblocking-modeset-vs-cursor-atomic
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_atomic_helper.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> b/drivers/gpu/drm/drm_atomic_helper.c
> index fa95f9974f6d..47398662b895 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -1460,6 +1460,9 @@ void drm_atomic_helper_wait_for_flip_done(struct
> drm_device *dev,
> DRM_ERROR("[CRTC:%d:%s] flip_done timed out\n",
> crtc->base.id, crtc->name);
> }
> +
> + if (old_state->fake_commit)
> + complete_all(_state->fake_commit->flip_done);
> }
> EXPORT_SYMBOL(drm_atomic_helper_wait_for_flip_done);
>
Yeah as long as we don't enable hw_done sooner, this should be fine.
For both patches:
Reviewed-by: Maarten Lankhorst
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[Intel-gfx] [PATCH 1/2] drm/atomic-helper: Complete fake_commit->flip_done potentially earlier
From: Ville Syrjälä
Consider the following scenario:
1. nonblocking enable crtc
2. wait for the event
3. nonblocking disable crtc
On i915 this can lead to a spurious -EBUSY from step 3 on
account of non-enabled planes getting the fake_commit in step 1
and we don't complete the fake_commit-> flip_done until
drm_atomic_helper_commit_hw_done() which can happen a long
time after the flip event was sent out.
This will become somewhat easy to hit on SKL+ once we start
to add all the planes for the crtc to every modeset commit
for the purposes of forcing a watermark register programming
[1].
To make the race a little less pronounced let's complete
fake_commit->flip_done after drm_atomic_helper_wait_for_flip_done().
For the single crtc case this should make the race quite
theoretical, assuming drm_atomic_helper_wait_for_flip_done()
actually has to wait for the real commit flip_done. In case
the real commit flip_done gets completed singificantly before
drm_atomic_helper_wait_for_flip_done(), or we are dealing with
multiple crtcs whose vblanks don't line up nicely the race still
exists.
[1] https://patchwork.freedesktop.org/patch/262670/
Cc: Maarten Lankhorst
Fixes: 080de2e5be2d ("drm/atomic: Check for busy planes/connectors before
setting the commit")
Testcase: igt/kms_cursor_legacy/*nonblocking-modeset-vs-cursor-atomic
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index fa95f9974f6d..47398662b895 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1460,6 +1460,9 @@ void drm_atomic_helper_wait_for_flip_done(struct
drm_device *dev,
DRM_ERROR("[CRTC:%d:%s] flip_done timed out\n",
crtc->base.id, crtc->name);
}
+
+ if (old_state->fake_commit)
+ complete_all(_state->fake_commit->flip_done);
}
EXPORT_SYMBOL(drm_atomic_helper_wait_for_flip_done);
--
2.18.1
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[Intel-gfx] [PATCH 2/2] drm/atomic-helper: WARN if fake_commit->hw_done is not completed as expected
From: Ville Syrjälä
For real commits we WARN if ->hw_done hasn't been completed by the time
drm_atomic_helper_commit_cleanup_done() is called. Let's do the same for
the fake commit.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic_helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index 47398662b895..bc9fc9665614 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -2220,8 +2220,10 @@ void drm_atomic_helper_commit_cleanup_done(struct
drm_atomic_state *old_state)
spin_unlock(>commit_lock);
}
- if (old_state->fake_commit)
+ if (old_state->fake_commit) {
complete_all(_state->fake_commit->cleanup_done);
+
WARN_ON(!try_wait_for_completion(_state->fake_commit->hw_done));
+ }
}
EXPORT_SYMBOL(drm_atomic_helper_commit_cleanup_done);
--
2.18.1
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Re: [Intel-gfx] [PATCH 2/2] gpu/i915: use HMM mirror for userptr buffer object.
On Thu, Nov 22, 2018 at 03:59:50PM +0200, Joonas Lahtinen wrote: > Hi Jerome, > > Bit late reply, but here goes :) > > We're working quite hard to avoid pinning any pages unless they're in > the GPU page tables. And when they are in the GPU page tables, they must > be pinned for whole of that duration, for the reason that our GPUs can > not take a fault. And to avoid thrashing GPU page tables, we do leave > objects in page tables with the expectation that smart userspace > recycles buffers. > > So what I understand of your proposal, it wouldn't really make a > difference for us in the amount of pinned pages (which I agree, > we'd love to see going down). When we're unable to take a fault, > the first use effectively forces us to pin any pages and keep them > pinned to avoid thrashing GPU page tables. > > So from i915 perspective, it just seems to be mostly an exchange of > an API to an another for getting the pages. You already mentioned > the fast path is being worked on, which is an obvious difference. > But is there some other improvement one would be expecting, beyond > the page pinning? > > Also, is the requirement for a single non-file-backed VMA in the > plans of being eliminated or is that inherent restriction of the > HMM_MIRROR feature? We're currently not imposing such a limitation. I think a clear plus for HMM would be if this helps us fix the deadlocks and races we're seeing. But I have no idea whether this gets us any closer here or not. -Daniel > > Regards, Joonas > > Quoting jgli...@redhat.com (2018-09-10 03:57:36) > > From: Jérôme Glisse > > > > This replace existing code that rely on get_user_page() aka GUP with > > code that now use HMM mirror to mirror a range of virtual address as > > a buffer object accessible by the GPU. There is no functional changes > > from userspace point of view. > > > > From kernel point of view we no longer pin pages for userptr buffer > > object which is a welcome change (i am assuming that everyone dislike > > page pin as i do). > > > > Another change, from kernel point of view, is that it does no longer > > have a fast path with get_user_pages_fast() this can eventually added > > back through HMM. > > > > Signed-off-by: Jérôme Glisse > > Cc: dri-de...@lists.freedesktop.org > > Cc: David Airlie > > Cc: Daniel Vetter > > Cc: Chris Wilson > > Cc: Lionel Landwerlin > > Cc: Jani Nikula > > Cc: Joonas Lahtinen > > Cc: Rodrigo Vivi > > Cc: intel-gfx@lists.freedesktop.org -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] gpu/i915: use HMM mirror for userptr buffer object.
Hi Jerome, Bit late reply, but here goes :) We're working quite hard to avoid pinning any pages unless they're in the GPU page tables. And when they are in the GPU page tables, they must be pinned for whole of that duration, for the reason that our GPUs can not take a fault. And to avoid thrashing GPU page tables, we do leave objects in page tables with the expectation that smart userspace recycles buffers. So what I understand of your proposal, it wouldn't really make a difference for us in the amount of pinned pages (which I agree, we'd love to see going down). When we're unable to take a fault, the first use effectively forces us to pin any pages and keep them pinned to avoid thrashing GPU page tables. So from i915 perspective, it just seems to be mostly an exchange of an API to an another for getting the pages. You already mentioned the fast path is being worked on, which is an obvious difference. But is there some other improvement one would be expecting, beyond the page pinning? Also, is the requirement for a single non-file-backed VMA in the plans of being eliminated or is that inherent restriction of the HMM_MIRROR feature? We're currently not imposing such a limitation. Regards, Joonas Quoting jgli...@redhat.com (2018-09-10 03:57:36) > From: Jérôme Glisse > > This replace existing code that rely on get_user_page() aka GUP with > code that now use HMM mirror to mirror a range of virtual address as > a buffer object accessible by the GPU. There is no functional changes > from userspace point of view. > > From kernel point of view we no longer pin pages for userptr buffer > object which is a welcome change (i am assuming that everyone dislike > page pin as i do). > > Another change, from kernel point of view, is that it does no longer > have a fast path with get_user_pages_fast() this can eventually added > back through HMM. > > Signed-off-by: Jérôme Glisse > Cc: dri-de...@lists.freedesktop.org > Cc: David Airlie > Cc: Daniel Vetter > Cc: Chris Wilson > Cc: Lionel Landwerlin > Cc: Jani Nikula > Cc: Joonas Lahtinen > Cc: Rodrigo Vivi > Cc: intel-gfx@lists.freedesktop.org ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [bug report] i915/dp/fec: Cache the FEC_CAPABLE DPCD register
Hello Anusha Srivatsa,
The patch 08cadae8e157: "i915/dp/fec: Cache the FEC_CAPABLE DPCD
register" from Nov 1, 2018, leads to the following static checker
warning:
drivers/gpu/drm/i915/intel_dp.c:3846 intel_dp_get_dsc_sink_cap()
warn: inconsistent indenting
drivers/gpu/drm/i915/intel_dp.c
3817 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
3818 {
3819 /*
3820 * Clear the cached register set to avoid using stale values
3821 * for the sinks that do not support DSC.
3822 */
3823 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
3824
3825 /* Clear fec_capable to avoid using stale values */
3826 intel_dp->fec_capable = 0;
3827
3828 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
3829 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
3830 intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3831 if (drm_dp_dpcd_read(_dp->aux, DP_DSC_SUPPORT,
3832 intel_dp->dsc_dpcd,
3833 sizeof(intel_dp->dsc_dpcd)) < 0)
3834 DRM_ERROR("Failed to read DPCD register 0x%x\n",
3835DP_DSC_SUPPORT);
3836
3837 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
3838(int)sizeof(intel_dp->dsc_dpcd),
3839intel_dp->dsc_dpcd);
3840 /* FEC is supported only on DP 1.4 */
3841 if (!intel_dp_is_edp(intel_dp)) {
3842 if (drm_dp_dpcd_readb(_dp->aux,
DP_FEC_CAPABILITY,
3843_dp->fec_capable) <
0)
3844 DRM_ERROR("Failed to read FEC DPCD
register\n");
3845
3846 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n",
3847intel_dp->fec_capable);
Probably this was suppose to be outside the braces? It's hard to say...
3848 }
3849 }
3850 }
regards,
dan carpenter
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/selftests: Flush the test object on creation
Quoting Patchwork (2018-11-22 12:42:24) > == Series Details == > > Series: series starting with [1/3] drm/i915/selftests: Flush the test object > on creation > URL : https://patchwork.freedesktop.org/series/52875/ > State : failure > > == Summary == > > = CI Bug Log - changes from CI_DRM_5186 -> Patchwork_10884 = > > == Summary - FAILURE == > > Serious unknown changes coming with Patchwork_10884 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_10884, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: > https://patchwork.freedesktop.org/api/1.0/series/52875/revisions/1/mbox/ > > == Possible new issues == > > Here are the unknown changes that may have been introduced in > Patchwork_10884: > > === IGT changes === > > Possible regressions > > igt@i915_selftest@live_contexts: > fi-bdw-5557u: PASS -> DMESG-FAIL > fi-skl-gvtdvm: PASS -> DMESG-FAIL > fi-skl-iommu: PASS -> DMESG-FAIL Of course you work for trybot and fail in public. Traitors. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/selftests: Flush the test object on creation
== Series Details ==
Series: series starting with [1/3] drm/i915/selftests: Flush the test object on
creation
URL : https://patchwork.freedesktop.org/series/52875/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5186 -> Patchwork_10884 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10884 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10884, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/52875/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10884:
=== IGT changes ===
Possible regressions
igt@gem_basic@bad-close:
fi-kbl-7560u: PASS -> INCOMPLETE
igt@i915_selftest@live_contexts:
fi-bdw-5557u: PASS -> DMESG-FAIL
fi-skl-gvtdvm: PASS -> DMESG-FAIL
fi-skl-iommu: PASS -> DMESG-FAIL
== Known issues ==
Here are the changes found in Patchwork_10884 that come from known issues:
=== IGT changes ===
Issues hit
igt@i915_module_load@reload-no-display:
{fi-kbl-7567u}: PASS -> DMESG-WARN (fdo#105602, fdo#103558) +1
igt@i915_module_load@reload-with-fault-injection:
{fi-kbl-7567u}: PASS -> DMESG-WARN (fdo#105602)
igt@i915_selftest@live_contexts:
fi-glk-j4005: PASS -> DMESG-FAIL (fdo#107830)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) +1
igt@pm_rpm@module-reload:
fi-skl-6770hq: PASS -> DMESG-WARN (fdo#105541)
{igt@runner@aborted}:
{fi-kbl-7567u}: NOTRUN -> FAIL (fdo#105602)
Possible fixes
igt@gem_ctx_create@basic-files:
fi-bsw-n3050: FAIL (fdo#108656) -> PASS
igt@gem_exec_suspend@basic-s3:
fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS
igt@gem_mmap@basic-small-bo:
fi-glk-dsi: INCOMPLETE (k.org#198133, fdo#103359) -> PASS
igt@kms_pipe_crc_basic@hang-read-crc-pipe-b:
fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS +1
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
fdo#105541 https://bugs.freedesktop.org/show_bug.cgi?id=105541
fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#107830 https://bugs.freedesktop.org/show_bug.cgi?id=107830
fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (51 -> 42) ==
Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-apl-guc fi-ctg-p8600 fi-icl-u3 fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_5186 -> Patchwork_10884
CI_DRM_5186: 890ed44fe2612f8bf15ca1b33610d30ff57ce7d9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4725: 9dc7c41d1c600133d6e3e63f1941c2e75d23bd3b @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10884: 678b25d4536dbb64c9c6779f7bc6075bbdfa6115 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
678b25d4536d drm/i915: Avoid using MI_STORE_DWORD_IMM on vecs
920e0aa2f1c1 drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency
5e991e45460d drm/i915/selftests: Flush the test object on creation
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10884/issues.html
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/selftests: Flush the test object on creation
== Series Details == Series: series starting with [1/3] drm/i915/selftests: Flush the test object on creation URL : https://patchwork.freedesktop.org/series/52875/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/selftests: Flush the test object on creation Okay! Commit: drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency +drivers/gpu/drm/i915/selftests/i915_gem_coherency.c:823:25: warning: expression using sizeof(void) Commit: drm/i915: Avoid using MI_STORE_DWORD_IMM on vecs Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/selftests: Flush the test object on creation
== Series Details == Series: series starting with [1/3] drm/i915/selftests: Flush the test object on creation URL : https://patchwork.freedesktop.org/series/52875/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5e991e45460d drm/i915/selftests: Flush the test object on creation 920e0aa2f1c1 drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency -:388: WARNING:LINE_SPACING: Missing a blank line after declarations #388: FILE: drivers/gpu/drm/i915/selftests/i915_gem_coherency.c:750: + struct drm_file *file; + IGT_TIMEOUT(end_time); total: 0 errors, 1 warnings, 0 checks, 470 lines checked 678b25d4536d drm/i915: Avoid using MI_STORE_DWORD_IMM on vecs ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915: Avoid using MI_STORE_DWORD_IMM on vecs
It runs out that our MI_FLUSH_DW we perform after each batch is not sufficient to flush MI_STORE_DWORD_IMM to memory. Of course, this raises the concern that MI_FLUSH_DW may not be flushing anything on vecs, but for the moment we have to neuter our own use of store-dw. I have tried: 8x MI_FLUSH_DW (with post-op sync) 8x MI_STORE_DWORD_IMM 8x MI_STORE_REG_MEM + MI_LOAD_REG_MEM with no lasting effect; they only appear to add some extra delay on the flush which partially masks the issue but not solve it. Testcase: igt/i915_selftest/live_coherency Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala --- drivers/gpu/drm/i915/intel_engine_cs.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 759c0fd58f8c..117667cfbda1 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1195,10 +1195,14 @@ bool intel_engine_can_store_dword(struct intel_engine_cs *engine) case 3: /* maybe only uses physical not virtual addresses */ return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915)); + case 4: + case 5: + /* no known limitations */ + return true; case 6: return engine->class != VIDEO_DECODE_CLASS; /* b0rked */ default: - return true; + return engine->class != VIDEO_ENHANCEMENT_CLASS;/* incoherent */ } } -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915/selftests: Flush the test object on creation
Move the flush from before emitting the gpu_fill request to the object's
creation to avoid forcing a stall on each write. The only stall should
be after all the writes have been queued and we want to read the
results.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/selftests/i915_gem_context.c | 23 ++-
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 7d82043aff10..625762de7743 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -347,15 +347,12 @@ static int gpu_fill(struct drm_i915_gem_object *obj,
if (IS_ERR(vma))
return PTR_ERR(vma);
- err = i915_gem_object_set_to_gtt_domain(obj, false);
- if (err)
- return err;
-
err = i915_vma_pin(vma, 0, 0, PIN_HIGH | PIN_USER);
if (err)
return err;
- /* Within the GTT the huge objects maps every page onto
+ /*
+* Within the GTT the huge objects maps every page onto
* its 1024 real pages (using phys_pfn = dma_pfn % 1024).
* We set the nth dword within the page using the nth
* mapping via the GTT - this should exercise the GTT mapping
@@ -396,14 +393,15 @@ static int gpu_fill(struct drm_i915_gem_object *obj,
if (err)
goto skip_request;
+ i915_gem_chipset_flush(vm->i915);
+ i915_request_add(rq);
+
i915_gem_object_set_active_reference(batch->obj);
i915_vma_unpin(batch);
i915_vma_close(batch);
i915_vma_unpin(vma);
- i915_request_add(rq);
-
return 0;
skip_request:
@@ -531,11 +529,14 @@ create_test_object(struct i915_gem_context *ctx,
err = cpu_fill(obj, STACK_MAGIC);
if (err) {
- pr_err("Failed to fill object with cpu, err=%d\n",
- err);
+ pr_err("Failed to fill object with cpu, err=%d\n", err);
return ERR_PTR(err);
}
+ err = i915_gem_object_set_to_gtt_domain(obj, false);
+ if (err)
+ return ERR_PTR(err);
+
list_add_tail(>st_link, objects);
return obj;
}
@@ -843,11 +844,11 @@ static int write_to_scratch(struct i915_gem_context *ctx,
goto skip_request;
i915_gem_object_set_active_reference(obj);
+ i915_request_add(rq);
+
i915_vma_unpin(vma);
i915_vma_close(vma);
- i915_request_add(rq);
-
return 0;
skip_request:
--
2.19.1
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[Intel-gfx] [PATCH 2/3] drm/i915/selftests: Check MI_STORE_DWORD_IMM coherency
We use MI_STORE_DWORD_IMM internally (e.g. for gpu relocations) and so
require that it its writes flushed to memory on demand. Verify this with
a selftest.
Signed-off-by: Chris Wilson
---
.../drm/i915/selftests/i915_gem_coherency.c | 454 ++
1 file changed, 454 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
index f7392c1ffe75..ee4abf8ea141 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
@@ -26,6 +26,7 @@
#include "../i915_selftest.h"
#include "i915_random.h"
+#include "igt_flush_test.h"
static int cpu_set(struct drm_i915_gem_object *obj,
unsigned long offset,
@@ -386,10 +387,463 @@ static int igt_gem_coherency(void *arg)
goto unlock;
}
+#define DW_PER_PAGE (PAGE_SIZE / sizeof(u32))
+
+struct live_test {
+ struct drm_i915_private *i915;
+ const char *func;
+ const char *name;
+
+ unsigned int reset_global;
+ unsigned int reset_engine[I915_NUM_ENGINES];
+};
+
+static int begin_live_test(struct live_test *t,
+ struct drm_i915_private *i915,
+ const char *func,
+ const char *name)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err;
+
+ t->i915 = i915;
+ t->func = func;
+ t->name = name;
+
+ err = i915_gem_wait_for_idle(i915,
+I915_WAIT_LOCKED,
+MAX_SCHEDULE_TIMEOUT);
+ if (err) {
+ pr_err("%s(%s): failed to idle before, with err=%d!",
+ func, name, err);
+ return err;
+ }
+
+ i915->gpu_error.missed_irq_rings = 0;
+ t->reset_global = i915_reset_count(>gpu_error);
+
+ for_each_engine(engine, i915, id)
+ t->reset_engine[id] =
+ i915_reset_engine_count(>gpu_error, engine);
+
+ return 0;
+}
+
+static int end_live_test(struct live_test *t)
+{
+ struct drm_i915_private *i915 = t->i915;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ if (igt_flush_test(i915, I915_WAIT_LOCKED))
+ return -EIO;
+
+ if (t->reset_global != i915_reset_count(>gpu_error)) {
+ pr_err("%s(%s): GPU was reset %d times!\n",
+ t->func, t->name,
+ i915_reset_count(>gpu_error) - t->reset_global);
+ return -EIO;
+ }
+
+ for_each_engine(engine, i915, id) {
+ if (t->reset_engine[id] ==
+ i915_reset_engine_count(>gpu_error, engine))
+ continue;
+
+ pr_err("%s(%s): engine '%s' was reset %d times!\n",
+ t->func, t->name, engine->name,
+ i915_reset_engine_count(>gpu_error, engine) -
+ t->reset_engine[id]);
+ return -EIO;
+ }
+
+ if (i915->gpu_error.missed_irq_rings) {
+ pr_err("%s(%s): Missed interrupts on engines %lx\n",
+ t->func, t->name, i915->gpu_error.missed_irq_rings);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int cpu_fill(struct drm_i915_gem_object *obj, u32 value)
+{
+ const bool has_llc = HAS_LLC(to_i915(obj->base.dev));
+ unsigned int n, need_flush;
+ int err;
+
+ err = i915_gem_obj_prepare_shmem_write(obj, _flush);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; n++) {
+ u32 *map;
+
+ map = kmap_atomic(i915_gem_object_get_page(obj, n));
+ memset32(map, value, DW_PER_PAGE);
+ if (!has_llc)
+ drm_clflush_virt_range(map, PAGE_SIZE);
+ kunmap_atomic(map);
+ }
+
+ i915_gem_obj_finish_shmem_access(obj);
+ obj->read_domains = I915_GEM_DOMAIN_GTT | I915_GEM_DOMAIN_CPU;
+ obj->write_domain = 0;
+ return 0;
+}
+
+static int file_add_object(struct drm_file *file,
+ struct drm_i915_gem_object *obj)
+{
+ int err;
+
+ GEM_BUG_ON(obj->base.handle_count);
+
+ /* tie the object to the drm_file for easy reaping */
+ err = idr_alloc(>object_idr, >base, 1, 0, GFP_KERNEL);
+ if (err < 0)
+ return err;
+
+ i915_gem_object_get(obj);
+ obj->base.handle_count++;
+ return 0;
+}
+
+static struct drm_i915_gem_object *
+create_test_object(struct drm_i915_private *i915,
+ unsigned int num_pages,
+ struct drm_file *file,
+ struct list_head *objects)
+{
+ struct drm_i915_gem_object *obj;
+ int err;
+
+ obj = i915_gem_object_create_internal(i915, num_pages << PAGE_SHIFT);
+ if (IS_ERR(obj))
+
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave, Here's the -fixes for 4.20-rc4. Stuck backlight/flickering fix for DSI screen and GPU hang fix for SNB are the main user visible ones. Then two more fixes to prevent GPU hangs in more rare scenarios. Regards, Joonas *** drm-intel-fixes-2018-11-22: - Fix for fastboot DSI panel boot time flicker regression, also fixes Bugzilla #108225 - Fix Bugzilla #101269 to avoid GPU hangs on Sandybridge machines - Avoid GPU hang on error capture on Broxton with Vt-d enabled - Avoid missing GPU relocations on Pineview and Bearlake (Gen3) The following changes since commit 9ff01193a20d391e8dbce4403dd5ef87c7eaaca6: Linux 4.20-rc3 (2018-11-18 13:33:44 -0800) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2018-11-22 for you to fetch changes up to f559156c399cfb11d53a128d210118fbea36816e: drm/i915: Add rotation readout for plane initial config (2018-11-21 14:30:58 +0200) - Fix for fastboot DSI panel boot time flicker regression, also fixes Bugzilla #108225 - Fix Bugzilla #101269 to avoid GPU hangs on Sandybridge machines - Avoid GPU hang on error capture on Broxton with Vt-d enabled - Avoid missing GPU relocations on Pineview and Bearlake (Gen3) Chris Wilson (2): drm/i915: Prevent machine hang from Broxton's vtd w/a and error capture drm/i915: Write GPU relocs harder with gen3 Ville Syrjälä (3): drm/i915: Disable LP3 watermarks on all SNB machines drm/i915: Force a LUT update in intel_initial_commit() drm/i915: Add rotation readout for plane initial config drivers/gpu/drm/i915/i915_gem_execbuffer.c | 7 - drivers/gpu/drm/i915/i915_gem_gtt.c| 5 drivers/gpu/drm/i915/i915_gpu_error.c | 15 ++- drivers/gpu/drm/i915/i915_gpu_error.h | 8 +- drivers/gpu/drm/i915/intel_display.c | 39 drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c| 41 +- 7 files changed, 112 insertions(+), 4 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Synchronize hpd work in i915_hpd_storm_ctl_show()
== Series Details ==
Series: drm/i915: Synchronize hpd work in i915_hpd_storm_ctl_show()
URL : https://patchwork.freedesktop.org/series/52796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5175_full -> Patchwork_10872_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10872_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10872_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in
Patchwork_10872_full:
=== IGT changes ===
Warnings
igt@tools_test@sysfs_l3_parity:
shard-hsw: SKIP -> PASS
igt@tools_test@tools_test:
{shard-iclb}: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_10872_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@drm_import_export@import-close-race-flink:
shard-glk: PASS -> TIMEOUT (fdo#108667)
igt@gem_exec_schedule@pi-ringfull-bsd:
shard-skl: NOTRUN -> FAIL (fdo#103158)
igt@gem_exec_whisper@normal:
shard-skl: PASS -> TIMEOUT (fdo#108592)
igt@gem_userptr_blits@readonly-unsync:
shard-skl: NOTRUN -> INCOMPLETE (fdo#108074)
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +3
igt@kms_cursor_crc@cursor-64x64-random:
shard-glk: PASS -> FAIL (fdo#103232) +1
igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
shard-glk: PASS -> DMESG-WARN (fdo#105763, fdo#106538)
igt@kms_draw_crc@draw-method-rgb565-blt-ytiled:
shard-glk: PASS -> FAIL (fdo#103184)
igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled:
shard-skl: PASS -> FAIL (fdo#103184)
igt@kms_flip_tiling@flip-to-y-tiled:
shard-skl: PASS -> FAIL (fdo#107931)
igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
shard-skl: PASS -> FAIL (fdo#105682) +3
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
shard-apl: PASS -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
shard-glk: PASS -> FAIL (fdo#103167) +6
igt@kms_frontbuffer_tracking@fbc-farfromfence:
{shard-iclb}: PASS -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
shard-skl: NOTRUN -> FAIL (fdo#105683)
igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
shard-skl: PASS -> FAIL (fdo#103167)
igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb:
shard-skl: NOTRUN -> FAIL (fdo#108145) +1
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
shard-apl: PASS -> FAIL (fdo#103166) +1
igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format:
{shard-iclb}: NOTRUN -> DMESG-WARN (fdo#107724)
igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
{shard-iclb}: PASS -> DMESG-WARN (fdo#107724) +1
igt@kms_setmode@basic:
shard-hsw: PASS -> FAIL (fdo#99912)
shard-kbl: PASS -> FAIL (fdo#99912)
igt@perf@polling:
shard-hsw: PASS -> FAIL (fdo#102252)
igt@pm_rpm@reg-read-ioctl:
shard-skl: NOTRUN -> INCOMPLETE (fdo#107807)
{igt@runner@aborted}:
shard-hsw: NOTRUN -> FAIL (fdo#108770)
Possible fixes
igt@drm_import_export@import-close-race-flink:
shard-skl: TIMEOUT (fdo#108667) -> PASS
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-kbl: INCOMPLETE (fdo#106887, fdo#103665, fdo#106023) ->
PASS
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
shard-kbl: DMESG-WARN (fdo#107956) -> PASS
igt@kms_chv_cursor_fail@pipe-b-256x256-right-edge:
shard-skl: FAIL (fdo#104671) -> PASS
igt@kms_color@pipe-c-ctm-0-75:
shard-skl: FAIL (fdo#108682) -> PASS
igt@kms_cursor_crc@cursor-128x128-suspend:
shard-glk: FAIL (fdo#103232) -> PASS +3
igt@kms_draw_crc@draw-method-xrgb-render-ytiled:
{shard-iclb}: WARN (fdo#108336) -> PASS +2
igt@kms_flip@plain-flip-fb-recreate-interruptible:
shard-skl: FAIL (fdo#100368) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
{shard-iclb}: FAIL (fdo#103167) -> PASS
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
shard-glk: FAIL (fdo#103167) -> PASS +1
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
{shard-iclb}: DMESG-FAIL (fdo#107724) -> PASS +6
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: avoid rebuilding i915_gpu_error.o on version string updates
Merged now, thanks for the patch and reviews.
Quoting Patchwork (2018-11-22 02:05:03)
> == Series Details ==
>
> Series: drm/i915: avoid rebuilding i915_gpu_error.o on version string updates
> URL : https://patchwork.freedesktop.org/series/52822/
> State : success
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_5181_full -> Patchwork_10877_full =
>
> == Summary - WARNING ==
>
> Minor unknown changes coming with Patchwork_10877_full need to be verified
> manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_10877_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> == Possible new issues ==
>
> Here are the unknown changes that may have been introduced in
> Patchwork_10877_full:
>
> === IGT changes ===
>
> Warnings
>
> igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt:
> shard-hsw: SKIP -> PASS
>
> igt@perf_pmu@rc6-runtime-pm-long:
> shard-kbl: PASS -> SKIP +1
>
> igt@pm_rc6_residency@rc6-accuracy:
> shard-kbl: SKIP -> PASS
> shard-snb: PASS -> SKIP
>
> igt@tools_test@tools_test:
> {shard-iclb}: PASS -> SKIP
>
>
> == Known issues ==
>
> Here are the changes found in Patchwork_10877_full that come from known
> issues:
>
> === IGT changes ===
>
> Issues hit
>
> igt@i915_suspend@shrink:
> {shard-iclb}: NOTRUN -> DMESG-WARN (fdo#108784)
>
> igt@kms_busy@extended-modeset-hang-newfb-render-b:
> shard-skl: NOTRUN -> DMESG-WARN (fdo#107956)
>
> igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
> {shard-iclb}: NOTRUN -> DMESG-WARN (fdo#107956)
>
> igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
> shard-glk: PASS -> FAIL (fdo#108145)
>
> igt@kms_color@pipe-a-legacy-gamma:
> shard-apl: PASS -> FAIL (fdo#108145, fdo#104782)
>
> igt@kms_cursor_crc@cursor-128x128-suspend:
> shard-skl: PASS -> FAIL (fdo#103191, fdo#103232)
>
> igt@kms_cursor_crc@cursor-64x21-sliding:
> {shard-iclb}: NOTRUN -> FAIL (fdo#103232) +1
>
> igt@kms_cursor_crc@cursor-64x64-onscreen:
> shard-skl: PASS -> FAIL (fdo#103232) +1
>
> igt@kms_fbcon_fbt@psr-suspend:
> {shard-iclb}: NOTRUN -> FAIL (fdo#107882)
>
> igt@kms_flip@plain-flip-ts-check:
> shard-kbl: PASS -> DMESG-WARN (fdo#103558, fdo#103313,
> fdo#105602) +4
>
> igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
> shard-apl: PASS -> FAIL (fdo#103167)
>
> igt@kms_frontbuffer_tracking@fbc-1p-rte:
> shard-kbl: PASS -> DMESG-WARN (fdo#103558, fdo#103313)
>
> igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
> shard-glk: PASS -> FAIL (fdo#103167) +1
>
> igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc:
> shard-skl: PASS -> FAIL (fdo#103167) +3
>
> igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
> {shard-iclb}: PASS -> FAIL (fdo#103167) +1
>
> igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
> {shard-iclb}: PASS -> FAIL (fdo#105683)
>
> igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
> {shard-iclb}: NOTRUN -> FAIL (fdo#103167) +3
>
> igt@kms_hdmi_inject@inject-audio:
> {shard-iclb}: NOTRUN -> FAIL (fdo#102370)
>
> igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
> shard-skl: PASS -> INCOMPLETE (fdo#107773, fdo#104108)
>
> igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
> shard-skl: PASS -> FAIL (fdo#108145, fdo#107815)
>
> igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
> shard-glk: PASS -> FAIL (fdo#103166) +2
> shard-apl: PASS -> FAIL (fdo#103166)
>
> igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
> {shard-iclb}: PASS -> FAIL (fdo#103166) +2
>
> igt@kms_psr@no_drrs:
> {shard-iclb}: PASS -> FAIL (fdo#108341)
>
> igt@kms_sysfs_edid_timing:
> shard-skl: NOTRUN -> FAIL (fdo#100047)
>
> igt@pm_rpm@fences:
> shard-skl: NOTRUN -> INCOMPLETE (fdo#107807)
>
> igt@pm_rpm@modeset-non-lpsp-stress:
> shard-skl: SKIP -> INCOMPLETE (fdo#107807)
>
>
> Possible fixes
>
> igt@kms_atomic_transition@1x-modeset-transitions:
> shard-hsw: DMESG-FAIL (fdo#102614) -> PASS
>
> igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
> shard-hsw: DMESG-WARN (fdo#107956) -> PASS
>
> igt@kms_color@pipe-b-degamma:
> shard-skl: FAIL (fdo#104782) -> PASS
>
> igt@kms_cursor_crc@cursor-256x256-random:
> shard-apl: FAIL
Re: [Intel-gfx] [PATCH] mm: convert totalram_pages, totalhigh_pages and managed_pages to atomic.
On Mon, Oct 22, 2018 at 10:53:22PM +0530, Arun KS wrote: > Remove managed_page_count_lock spinlock and instead use atomic > variables. > > Suggested-by: Michal Hocko > Suggested-by: Vlastimil Babka > Signed-off-by: Arun KS > > --- > As discussed here, > https://patchwork.kernel.org/patch/10627521/#22261253 > --- > --- > arch/csky/mm/init.c | 4 +- > arch/powerpc/platforms/pseries/cmm.c | 11 ++-- > arch/s390/mm/init.c | 2 +- > arch/um/kernel/mem.c | 4 +- > arch/x86/kernel/cpu/microcode/core.c | 5 +- > drivers/char/agp/backend.c| 4 +- > drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +- > drivers/gpu/drm/i915/i915_gem.c | 2 +- > drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 +- > drivers/hv/hv_balloon.c | 19 +++ > drivers/md/dm-bufio.c | 5 +- > drivers/md/dm-crypt.c | 4 +- > drivers/md/dm-integrity.c | 4 +- > drivers/md/dm-stats.c | 3 +- > drivers/media/platform/mtk-vpu/mtk_vpu.c | 3 +- > drivers/misc/vmw_balloon.c| 2 +- > drivers/parisc/ccio-dma.c | 5 +- > drivers/parisc/sba_iommu.c| 5 +- > drivers/staging/android/ion/ion_system_heap.c | 2 +- > drivers/xen/xen-selfballoon.c | 7 +-- > fs/ceph/super.h | 3 +- > fs/file_table.c | 9 ++-- > fs/fuse/inode.c | 4 +- > fs/nfs/write.c| 3 +- > fs/nfsd/nfscache.c| 3 +- > fs/ntfs/malloc.h | 2 +- > fs/proc/base.c| 3 +- > include/linux/highmem.h | 2 +- > include/linux/mm.h| 2 +- > include/linux/mmzone.h| 10 +--- > include/linux/swap.h | 2 +- > kernel/fork.c | 6 +-- > kernel/kexec_core.c | 5 +- > kernel/power/snapshot.c | 2 +- > lib/show_mem.c| 3 +- > mm/highmem.c | 2 +- > mm/huge_memory.c | 2 +- > mm/kasan/quarantine.c | 4 +- > mm/memblock.c | 6 +-- > mm/memory_hotplug.c | 4 +- > mm/mm_init.c | 3 +- > mm/oom_kill.c | 2 +- > mm/page_alloc.c | 75 > ++- > mm/shmem.c| 12 +++-- > mm/slab.c | 3 +- > mm/swap.c | 3 +- > mm/util.c | 2 +- > mm/vmalloc.c | 4 +- > mm/vmstat.c | 4 +- > mm/workingset.c | 2 +- > mm/zswap.c| 2 +- > net/dccp/proto.c | 6 +-- > net/decnet/dn_route.c | 2 +- > net/ipv4/tcp_metrics.c| 2 +- > net/netfilter/nf_conntrack_core.c | 6 +-- > net/netfilter/xt_hashlimit.c | 4 +- > net/sctp/protocol.c | 6 +-- > security/integrity/ima/ima_kexec.c| 2 +- > 58 files changed, 171 insertions(+), 143 deletions(-) > > diff --git a/arch/csky/mm/init.c b/arch/csky/mm/init.c > index dc07c07..3f4d35e 100644 > --- a/arch/csky/mm/init.c > +++ b/arch/csky/mm/init.c > @@ -71,7 +71,7 @@ void free_initrd_mem(unsigned long start, unsigned long end) > ClearPageReserved(virt_to_page(start)); > init_page_count(virt_to_page(start)); > free_page(start); > - totalram_pages++; > + atomic_long_inc(_pages); > } > } > #endif > @@ -88,7 +88,7 @@ void free_initmem(void) > ClearPageReserved(virt_to_page(addr)); > init_page_count(virt_to_page(addr)); > free_page(addr); > - totalram_pages++; > + atomic_long_inc(_pages); > addr += PAGE_SIZE; > } For csky part, it's OK. Guo Ren ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/atomic: Create and use __drm_atomic_helper_crtc_reset() everywhere
On 12/11/2018 15:01, Maarten Lankhorst wrote:
> We already have __drm_atomic_helper_connector_reset() and
> __drm_atomic_helper_plane_reset(), extend this to crtc as well.
>
> Most drivers already have a gpu reset hook, correct it.
> Nouveau already implemented its own __drm_atomic_helper_crtc_reset(),
> convert it to the common one.
>
> Signed-off-by: Maarten Lankhorst
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: "David (ChunMing) Zhou"
> Cc: David Airlie
> Cc: Liviu Dudau
> Cc: Brian Starkey
> Cc: Mali DP Maintainers
> Cc: Boris Brezillon
> Cc: Nicolas Ferre
> Cc: Alexandre Belloni
> Cc: Ludovic Desroches
> Cc: Maarten Lankhorst
> Cc: Maxime Ripard
> Cc: Sean Paul
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: Philipp Zabel
> Cc: CK Hu
> Cc: Matthias Brugger
> Cc: Rob Clark
> Cc: Ben Skeggs
> Cc: Tomi Valkeinen
> Cc: Laurent Pinchart
> Cc: Kieran Bingham
> Cc: Sandy Huang
> Cc: "Heiko Stübner"
> Cc: Thierry Reding
> Cc: Jonathan Hunter
> Cc: Eric Anholt
> Cc: VMware Graphics
> Cc: Sinclair Yeh
> Cc: Thomas Hellstrom
> Cc: Tony Cheng
> Cc: Shirish S
> Cc: Mikita Lipski
> Cc: Bhawanpreet Lakha
> Cc: David Francis
> Cc: Anthony Koo
> Cc: Jeykumar Sankaran
> Cc: Jordan Crouse
> Cc: Bruce Wang
> Cc: Sravanthi Kollukuduru
> Cc: Archit Taneja
> Cc: Steve Kowalik
> Cc: Carsten Behling
> Cc: Haneen Mohammed
> Cc: Daniel Vetter
> Cc: Rodrigo Siqueira
> Cc: Mahesh Kumar
> Cc: amd-...@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Cc: linux-ker...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: intel-gfx@lists.freedesktop.org
> Cc: linux-media...@lists.infradead.org
> Cc: linux-arm-...@vger.kernel.org
> Cc: freedr...@lists.freedesktop.org
> Cc: nouv...@lists.freedesktop.org
> Cc: linux-renesas-...@vger.kernel.org
> Cc: linux-rockc...@lists.infradead.org
> Cc: linux-te...@vger.kernel.org
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +--
> drivers/gpu/drm/arm/malidp_crtc.c | 5 +--
> .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c| 5 +--
> drivers/gpu/drm/drm_atomic_state_helper.c | 31 ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/imx/ipuv3-crtc.c | 5 +--
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 5 +--
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 ++-
> drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 6 +---
> drivers/gpu/drm/nouveau/dispnv50/head.c | 13 ++--
> drivers/gpu/drm/omapdrm/omap_crtc.c | 7 ++---
> drivers/gpu/drm/rcar-du/rcar_du_crtc.c| 4 +--
> drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 7 +++--
> drivers/gpu/drm/tegra/dc.c| 5 +--
> drivers/gpu/drm/vc4/vc4_crtc.c| 8 ++---
> drivers/gpu/drm/vkms/vkms_crtc.c | 7 +
> drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 9 +-
> include/drm/drm_atomic_state_helper.h | 2 ++
> 18 files changed, 56 insertions(+), 81 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 5064768642f3..770a71726cd1 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -2802,9 +2802,7 @@ static void dm_crtc_reset_state(struct drm_crtc *crtc)
> if (WARN_ON(!state))
> return;
>
> - crtc->state = >base;
> - crtc->state->crtc = crtc;
> -
> + __drm_atomic_helper_crtc_reset(crtc, >base);
> }
>
> static struct drm_crtc_state *
> diff --git a/drivers/gpu/drm/arm/malidp_crtc.c
> b/drivers/gpu/drm/arm/malidp_crtc.c
> index e1b72782848c..9a924ff27148 100644
> --- a/drivers/gpu/drm/arm/malidp_crtc.c
> +++ b/drivers/gpu/drm/arm/malidp_crtc.c
> @@ -474,10 +474,7 @@ static void malidp_crtc_reset(struct drm_crtc *crtc)
>
> kfree(state);
> state = kzalloc(sizeof(*state), GFP_KERNEL);
> - if (state) {
> - crtc->state = >base;
> - crtc->state->crtc = crtc;
> - }
> + __drm_atomic_helper_crtc_reset(crtc, >base);
> }
>
> static void malidp_crtc_destroy_state(struct drm_crtc *crtc,
> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> index 96f4082671fe..8084d549c7d1 100644
> --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> @@ -412,10 +412,7 @@ static void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc)
> }
>
> state = kzalloc(sizeof(*state), GFP_KERNEL);
> - if (state) {
> - crtc->state = >base;
> - crtc->state->crtc = crtc;
> - }
> + __drm_atomic_helper_crtc_reset(crtc, >base);
> }
>
> static struct drm_crtc_state *
> diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
>
Re: [Intel-gfx] [PATCH v2 0/7] Make GEN macros more similar
On 21/11/2018 22:19, Rodrigo Vivi wrote: On Mon, Nov 19, 2018 at 02:20:55PM -0800, Lucas De Marchi wrote: On Thu, Nov 08, 2018 at 11:23:46AM +, Tvrtko Ursulin wrote: On 08/11/2018 00:57, Lucas De Marchi wrote: On Wed, Nov 07, 2018 at 10:05:19AM +, Tvrtko Ursulin wrote: On 06/11/2018 21:51, Lucas De Marchi wrote: This is the second version of the series trying to make GEN checks more similar. These or roughly the changes from v1: - We don't have a single macro receiving 2 or 3 parameters. Now there is GT_GEN_RANGE(), and GT_GEN(). The firs is the conversion from IS_GEN() while the second is the conversion from IS_GEN() - Bring GEN_FOREVER back to be used with above macros - Patch converting <, <=, ==, >, >= checks using INTEL_GEN() to use the macros above was added - INTEL_GEN() is removed to avoid it being used when we should prefer the new macros The idea of the names is to pave the way for checks of the display version, which would be named DISPLAY_GEN(), DISPLAY_GEN_RANGE(). In the commit messages we have the scripts to regenerate the patch to make it easier to apply after the discussions and also to be able to convert inflight patches. Sorry in advance for the noise this causes in the codebase, but hopefully it is for the greater good. Lucas De Marchi (6): Revert "drm/i915: Kill GEN_FOREVER" drm/i915: replace IS_GEN with GT_GEN(..., N) drm/i915: rename IS_GEN9_* to GT_GEN9_* drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE I have reservations about this patch, where I think forcing only one flavour maybe is not the best thing. Because for plain if-ladder cases it feels more readable to stick with the current scheme of arithmetic comparisons. And it is more efficient in code as well. Range checks are on the other hand useful either when combined in the same conditional as some other bitmask based test, or when both ends of the comparison edge are bound. So are you against changing the == to use the macros, changing the >=, >, <, <=, or all of them? Definitely not all of them. Just plain if ladders I think are definitely more readable in source and result in better code in the normal fashion of: if (gen >= 11) else if (gen >= 9) else if (gen >= 7) ... etc ... Where I think it makes sense is when either both edges are bound, like: if (gen < 11 || gen >= 8) if (gen >= 10 || gen == 8) ok, I will take a look before respinning this. But not sure how many of those there are. What definitely exists in large-ish numbers are: specially on display side... if (gen >= 11 || IS_PLATFORM) My goal is exactly to organize the gen numbers in a way that we minimize this mix as much as possible. At some point I had a prototype which puts the gen and platform masks into a bag of bits and then, depending on bits locality, this too can be compressed to a single bitmask test. However I felt that was going too far, and the issue is achieving interesting bits locality for it too work. But I digress. Looking at the changes to ==, they seem very reasonable and in a few cases it allowed the next patch to merge them in a GT_GEN_RANGE() -- yes the patch ordering was on purpose to allow that. Yep those are the good ones. The others are indeed debatable. However IMO for the cases it makes sense, there's always the fallback if (dev_priv->info.gen == 10) ... else if (dev_priv->info.gen == 11) ... else if (dev_priv->info.gen < 5) ... We can go on a case by case manner in this patch rather than the mass conversion for these. drm/i915: merge gen checks to use range drm/i915: remove INTEL_GEN macro I have reservations about this as as well, especially considering the previous paragraph. But even on it's own I am not sure we want to go back to more verbose. see above. IMO it's not actually so verbose as one would think. if (INTEL_GEN(dev_priv) == 11) vs if (dev_priv->info.gen == 11) I think it should be: if (INTEL_INFO(dev_priv)->gen == 11) Which is a tiny bit longer.. If it's longer, why bother? We could just as well do for the if ladders: gen = dev_priv->info.gen; or gen = INTEL_INFO(dev_priv)->gen In your other series you would be moving gen to a runtime info, so this would cause the same amount of churn (although I disagree with moving gen to a runtime info just because of the mock struct). The "verbose" version is actually one character less and one lookup less to what the macro is doing underneath. Of course that means a lot of churn to the codebase when/if we change where the gen number is located, but that number is at the same place since its introduction in 2010 (commit c96c3a8cb7fadcb33d9a5ebe35fcee8b7d0a7946) I am pretty sure we went through patches to a) move towards INTEL_INFO and b) replace INTEL_INFO(dev_priv)->gen with INTEL_GEN. So I don't see an advantage of reverting that, just so that we can lose
Re: [Intel-gfx] [PATCH 01/15] drm/vblank: Allow dynamic per-crtc max_vblank_count
On Wed, Nov 21, 2018 at 06:46:57PM +0200, Ville Syrjälä wrote:
> On Wed, Nov 21, 2018 at 05:22:49PM +0100, Daniel Vetter wrote:
> > On Wed, Nov 21, 2018 at 5:16 PM Ville Syrjälä
> > wrote:
> > >
> > > On Wed, Nov 21, 2018 at 04:19:36PM +0100, Daniel Vetter wrote:
> > > > On Wed, Nov 21, 2018 at 01:37:51PM +0200, Ville Syrjälä wrote:
> > > > > On Wed, Nov 21, 2018 at 10:27:27AM +0100, Daniel Vetter wrote:
> > > > > > On Mon, Nov 12, 2018 at 06:59:45PM +0200, Ville Syrjala wrote:
> > > > > > > From: Ville Syrjälä
> > > > > > >
> > > > > > > On i965gm we need to adjust max_vblank_count dynamically
> > > > > > > depending on whether the TV encoder is used or not. To
> > > > > > > that end add a per-crtc max_vblank_count that takes
> > > > > > > precedence over its device wide counterpart. The driver
> > > > > > > can now call drm_crtc_set_max_vblank_count() to configure
> > > > > > > the per-crtc value before calling drm_vblank_on().
> > > > > > >
> > > > > > > Also looks like there was some discussion about exynos needing
> > > > > > > similar treatment.
> > > > > > >
> > > > > > > Cc: sta...@vger.kernel.org
> > > > > > > Cc: Inki Dae
> > > > > > > Cc: Daniel Vetter
> > > > > > > Signed-off-by: Ville Syrjälä
> > > > > > > ---
> > > > > > > drivers/gpu/drm/drm_vblank.c | 39
> > > > > > >
> > > > > > > include/drm/drm_vblank.h | 8
> > > > > > > 2 files changed, 43 insertions(+), 4 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/drm_vblank.c
> > > > > > > b/drivers/gpu/drm/drm_vblank.c
> > > > > > > index 98e091175921..c3abbdca8aba 100644
> > > > > > > --- a/drivers/gpu/drm/drm_vblank.c
> > > > > > > +++ b/drivers/gpu/drm/drm_vblank.c
> > > > > > > @@ -105,13 +105,20 @@ static void store_vblank(struct drm_device
> > > > > > > *dev, unsigned int pipe,
> > > > > > > write_sequnlock(>seqlock);
> > > > > > > }
> > > > > > >
> > > > > > > +static u32 drm_max_vblank_count(struct drm_device *dev, unsigned
> > > > > > > int pipe)
> > > > > > > +{
> > > > > > > + struct drm_vblank_crtc *vblank = >vblank[pipe];
> > > > > > > +
> > > > > > > + return vblank->max_vblank_count ?: dev->max_vblank_count;
> > > > > > > +}
> > > > > > > +
> > > > > > > /*
> > > > > > > * "No hw counter" fallback implementation of
> > > > > > > .get_vblank_counter() hook,
> > > > > > > * if there is no useable hardware frame counter available.
> > > > > > > */
> > > > > > > static u32 drm_vblank_no_hw_counter(struct drm_device *dev,
> > > > > > > unsigned int pipe)
> > > > > > > {
> > > > > > > - WARN_ON_ONCE(dev->max_vblank_count != 0);
> > > > > > > + WARN_ON_ONCE(drm_max_vblank_count(dev, pipe) != 0);
> > > > > > > return 0;
> > > > > > > }
> > > > > > >
> > > > > > > @@ -198,6 +205,7 @@ static void drm_update_vblank_count(struct
> > > > > > > drm_device *dev, unsigned int pipe,
> > > > > > > ktime_t t_vblank;
> > > > > > > int count = DRM_TIMESTAMP_MAXRETRIES;
> > > > > > > int framedur_ns = vblank->framedur_ns;
> > > > > > > + u32 max_vblank_count = drm_max_vblank_count(dev, pipe);
> > > > > > >
> > > > > > > /*
> > > > > > > * Interrupts were disabled prior to this call, so deal
> > > > > > > with counter
> > > > > > > @@ -216,9 +224,9 @@ static void drm_update_vblank_count(struct
> > > > > > > drm_device *dev, unsigned int pipe,
> > > > > > > rc = drm_get_last_vbltimestamp(dev, pipe,
> > > > > > > _vblank, in_vblank_irq);
> > > > > > > } while (cur_vblank != __get_vblank_counter(dev, pipe) &&
> > > > > > > --count > 0);
> > > > > > >
> > > > > > > - if (dev->max_vblank_count != 0) {
> > > > > > > + if (max_vblank_count) {
> > > > > > > /* trust the hw counter when it's around */
> > > > > > > - diff = (cur_vblank - vblank->last) &
> > > > > > > dev->max_vblank_count;
> > > > > > > + diff = (cur_vblank - vblank->last) &
> > > > > > > max_vblank_count;
> > > > > > > } else if (rc && framedur_ns) {
> > > > > > > u64 diff_ns = ktime_to_ns(ktime_sub(t_vblank,
> > > > > > > vblank->time));
> > > > > > >
> > > > > > > @@ -258,7 +266,8 @@ static void drm_update_vblank_count(struct
> > > > > > > drm_device *dev, unsigned int pipe,
> > > > > > > pipe, vblank->count, diff, cur_vblank,
> > > > > > > vblank->last);
> > > > > > >
> > > > > > > if (diff == 0) {
> > > > > > > - WARN_ON_ONCE(cur_vblank != vblank->last);
> > > > > > > + WARN_ON_ONCE(max_vblank_count &&
> > > > > > > +cur_vblank != vblank->last);
> > > > > >
> > > > > > Unrelated bugfix for this warning? Should be a separate patch I
> > > > > > think, or
> > > > > > I'm missing something.
> > > > >
> > > > > Ah, yeah this was due to a quirk of i965gm hardware. The hw counter
> > > > > does work until the exact
