== Series Details ==
Series: series starting with [1/5] drm/i915/execlists: Flush the tasklet on
parking
URL : https://patchwork.freedesktop.org/series/60125/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6018 -> Patchwork_12914
From: Ville Syrjälä
Supposedly both src coordinates have to even when doing 90/270
degree rotation with RGB565. This is definitely true for the
X coordinate (we just get a black screen when it is odd). My
experiments didn't show any misbehaviour with an odd
Y coordinate, but let's trust the spec
== Series Details ==
Series: drm/i915: Fix 90/270 degree rotated RGB565 src coord checks (rev2)
URL : https://patchwork.freedesktop.org/series/59956/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6018 -> Patchwork_12916
== Series Details ==
Series: drm/i915: Fix 90/270 degree rotated RGB565 src coord checks (rev2)
URL : https://patchwork.freedesktop.org/series/59956/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Fix 90/270 degree rotated RGB565 src coord
== Series Details ==
Series: series starting with [1/2] drm/i915: Don't skip audio enable if ELD is
bogus
URL : https://patchwork.freedesktop.org/series/60119/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6017 -> Patchwork_12912
On Thu, Apr 11, 2019 at 08:33:08PM +, Sripada, Radhakrishna wrote:
> On Thu, 2019-04-11 at 21:27 +0300, Ville Syrjälä wrote:
> > On Tue, Apr 09, 2019 at 02:04:01PM -0700, Dhinakaran Pandiyan wrote:
> > > On Tue, 2019-04-09 at 23:38 +0300, Ville Syrjälä wrote:
> > > > On Tue, Apr 09, 2019 at
On Tue, Apr 30, 2019 at 07:13:36PM +0530, Sharma, Shashank wrote:
>
> On 4/30/2019 4:09 PM, Ville Syrjälä wrote:
> > On Tue, Apr 30, 2019 at 10:22:40AM +0530, Sharma, Shashank wrote:
> >> On 4/26/2019 8:07 PM, Ville Syrjälä wrote:
> >>> On Fri, Apr 26, 2019 at 06:40:11PM +0530, Sharma, Shashank
On 4/30/19 2:25 AM, Jani Nikula wrote:
On Thu, 04 Apr 2019, Aditya Swarup wrote:
On Tue, Apr 02, 2019 at 05:14:40AM -0700, Aditya Swarup wrote:
Adding N & CTS values for 10/12 bit deep color from Appendix C
table in HDMI 2.0 spec. The correct values for N is not chosen
automatically by
== Series Details ==
Series: Enable Multi-segmented-gamma for ICL
URL : https://patchwork.freedesktop.org/series/60126/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
dc4b88abc4e0 drm/i915: Change gamma/degamma_lut_size data type to u32
8811262cd9fa drm/i915/icl: Add register
== Series Details ==
Series: drm/i915: Drop the _INCOMPLETE for has_infoframe
URL : https://patchwork.freedesktop.org/series/60120/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6018 -> Patchwork_12913
Summary
---
== Series Details ==
Series: Enable Multi-segmented-gamma for ICL
URL : https://patchwork.freedesktop.org/series/60126/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6018 -> Patchwork_12915
Summary
---
**SUCCESS**
On Tue, Apr 30, 2019 at 01:10:02PM +0200, Christian König wrote:
> Add a structure for the parameters of dma_buf_attach, this makes it much
> easier
> to add new parameters later on.
I don't understand this reasoning. What are the "new parameters" that
are being proposed, and why do we need to
== Series Details ==
Series: drm/i915: Fix 90/270 degree rotated RGB565 src coord checks (rev2)
URL : https://patchwork.freedesktop.org/series/59956/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
53aadb3c2bf5 drm/i915: Fix 90/270 degree rotated RGB565 src coord checks
-:47:
Additionally, ensure these are all prefixed with intel_sseu_*
to match the convention of other functions in i915.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 54 +++
drivers/gpu/drm/i915/gt/intel_sseu.h | 57 +++-
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice
Add a new function to return the number of subslices per slice to
consolidate code usage.
v2: rebase on changes to move sseu struct to intel_sseu.h
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 6 ++
In the GETPARAM ioctl handler, use a local variable to consolidate
usage of SSEU runtime info.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/i915_drv.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git
Hi "Christian,
I love your patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.1-rc7 next-20190430]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0d
This patch series contains a few code clean-up patches, followed
by a patch which changes the storage of the subslice mask to better
match the userspace access through the I915_QUERY_TOPOLOGY_INFO
ioctl. The index into the subslice_mask array is then calculated:
slice * subslice stride +
== Series Details ==
Series: Refactor to expand subslice mask (rev5)
URL : https://patchwork.freedesktop.org/series/59742/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6020 -> Patchwork_12917
Summary
---
On Tue, 2019-04-30 at 11:58 +0300, Jani Nikula wrote:
> On Mon, 29 Apr 2019, Stuart Summers wrote:
> > In the GETPARAM ioctl handler, use a local variable to consolidate
> > usage of SSEU runtime info.
> >
> > Cc: Daniele Ceraolo Spurio
> > Signed-off-by: Stuart Summers
> > ---
> >
== Series Details ==
Series: Refactor to expand subslice mask (rev5)
URL : https://patchwork.freedesktop.org/series/59742/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Use local variable for SSEU info in GETPARAM ioctl
Okay!
Commit:
== Series Details ==
Series: i915: disable framebuffer compression on GeminiLake
URL : https://patchwork.freedesktop.org/series/60090/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6014_full -> Patchwork_12904_full
Summary
Subslice stride and EU stride are calculated multiple times in
i915_query. Move this calculation to a macro to reduce code duplication.
v2: update headers in intel_sseu.h
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 2 ++
v2: fix spacing from checkpatch warning
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 47
drivers/gpu/drm/i915/intel_device_info.h | 47
2 files changed, 47 insertions(+), 47 deletions(-)
diff --git
== Series Details ==
Series: Refactor to expand subslice mask (rev6)
URL : https://patchwork.freedesktop.org/series/59742/
State : failure
== Summary ==
Applying: drm/i915: Use local variable for SSEU info in GETPARAM ioctl
Applying: drm/i915: Add macro for SSEU stride calculation
Applying:
On Tue, Apr 30, 2019 at 06:05:18PM +0300, Ville Syrjälä wrote:
> On Mon, Apr 29, 2019 at 05:00:28PM -0700, Aditya Swarup wrote:
> > From: Ville Syrjälä
> >
> > There is a bug in hdmi_deep_color_possible() - we compare pipe_bpp
> > <= 8*3 which returns true every time for hdmi_deep_color_possible
== Series Details ==
Series: Refactor to expand subslice mask (rev5)
URL : https://patchwork.freedesktop.org/series/59742/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2699899bf520 drm/i915: Use local variable for SSEU info in GETPARAM ioctl
5c73378a02c2 drm/i915: Add macro
In the GETPARAM ioctl handler, use a local variable to consolidate
usage of SSEU runtime info.
v2: add const to sseu_dev_info variable
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/i915_drv.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
== Series Details ==
Series: drm/i915/csr: alpha_support doesn't depend on csr or vice versa (rev2)
URL : https://patchwork.freedesktop.org/series/60062/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6014_full -> Patchwork_12903_full
== Series Details ==
Series: dma-buf: add struct dma_buf_attach_info v2
URL : https://patchwork.freedesktop.org/series/60107/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6017_full -> Patchwork_12908_full
Summary
---
== Series Details ==
Series: series starting with [1/2] drm/i915: Use mul_u32_u32() more (rev2)
URL : https://patchwork.freedesktop.org/series/59180/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6017_full -> Patchwork_12909_full
== Series Details ==
Series: drm/i915: add single combo phy init/unit functions
URL : https://patchwork.freedesktop.org/series/60112/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6017 -> Patchwork_12910
Summary
---
== Series Details ==
Series: drm/i915: Corrupt DSI picture fix for GeminiLake (rev3)
URL : https://patchwork.freedesktop.org/series/60084/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Corrupt DSI picture fix for GeminiLake
== Series Details ==
Series: drm/i915: Corrupt DSI picture fix for GeminiLake (rev3)
URL : https://patchwork.freedesktop.org/series/60084/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6017 -> Patchwork_12911
Summary
On Mon, Apr 29, 2019 at 05:00:28PM -0700, Aditya Swarup wrote:
> From: Ville Syrjälä
>
> There is a bug in hdmi_deep_color_possible() - we compare pipe_bpp
> <= 8*3 which returns true every time for hdmi_deep_color_possible 12 bit
> deep color mode test in intel_hdmi_compute_config().(Even when
== Series Details ==
Series: series starting with [1/2] drm/i915: Don't skip audio enable if ELD is
bogus
URL : https://patchwork.freedesktop.org/series/60119/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e685e5944a53 drm/i915: Don't skip audio enable if ELD is bogus
== Series Details ==
Series: series starting with [1/2] drm/i915: Don't skip audio enable if ELD is
bogus
URL : https://patchwork.freedesktop.org/series/60119/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Don't skip audio enable if ELD is
The original intent for the delay before running the idle_work was to
provide a hysteresis to avoid ping-ponging the device runtime-pm. Since
then we have also pulled in some memory management and general device
management for parking. But with the inversion of the wakeref handling,
GEM is no
Tidy up the cleanup sequence by always ensure that the tasklet is
flushed on parking (before we cleanup). The parking provides a
convenient point to ensure that the backend is truly idle.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 25 +++--
Drop the check in GEM parking that the engines were already parked. The
intention here was that before we dropped the GT wakeref, we were sure
that no more interrupts could be raised -- however, we have already
dropped the wakeref by this point and the warning is no longer valid.
Signed-off-by:
If the user is racing a call to debugfs/i915_drop_caches with ongoing
submission from another thread/process, we may never end up idling the
GPU and be uninterruptibly spinning in debugfs/i915_drop_caches trying
to catch an idle moment.
Just flush the work once, that should be enough to park the
Replace the racy continuation check within retire_work with a definite
kill-switch on idling. The race was being exposed by gem_concurrent_blit
where the retire_worker would be terminated too early leaving us
spinning in debugfs/i915_drop_caches with nothing flushing the
retirement queue.
ICL introduces a new gamma correction mode in display engine, called
multi-segmented-gamma mode. This mode allows users to program the
darker region of the gamma curve with sueprfine precision. An
example use case for this is HDR curves (like PQ ST-2084).
If we plot a gamma correction curve from
From: Uma Shankar
Add macros to define multi segmented gamma registers
V2: Addressed Ville's comments:
Add gen-lable before bit definition
Addressed Jani's comment
- Use REG_GENMASK() and REG_BIT()
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Maarten Lankhorst
Signed-off-by:
This patch renames function ivb_load_lut_10_max to
ivb_load_lut_ext_max.
Cc: Uma Shankar
Suggested-by: Ville Syrjala
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_color.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git
Currently, data type of gamma_lut_size & degamma_lut_size elements
in intel_device_info is u16, which means it can accommodate maximum
64k values. In case of ICL multisegmented gamma, the size of gamma
LUT is 256K.
This patch changes the data type of both of these elements to u32.
Cc: Ville
This patch series enables programming of Multi-segmented-gamma
palette for ICL.
Shashank Sharma (3):
drm/i915: Change gamma/degamma_lut_size data type to u32
drm/i915: Rename ivb_load_lut_10_max
drm/i915/icl: Add Multi-segmented gamma support
Uma Shankar (1):
drm/i915/icl: Add register
linux/commits/Christian-K-nig/dma-buf-add-struct-dma_buf_attach_info-v2/20190430-221017
config: xtensa-allyesconfig (attached as .config)
compiler: xtensa-linux-gcc (GCC) 8.1.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
== Series Details ==
Series: drm/i915: Corrupt DSI picture fix for GeminiLake
URL : https://patchwork.freedesktop.org/series/60084/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Corrupt DSI picture fix for GeminiLake
On Tue, Apr 30, 2019 at 10:22:40AM +0530, Sharma, Shashank wrote:
>
> On 4/26/2019 8:07 PM, Ville Syrjälä wrote:
> > On Fri, Apr 26, 2019 at 06:40:11PM +0530, Sharma, Shashank wrote:
> >> On 4/13/2019 12:00 AM, Ville Syrjala wrote:
> >>> From: Ville Syrjälä
> >>>
> >>> The pipe has a special HDR
On 29/04/2019 19:00, Chris Wilson wrote:
Asking the GPU to busywait on a memory address, perhaps not unexpectedly
in hindsight for a shared system, leads to bus contention that affects
CPU programs trying to concurrently access memory. This can manifest as
a drop in transcode throughput on
On Mon, 29 Apr 2019, Stuart Summers wrote:
> In the GETPARAM ioctl handler, use a local variable to consolidate
> usage of SSEU runtime info.
>
> Cc: Daniele Ceraolo Spurio
> Signed-off-by: Stuart Summers
> ---
> drivers/gpu/drm/i915/i915_drv.c | 11 ++-
> 1 file changed, 6
On Tue, 30 Apr 2019, Vandita Kulkarni wrote:
> Read back the pixel fomrat register and get the bpp.
>
> v2: Read the PIPE_MISC register (Jani).
>
> Signed-off-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 3 +++
> drivers/gpu/drm/i915/intel_dsi.h | 1 +
>
If we couple the scheduler more tightly with the execlists policy, we
can apply the preemption policy to the question of whether we need to
kick the tasklet at all for this priority bump.
v2: Rephrase it as a core i915 policy and not an execlists foible.
Signed-off-by: Chris Wilson
Cc: Tvrtko
When the system is idling, contention for struct_mutex should be low and
so we will be more efficient to wait for a contended mutex than
reschedule.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_pm.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git
== Series Details ==
Series: drm/i915: Corrupt DSI picture fix for GeminiLake
URL : https://patchwork.freedesktop.org/series/60084/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6014 -> Patchwork_12902
Summary
---
Add a structure for the parameters of dma_buf_attach, this makes it much easier
to add new parameters later on.
v2: rebase cleanup and fix all new implementations as well
Signed-off-by: Christian König
---
drivers/dma-buf/dma-buf.c | 13 +++--
On 4/29/2019 7:42 PM, Jani Nikula wrote:
On Fri, 26 Apr 2019, Shashank Sharma wrote:
From: Uma Shankar
Add macros to define multi segmented gamma registers
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 17 +
1
On Mon, 29 Apr 2019, Stuart Summers wrote:
> Signed-off-by: Stuart Summers
> ---
> drivers/gpu/drm/i915/gt/intel_sseu.h | 47
> drivers/gpu/drm/i915/intel_device_info.h | 47
> 2 files changed, 47 insertions(+), 47 deletions(-)
>
> diff
Quoting Tvrtko Ursulin (2019-04-30 09:55:59)
>
> On 29/04/2019 19:00, Chris Wilson wrote:
> > Asking the GPU to busywait on a memory address, perhaps not unexpectedly
> > in hindsight for a shared system, leads to bus contention that affects
> > CPU programs trying to concurrently access memory.
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Ville
>Syrjälä
>Sent: Friday, April 26, 2019 8:07 PM
>To: Sharma, Shashank
>Cc: intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable pipe HDR mode on
HI,
> -Original Message-
> From: Lisovskiy, Stanislav
> Sent: tiistai 30. huhtikuuta 2019 11.01
> To: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com
> Cc: Saarinen, Jani ; Peres, Martin
>
> Subject: Re: [Intel-gfx] [PATCH v2] drm/i915: Corrupt DSI picture fix for
>
On Mon, 29 Apr 2019, Stuart Summers wrote:
> Currently, the subslice_mask runtime parameter is stored as an
> array of subslices per slice. Expand the subslice mask array to
> better match what is presented to userspace through the
> I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
>
Quoting Tvrtko Ursulin (2019-04-30 09:55:59)
>
> On 29/04/2019 19:00, Chris Wilson wrote:
> So I am still leaning towards being cautious and just abandoning
> semaphores for now.
Fwiw, we have another 4 weeks to pull the plug for 5.2.
-Chris
___
On Thu, 04 Apr 2019, Aditya Swarup wrote:
> On Tue, Apr 02, 2019 at 05:14:40AM -0700, Aditya Swarup wrote:
>> Adding N & CTS values for 10/12 bit deep color from Appendix C
>> table in HDMI 2.0 spec. The correct values for N is not chosen
>> automatically by hardware for deep color modes.
>>
>>
Replace the racy continuation check within retire_work with a definite
kill-switch on idling. The race was being exposed by gem_concurrent_blit
where the retire_worker would be terminated too early leaving us
spinning in debugfs/i915_drop_caches with nothing flushing the
retirement queue.
Quoting Joonas Lahtinen (2019-04-30 08:24:07)
> Quoting Jani Nikula (2019-04-29 16:03:33)
> > On Mon, 29 Apr 2019, Chris Wilson wrote:
> > > Quoting Jani Nikula (2019-04-29 13:29:37)
> > >> Commit 696173b064c6 ("drm/i915: extract intel_pm.h from intel_drv.h")
> > >> missed the declarations in
Quoting Jani Nikula (2019-04-29 13:29:18)
> Continue the header refactoring started in part one [1].
>
> BR,
> Jani.
>
> [1] https://patchwork.freedesktop.org/series/59022/
>
>
> Jani Nikula (21):
> drm/i915: ensure more headers remain self-contained
> drm/i915: make intel_bios.h
== Series Details ==
Series: series starting with [1/5] drm/i915: Wait for the struct_mutex on idling
URL : https://patchwork.freedesktop.org/series/60072/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6012_full -> Patchwork_12899_full
Quoting Tvrtko Ursulin (2019-04-18 13:06:34)
> From: Tvrtko Ursulin
>
> WaEnableStateCacheRedirectToCS context workaround configures the L3 cache
> to benefit 3d workloads but media has different requirements.
>
> Remove the workaround and whitelist the register to allow any userspace
>
Hi Dave & Daniel,
Just one fix to fix Icelake CSC programming (fixes loss of blue channel).
Best Regards, Joonas
***
drm-intel-next-fixes-2019-04-30:
- Fix to Icelake CSC losing blue channel
The following changes since commit 447811a686e8da7325516a78069ccfbd139ef1a7:
drm/i915/icl: Fix
On Tue, 30 Apr 2019, Stanislav Lisovskiy wrote:
> Currently due to regression CI machine
> displays show corrupt picture.
> Problem is when CDCLK is as low as 79200, picture gets
> unstable, while DSI and DE pll values were
> confirmed to be correct.
> Limiting to 158400 as agreed with Ville.
>
>
== Series Details ==
Series: drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color
(rev8)
URL : https://patchwork.freedesktop.org/series/58912/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6012 -> Patchwork_12900
== Series Details ==
Series: drm/i915/icl: Fix setting 10 bit deep color mode
URL : https://patchwork.freedesktop.org/series/60080/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6012 -> Patchwork_12901
Summary
---
On Tue, 2019-04-30 at 10:43 +0300, Jani Nikula wrote:
> On Tue, 30 Apr 2019, Stanislav Lisovskiy <
> stanislav.lisovs...@intel.com> wrote:
> > Currently due to regression CI machine
> > displays show corrupt picture.
> > Problem is when CDCLK is as low as 79200, picture gets
> > unstable, while
From: Daniel Drake
On many (all?) the Gemini Lake systems we work with, there is frequent
momentary graphical corruption at the top of the screen, and it seems
that disabling framebuffer compression can avoid this.
The ticket was reported 6 months ago and has already affected a
multitude of
On 30/04/2019 07:53, Joonas Lahtinen wrote:
Quoting Tvrtko Ursulin (2019-04-18 13:06:34)
From: Tvrtko Ursulin
WaEnableStateCacheRedirectToCS context workaround configures the L3 cache
to benefit 3d workloads but media has different requirements.
Remove the workaround and whitelist the
>
> + /*
> + * On Geminilake once the CDCLK gets as low as 79200
> + * picture gets unstable, despite that values are
> + * correct for DSI PLL and DE PLL.
> + */
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> + IS_GEMINILAKE(dev_priv))
> +
== Series Details ==
Series: series starting with [1/5] drm/i915: Wait for the struct_mutex on idling
URL : https://patchwork.freedesktop.org/series/60072/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6012 -> Patchwork_12899
On 30/04/2019 11:01, Lisovskiy, Stanislav wrote:
> On Tue, 2019-04-30 at 10:43 +0300, Jani Nikula wrote:
>> On Tue, 30 Apr 2019, Stanislav Lisovskiy <
>> stanislav.lisovs...@intel.com> wrote:
>>> Currently due to regression CI machine
>>> displays show corrupt picture.
>>> Problem is when CDCLK is
Read back the pixel fomrat register and get the bpp.
v2: Read the PIPE_MISC register (Jani).
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/icl_dsi.c | 3 +++
drivers/gpu/drm/i915/intel_dsi.h | 1 +
drivers/gpu/drm/i915/vlv_dsi.c | 2 +-
3 files changed, 5 insertions(+), 1
Adjust the get transcoder timings for mipi dsi as per the
set timing calculations.
v2: Use the existing intel_get_pipe_timings and do the dsi
specific adjustments in the encoder get_config hook.(Ville, Jani)
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/icl_dsi.c | 29
In case of dual link mode, the mode clock that we get
from the VBT is halved.
v2: Simplify the calculation (Jani).
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/icl_dsi.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c
Currently due to regression CI machine
displays show corrupt picture.
Problem is when CDCLK is as low as 79200, picture gets
unstable, while DSI and DE pll values were
confirmed to be correct.
Limiting to 158400 as agreed with Ville.
We could not come up with any better solution
yet, as PLL
Op 29-04-2019 om 17:10 schreef Stanislav Lisovskiy:
> When CDCLK is as low as 79200, picture gets
> unstable, while DSI and DE pll values were
> confirmed to be correct.
> Limiting to 158400 as agreed with Ville.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/intel_cdclk.c |
Quoting Jani Nikula (2019-04-29 16:03:33)
> On Mon, 29 Apr 2019, Chris Wilson wrote:
> > Quoting Jani Nikula (2019-04-29 13:29:37)
> >> Commit 696173b064c6 ("drm/i915: extract intel_pm.h from intel_drv.h")
> >> missed the declarations in i915_drv.h.
> >
> > Fwiw, I want to pull these along with
== Series Details ==
Series: i915: disable framebuffer compression on GeminiLake
URL : https://patchwork.freedesktop.org/series/60090/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6014 -> Patchwork_12904
Summary
---
On Thu, 25 Apr 2019, Imre Deak wrote:
> Factor out the combo PHY lane power configuration code to a separate
> helper; it will be also needed by the next patch adding the same
> configuration for DDI ports.
>
> Add support for DDI ports and lane reversal as preparation for the next
> patch.
>
>
> -Original Message-
> From: Nikula, Jani
> Sent: Tuesday, April 30, 2019 6:16 PM
> To: Kulkarni, Vandita ; intel-
> g...@lists.freedesktop.org
> Cc: Syrjala, Ville
> Subject: Re: [Intel-gfx] [v2 2/3] drm/i915: Fix pipe config mismatch for bpp,
> output format
>
> On Tue, 30 Apr 2019,
Currently due to regression CI machine
displays show corrupt picture.
Problem is when CDCLK is as low as 79200, picture gets
unstable, while DSI and DE pll values were
confirmed to be correct.
Limiting to 158400 as agreed with Ville.
We could not come up with any better solution
yet, as PLL
> -Original Message-
> From: Nikula, Jani
> Sent: Tuesday, April 30, 2019 3:03 PM
> To: Kulkarni, Vandita ; intel-
> g...@lists.freedesktop.org
> Cc: Syrjala, Ville ; Shankar, Uma
> ; Kulkarni, Vandita
> Subject: Re: [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output
> format
On Tue, 30 Apr 2019, Stanislav Lisovskiy wrote:
> Currently due to regression CI machine
> displays show corrupt picture.
> Problem is when CDCLK is as low as 79200, picture gets
> unstable, while DSI and DE pll values were
> confirmed to be correct.
> Limiting to 158400 as agreed with Ville.
>
>
Currently due to regression CI machine
displays show corrupt picture.
Problem is when CDCLK is as low as 79200, picture gets
unstable, while DSI and DE pll values were
confirmed to be correct.
Limiting to 158400 as agreed with Ville.
We could not come up with any better solution
yet, as PLL
== Series Details ==
Series: series starting with [v2,1/3] drm/i915: Fix the pipe state timing
mismatch warnings
URL : https://patchwork.freedesktop.org/series/60094/
State : failure
== Summary ==
Applying: drm/i915: Fix the pipe state timing mismatch warnings
Applying: drm/i915: Fix pipe
== Series Details ==
Series: drm/i915/csr: alpha_support doesn't depend on csr or vice versa (rev2)
URL : https://patchwork.freedesktop.org/series/60062/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6014 -> Patchwork_12903
On Tue, 30 Apr 2019, Chris Wilson wrote:
> Quoting Jani Nikula (2019-04-29 13:29:18)
>> Continue the header refactoring started in part one [1].
>>
>> BR,
>> Jani.
>>
>> [1] https://patchwork.freedesktop.org/series/59022/
>>
>>
>> Jani Nikula (21):
>> drm/i915: ensure more headers remain
On 30/04/2019 10:44, Chris Wilson wrote:
When the system is idling, contention for struct_mutex should be low and
so we will be more efficient to wait for a contended mutex than
reschedule.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_pm.c | 8 +---
1 file changed, 1
Work on the principle that files should prefer not to expose platform
specific functions.
v2: Rebase
Cc: Imre Deak
Reviewed-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_combo_phy.c | 24
drivers/gpu/drm/i915/intel_combo_phy.h | 6
On Tue, 30 Apr 2019, "Kulkarni, Vandita" wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Tuesday, April 30, 2019 3:03 PM
>> To: Kulkarni, Vandita ; intel-
>> g...@lists.freedesktop.org
>> Cc: Syrjala, Ville ; Shankar, Uma
>> ; Kulkarni, Vandita
>> Subject: Re: [v2 2/3]
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