== Series Details ==
Series: drm/i915/tgl: Lower cdclk for sub 4k resolutions
URL : https://patchwork.freedesktop.org/series/65475/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6748 -> Patchwork_14100
Summary
---
On Sat, Aug 17, 2019 at 02:38:53AM -0700, Lucas De Marchi wrote:
From: Michel Thierry
GAM registers located in the 0x4xxx range have been relocated to 0xCxxx;
this is to make space for global MOCS registers.
HSD: 399379
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
Signed-off-by:
== Series Details ==
Series: series starting with [1/3] drm/i915: Switch obj->mm.lock lockdep
annotations on its head
URL : https://patchwork.freedesktop.org/series/65467/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6743_full -> Patchwork_14096_full
On Tue, Aug 20, 2019 at 10:19:01AM +0200, Daniel Vetter wrote:
> In some special cases we must not block, but there's not a
> spinlock, preempt-off, irqs-off or similar critical section already
> that arms the might_sleep() debug checks. Add a non_block_start/end()
> pair to annotate these.
>
>
On 8/20/19 12:54 PM, Daniel Vetter wrote:
The cpu (de)tiler hw is gone, this stopped being useful. Plus it never
supported any of the fancy new tiling formats, which means userspace
also stopped using the magic side-channel this provides.
This would totally break a lot of the igts, but
Hi,
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag,
fixing commit: 5ca0ef8a56b8 drm/i915: Add max_bpc property for DP MST.
The bot has tested the following trees: v5.2.9.
v5.2.9: Failed to apply! Possible dependencies:
Unable to calculate
== Series Details ==
Series: RFC/T: dma_resv vs. mmap_sem
URL : https://patchwork.freedesktop.org/series/65488/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6749 -> Patchwork_14107
Summary
---
**FAILURE**
On Tue, Aug 20, 2019 at 8:55 PM Chris Wilson wrote:
>
> Quoting Daniel Vetter (2019-08-20 18:06:31)
> > The cpu (de)tiler hw is gone, this stopped being useful. Plus it never
> > supported any of the fancy new tiling formats, which means userspace
> > also stopped using the magic side-channel
== Series Details ==
Series: drm/i915: disable set/get_tiling ioctl on gen12+
URL : https://patchwork.freedesktop.org/series/65495/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6749 -> Patchwork_14109
Summary
---
== Series Details ==
Series: drm/i915: Serialize insertion into the file->mm.request_list
URL : https://patchwork.freedesktop.org/series/65468/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6743_full -> Patchwork_14097_full
== Series Details ==
Series: drm/i915: disable set/get_tiling ioctl on gen12+ (rev2)
URL : https://patchwork.freedesktop.org/series/65495/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5281445913b8 drm/i915: disable set/get_tiling ioctl on gen12+
-:56:
On Sat, Aug 17, 2019 at 02:38:43AM -0700, Lucas De Marchi wrote:
From: Michel Thierry
HCP/MFX power gating is disabled by default, turn it on for the vd units
available. User space will also issue a MI_FORCE_WAKEUP properly to
wake up proper subwell.
During driver load, init_clock_gating
The cpu (de)tiler hw is gone, this stopped being useful. Plus it never
supported any of the fancy new tiling formats, which means userspace
also stopped using the magic side-channel this provides.
This would totally break a lot of the igts, but they're already broken
for the same reasons as
== Series Details ==
Series: drm/i915: Serialise the fill BLT with the vma pinning (rev2)
URL : https://patchwork.freedesktop.org/series/65482/
State : failure
== Summary ==
Applying: drm/i915: Serialise the fill BLT with the vma pinning
Using index info to reconstruct a base tree...
M
== Series Details ==
Series: drm/i915/gtt: Relax pd_used assertion
URL : https://patchwork.freedesktop.org/series/65484/
State : failure
== Summary ==
Applying: drm/i915/gtt: Relax pd_used assertion
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_gem_gtt.c
Quoting Summers, Stuart (2019-08-20 20:01:05)
> On Tue, 2019-08-20 at 11:53 +0100, Chris Wilson wrote:
> > Quoting Stuart Summers (2019-08-19 22:50:00)
> > > Add a new function to determine whether a particular slice
> > > has a given subslice.
> > >
> > > Signed-off-by: Stuart Summers
> > > ---
Hi Maarten,
For this patch, you want me to modify it such that if (slave && needs_modeset)
then
dont do anything since the slave update crtc and pipe an dplane updates will
happen with master.
So if(master && needs_modeset) {
obtain slaves from slave_mask
obtain corresponding slave crtc state
== Series Details ==
Series: Tiger Lake batch 3 (rev3)
URL : https://patchwork.freedesktop.org/series/65290/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6743_full -> Patchwork_14094_full
Summary
---
**SUCCESS**
On 8/20/19 8:42 AM, Michal Wajdeczko wrote:
On Tue, 20 Aug 2019 04:01:47 +0200, Daniele Ceraolo Spurio
wrote:
diff --git a/drivers/gpu/drm/i915/intel_reg_types.h
b/drivers/gpu/drm/i915/intel_reg_types.h
new file mode 100644
index ..87bce80dd5ed
--- /dev/null
+++
== Series Details ==
Series: drm/i915: Do not create a new max_bpc prop for MST connectors
URL : https://patchwork.freedesktop.org/series/65493/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6749 -> Patchwork_14108
Summary
On Sat, Aug 17, 2019 at 02:38:28AM -0700, Lucas De Marchi wrote:
From: José Roberto de Souza
According to PSR2_CTL definition in BSpec there is only one instance of
PSR2_CTL. Platforms gen < 12 with EDP transcoder only support PSR2 on
TRANSCODER_EDP while on TGL PSR2 is only supported by
On Tue, 2019-08-20 at 13:16 -0700, Lucas De Marchi wrote:
> On Sat, Aug 17, 2019 at 02:38:27AM -0700, Lucas De Marchi wrote:
> > From: José Roberto de Souza
> >
> > PSR registers are a mess, some have the full address while others
> > just
> > have the additional offset from psr_mmio_base.
> >
== Series Details ==
Series: drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev4)
URL : https://patchwork.freedesktop.org/series/63432/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6743_full -> Patchwork_14093_full
Summary
== Series Details ==
Series: RFC/T: dma_resv vs. mmap_sem
URL : https://patchwork.freedesktop.org/series/65488/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4823a79936e3 dma_resv: prime lockdep annotations
-:65: WARNING:BAD_SIGN_OFF: email address '"VMware Graphics"
' might
On Tue, 2019-08-20 at 11:53 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-19 22:50:00)
> > Add a new function to determine whether a particular slice
> > has a given subslice.
> >
> > Signed-off-by: Stuart Summers
> > ---
> > drivers/gpu/drm/i915/gt/intel_sseu.h | 10
The cpu (de)tiler hw is gone, this stopped being useful. Plus it never
supported any of the fancy new tiling formats, which means userspace
also stopped using the magic side-channel this provides.
This would totally break a lot of the igts, but they're already broken
for the same reasons as
On Sat, Aug 17, 2019 at 02:38:29AM -0700, Lucas De Marchi wrote:
From: José Roberto de Souza
No need to unmask PSR interrutpion if PSR is not enabled, better move
the call to intel_psr_enable_source().
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
The dma-fence selftest uses an on-stack timer that requires explicit
annotation for debugobjects.
Signed-off-by: Chris Wilson
Cc: Daniel Vetter
---
drivers/dma-buf/st-dma-fence.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/dma-buf/st-dma-fence.c
On Fri, Aug 09, 2019 at 11:47:12AM +0300, Imre Deak wrote:
> On Fri, Aug 09, 2019 at 06:55:53AM +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915: Fix HW readout for crtc_clock in HDMI mode (rev2)
> > URL : https://patchwork.freedesktop.org/series/64909/
> > State :
On Tue, Aug 20, 2019 at 01:35:37PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Kahola, Mika
> >Sent: Tuesday, August 20, 2019 4:37 PM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Shankar, Uma ; Kahola, Mika
> >
> >Subject: [PATCH] drm/i915/tgl: Lower cdclk for sub 4k
The current assertion tries to make sure that we do not over count the
number of used PDE inside a page directory -- that is with an array of
512 pde, we do not expect more than 512 elements used! However, our
assertion has to take into account that as we pin an element into the
page directory,
On 2019-08-20 at 16:40:19 +0300, Jani Nikula wrote:
> It's static const data, make it so.
>
> Cc: Ramalingam C
> Signed-off-by: Jani Nikula
Reviewed-by: Ramalingam C
-Ram
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff
On Tue, 20 Aug 2019, Ville Syrjälä wrote:
> On Tue, Aug 20, 2019 at 04:40:15PM +0300, Jani Nikula wrote:
>> Split struct declaration and array definition. Fix indents and
>> whitespace. No functional changes.
>>
>> Cc: Ramalingam C
>> Signed-off-by: Jani Nikula
>> ---
>>
Am 20.08.19 um 16:53 schrieb Daniel Vetter:
> Full audit of everyone:
>
> - i915, radeon, amdgpu should be clean per their maintainers.
>
> - vram helpers should be fine, they don't do command submission, so
>really no business holding struct_mutex while doing copy_*_user. But
>I haven't
Am 20.08.19 um 17:41 schrieb Daniel Vetter:
> On Tue, Aug 20, 2019 at 5:34 PM Koenig, Christian
> wrote:
>> Am 20.08.19 um 17:21 schrieb Daniel Vetter:
>>> On Tue, Aug 20, 2019 at 5:16 PM Koenig, Christian
>>> wrote:
Am 20.08.19 um 16:53 schrieb Daniel Vetter:
> With nouveau fixed all
On Tue, 20 Aug 2019, Ramalingam C wrote:
> On 2019-08-20 at 14:14:03 +0530, Winkler, Tomas wrote:
>>
>>
>> >
>> > For the reusability of the enum transcoder and enum pipe in other driver
>> > modules (like mei_hdcp), enum port definition is moved from I915 local
>> > header
>> >
On 2019-08-20 at 15:30:53 +0300, Jani Nikula wrote:
> On Tue, 20 Aug 2019, Ramalingam C wrote:
> > On 2019-08-20 at 14:14:03 +0530, Winkler, Tomas wrote:
> >>
> >>
> >> >
> >> > For the reusability of the enum transcoder and enum pipe in other driver
> >> > modules (like mei_hdcp), enum port
On Tue, 2019-08-20 at 16:03 +0300, Ville Syrjälä wrote:
> On Tue, Aug 20, 2019 at 02:06:31PM +0300, Mika Kahola wrote:
> > In order to achieve improved power savings we can tune down CD
> > clock frequency
> > for sub 4k resolutions. The maximum CD clock frequency for sub 4k
> > resolutions is set
On Sat, Aug 17, 2019 at 02:58:45AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Sanitize PHY state during display core uninit
> URL : https://patchwork.freedesktop.org/series/65298/
> State : success
Thanks for the review, pushed to -dinq.
>
> == Summary ==
>
> CI
Split struct declaration and array definition. Fix indents and
whitespace. No functional changes.
Cc: Ramalingam C
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 39 +++
1 file changed, 19 insertions(+), 20 deletions(-)
diff --git
Split struct declaration and array definition. Fix indents and
whitespace. No functional changes.
Cc: Ramalingam C
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 70 +
1 file changed, 36 insertions(+), 34 deletions(-)
diff --git
Everything seems to be all right, but shadowing is to be avoided.
Cc: Ramalingam C
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
It's static const data, make it so.
Cc: Ramalingam C
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index
It's static const data, make it so.
Cc: Ramalingam C
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index
Quoting Daniel Vetter (2019-08-20 15:53:34)
> Full audit of everyone:
>
> - i915, radeon, amdgpu should be clean per their maintainers.
>
> - vram helpers should be fine, they don't do command submission, so
> really no business holding struct_mutex while doing copy_*_user. But
> I haven't
== Series Details ==
Series: Tiger Lake batch 3 (rev3)
URL : https://patchwork.freedesktop.org/series/65290/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6743 -> Patchwork_14094
Summary
---
**FAILURE**
Serious
Always put_filesystem() in i915_gemfs_init().
Signed-off-by: Sergey Senozhatsky
---
- v2: rebased (i915 does not remount gemfs anymore)
drivers/gpu/drm/i915/gem/i915_gemfs.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gemfs.c
Modules, e.g. i915, can use exported get_fs_type(), but are
unable to put_filesystem(). Export it and let modules to
decrement file systems' reference counters.
Signed-off-by: Sergey Senozhatsky
---
fs/filesystems.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/fs/filesystems.c
On 8/19/19 4:48 PM, Neil Armstrong wrote:
> Hi Dariusz, Hans,
>
> I can apply the dw-hdmi patches if necessary.
I'd appreciate it if you can do that.
Thanks,
Hans
>
> Neil
>
> On 19/08/2019 11:38, Hans Verkuil wrote:
>> Hi all,
>>
>> The patches in this series can be applied
Make sure that we wait for the vma to be pinned prior to telling the GPU
to fill the pages through that vma.
However, since our async operations fight over obj->resv->excl_fence we
must manually order them. This makes it much more fragile, and gives an
outside observer the chance to see the
Am 20.08.19 um 16:53 schrieb Daniel Vetter:
> With nouveau fixed all ttm-using drives have the correct nesting of
> mmap_sem vs dma_resv, and we can just lock the buffer.
>
> Assuming I didn't screw up anything with my audit of course.
>
> Signed-off-by: Daniel Vetter
> Cc: Christian Koenig
>
== Series Details ==
Series: drm/i915/tgl: Gen12 csb support (rev3)
URL : https://patchwork.freedesktop.org/series/62890/
State : failure
== Summary ==
Applying: drm/i915/tgl: Gen12 csb support
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/gt/intel_lrc.c
Falling
On Tue, Aug 20, 2019 at 02:06:31PM +0300, Mika Kahola wrote:
> In order to achieve improved power savings we can tune down CD clock frequency
> for sub 4k resolutions. The maximum CD clock frequency for sub 4k
> resolutions is set to 172.8 MHz.
>
> Signed-off-by: Mika Kahola
> ---
>
On 2019-08-20 at 16:40:18 +0300, Jani Nikula wrote:
> Split struct declaration and array definition. Fix indents and
> whitespace. No functional changes.
>
> Cc: Ramalingam C
> Signed-off-by: Jani Nikula
Reviewed-by: Ramalingam C
-Ram
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 39
On 2019-08-20 at 16:40:17 +0300, Jani Nikula wrote:
> It's static const data, make it so.
>
> Cc: Ramalingam C
> Signed-off-by: Jani Nikula
Reviewed-by: Ramalingam C
-Ram
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
>
The current assertion tries to make sure that we do not over count the
number of used PDE inside a page directory -- that is with an array of
512 pde, we do not expect more than 512 elements used! However, our
assertion has to take into account that as we pin an element into the
page directory,
We can reduce the locking for fence registers from the dev->struct_mutex
to a local mutex. We could introduce a mutex for the sole purpose of
tracking the fence acquisition, except there is a little bit of overlap
with the fault tracking, so use the i915_ggtt.mutex as it covers both.
When under severe stress for GTT mappable space, the LRU eviction model
falls off a cliff. We spend all our time scanning the much large
non-mappable vma searching for something within the mappable zone we can
evict. Turn this on its head by only using the full vma if it is already
pinned in the
Avoid calling i915_vma_put_fence() by using our alternate paths that
bind a secondary vma avoiding the original fenced vma. For the few
instances where we need to release the fence (i.e. on binding when the
GGTT range becomes invalid), replace the put_fence with a revoke_fence.
Signed-off-by:
Since we want to revoke the ggtt vma from only under the ggtt->mutex, we
need to move protection of the userfault tracking from the struct_mutex
to the ggtt->mutex.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 10 +++---
drivers/gpu/drm/i915/i915_debugfs.c
The premise here is to simply avoiding having to acquire the vm->mutex
inside vma create/destroy to update the vm->unbound_lists, to avoid some
nasty lock recursions later.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c
Am 20.08.19 um 17:21 schrieb Daniel Vetter:
> On Tue, Aug 20, 2019 at 5:16 PM Koenig, Christian
> wrote:
>> Am 20.08.19 um 16:53 schrieb Daniel Vetter:
>>> With nouveau fixed all ttm-using drives have the correct nesting of
>>> mmap_sem vs dma_resv, and we can just lock the buffer.
>>>
>>>
== Series Details ==
Series: drm/i915/tgl: Lower cdclk for sub 4k resolutions
URL : https://patchwork.freedesktop.org/series/65475/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0fb206f34d2d drm/i915/tgl: Lower cdclk for sub 4k resolutions
-:6: WARNING:COMMIT_LOG_LONG_LINE:
== Series Details ==
Series: drm/i915/tgl: Lower cdclk for sub 4k resolutions
URL : https://patchwork.freedesktop.org/series/65475/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: Lower cdclk for sub 4k resolutions
>-Original Message-
>From: Kahola, Mika
>Sent: Tuesday, August 20, 2019 4:37 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma ; Kahola, Mika
>
>Subject: [PATCH] drm/i915/tgl: Lower cdclk for sub 4k resolutions
>
>In order to achieve improved power savings we can tune down CD
Make sure that we wait for the vma to be pinned prior to telling the GPU
to fill the pages through that vma.
However, since our async operations fight over obj->resv->excl_fence we
must manually order them. This makes it much more fragile, and gives an
outside observer the chance to see the
== Series Details ==
Series: drm/i915/uc: define GuC and HuC FWs for EHL
URL : https://patchwork.freedesktop.org/series/65444/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741_full -> Patchwork_14090_full
Summary
---
On Tue, Aug 20, 2019 at 04:40:15PM +0300, Jani Nikula wrote:
> Split struct declaration and array definition. Fix indents and
> whitespace. No functional changes.
>
> Cc: Ramalingam C
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 70 +
>
On 2019-08-20 at 16:40:15 +0300, Jani Nikula wrote:
> Split struct declaration and array definition. Fix indents and
> whitespace. No functional changes.
>
Reviewed-by: Ramalingam C
-Ram
> Cc: Ramalingam C
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 70
== Series Details ==
Series: series starting with [1/3] drm/i915: Switch obj->mm.lock lockdep
annotations on its head
URL : https://patchwork.freedesktop.org/series/65467/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6743 -> Patchwork_14096
Quoting Mika Kuoppala (2019-08-20 15:25:50)
> Chris Wilson writes:
>
> > The current assertion tries to make sure that we do not over count the
> > number of used PDE inside a page directory -- that is with an array of
> > 512 pde, we do not expect more than 512 elements used! However, our
> >
On Wed, 14 Aug 2019, Animesh Manna wrote:
> Yes, have missed and local build also could not catch as maybe object
> files were present in that directory.
> Fixed the issue and latest trybot link -
> https://patchwork.freedesktop.org/series/65161/
I don't have the patches. I'm not subscribed to
>> >-Original Message-
>> >From: Kahola, Mika
>> >Sent: Tuesday, August 20, 2019 4:37 PM
>> >To: intel-gfx@lists.freedesktop.org
>> >Cc: Shankar, Uma ; Kahola, Mika
>> >
>> >Subject: [PATCH] drm/i915/tgl: Lower cdclk for sub 4k resolutions
>> >
>> >In order to achieve improved power
On Tue, 20 Aug 2019 04:01:47 +0200, Daniele Ceraolo Spurio
wrote:
diff --git a/drivers/gpu/drm/i915/intel_reg_types.h
b/drivers/gpu/drm/i915/intel_reg_types.h
new file mode 100644
index ..87bce80dd5ed
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_reg_types.h
+
+typedef
On Tue, Aug 20, 2019 at 5:34 PM Koenig, Christian
wrote:
>
> Am 20.08.19 um 17:21 schrieb Daniel Vetter:
> > On Tue, Aug 20, 2019 at 5:16 PM Koenig, Christian
> > wrote:
> >> Am 20.08.19 um 16:53 schrieb Daniel Vetter:
> >>> With nouveau fixed all ttm-using drives have the correct nesting of
>
== Series Details ==
Series: mmu notifier debug annotations/checks
URL : https://patchwork.freedesktop.org/series/65465/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6743 -> Patchwork_14095
Summary
---
**SUCCESS**
Quoting Chris Wilson (2019-08-20 12:16:36)
> Quoting Daniele Ceraolo Spurio (2019-08-20 03:01:47)
> > With the introduction of display uncore, we want to categorize registers
> > between display and non-display. To help us getting it right, it will
> > be useful to move the display registers to a
Chris Wilson writes:
> The current assertion tries to make sure that we do not over count the
> number of used PDE inside a page directory -- that is with an array of
> 512 pde, we do not expect more than 512 elements used! However, our
> assertion has to take into account that as we pin an
On Tue, Aug 20, 2019 at 5:16 PM Koenig, Christian
wrote:
>
> Am 20.08.19 um 16:53 schrieb Daniel Vetter:
> > With nouveau fixed all ttm-using drives have the correct nesting of
> > mmap_sem vs dma_resv, and we can just lock the buffer.
> >
> > Assuming I didn't screw up anything with my audit of
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Dynamically allocate s0ix
struct for VLV
URL : https://patchwork.freedesktop.org/series/65445/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741_full -> Patchwork_14091_full
On Tue, Aug 20, 2019 at 01:22:00PM +, Kahola, Mika wrote:
> On Tue, 2019-08-20 at 16:03 +0300, Ville Syrjälä wrote:
> > On Tue, Aug 20, 2019 at 02:06:31PM +0300, Mika Kahola wrote:
> > > In order to achieve improved power savings we can tune down CD
> > > clock frequency
> > > for sub 4k
== Series Details ==
Series: drm/i915: Serialize insertion into the file->mm.request_list
URL : https://patchwork.freedesktop.org/series/65468/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6743 -> Patchwork_14097
Summary
On Tue, Aug 20, 2019 at 10:34:18AM -0300, Jason Gunthorpe wrote:
> On Tue, Aug 20, 2019 at 10:19:02AM +0200, Daniel Vetter wrote:
> > We need to make sure implementations don't cheat and don't have a
> > possible schedule/blocking point deeply burried where review can't
> > catch it.
> >
> > I'm
== Series Details ==
Series: Tiger Lake batch 3 (rev3)
URL : https://patchwork.freedesktop.org/series/65290/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6743 -> Patchwork_14094
Summary
---
**SUCCESS**
No
On 2019-08-20 at 16:40:16 +0300, Jani Nikula wrote:
> Everything seems to be all right, but shadowing is to be avoided.
>
> Cc: Ramalingam C
> Signed-off-by: Jani Nikula
Reviewed-by: Ramalingam C
-Ram
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 8
> 1 file changed, 4
With nouveau fixed all ttm-using drives have the correct nesting of
mmap_sem vs dma_resv, and we can just lock the buffer.
Assuming I didn't screw up anything with my audit of course.
Signed-off-by: Daniel Vetter
Cc: Christian Koenig
Cc: Huang Rui
Cc: Gerd Hoffmann
Cc: "VMware Graphics"
Cc:
Hi all,
As part of all the recent discussions around ttm and dma_resv I started
looking into this. The goal (at least somewhen in the near future) is to
have it all documented and the cross-driver semantics locked down as much
as possible.
One of the biggest issues there is how the dma_resv
Full audit of everyone:
- i915, radeon, amdgpu should be clean per their maintainers.
- vram helpers should be fine, they don't do command submission, so
really no business holding struct_mutex while doing copy_*_user. But
I haven't checked them all.
- panfrost seems to dma_resv_lock only
We can't copy_*_user while holding reservations, that will (soon even
for nouveau) lead to deadlocks. And it breaks the cross-driver
contract around dma_resv.
Fix this by adding a slowpath for when we need relocations, and by
pushing the writeback of the new presumed offsets to the very end.
== Series Details ==
Series: drm/i915: Be defensive when starting vma activity
URL : https://patchwork.freedesktop.org/series/65471/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6743 -> Patchwork_14098
Summary
---
From: Ville Syrjälä
We're not allowed to create new properties after device registration
so for MST connectors we need to either create the max_bpc property
earlier, or we reuse one we already have. Let's do the latter apporach
since the corresponding SST connector already has the prop and its
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