> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Jani
> Nikula
> Sent: Friday, August 30, 2019 7:02 PM
> To: Manna, Animesh ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v4 08/10] drm/i915/dsb: Enable gamma lut
Quoting Jani Nikula (2019-09-02 21:29:16)
> Add a helper instead of open coding the plurals in debug logs. Also
> fixes the case for "0 display pipes available."
>
> Signed-off-by: Jani Nikula
>
> ---
>
> I stumbled upon the pipes one while working on ->num_pipes. I honestly
> thought we'd
Support for HDR10 video was introduced in DisplayPort 1.4.
On GLK+ platform, in order to use DisplayPort HDR10, we need to support
BT.2020 colorimetry and HDR Static metadata.
It implements the CTA-861-G standard for transport of static HDR metadata.
It enables writing of HDR metadata infoframe
In order to use colorspace property to Display Port connectors, it extends
DRM_MODE_CONNECTOR_DisplayPort connector_type on
drm_mode_create_colorspace_property function.
v3: Addressed review comments from Ville
- Add new colorimetry options for DP 1.4a spec.
- Separate set of colorimetry
It refactors and renames a function which handled vsc sdp header and data
block setup for supporting colorimetry format.
Function intel_dp_setup_vsc_sdp handles vsc sdp header and data block
setup for pixel encoding / colorimetry format.
In order to use colorspace information of a connector, it
Function intel_dp_setup_hdr_metadata_infoframe_sdp handles Infoframe SDP
header and data block setup for HDR Static Metadata. It enables writing of
HDR metadata infoframe SDP to panel. Support for HDR video was introduced
in DisplayPort 1.4. It implements the CTA-861-G standard for transport of
According to Bspec, GEN11 and prior GEN11 have different register size for
HDR Metadata Infoframe SDP packet. It adds new VIDEO_DIP_GMP_DATA_SIZE for
GEN11. And it makes handle different register size for
HDMI_PACKET_TYPE_GAMUT_METADATA on hsw_dip_data_size() for each GEN
platforms. It addresses
It attaches HDR metadata property to DP connector on GLK+.
It enables HDR metadata infoframe sdp on GLK+ to be used to send
HDR metadata to DP sink.
v2: Minor style fix
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 +
1 file
When BT.2020 Colorimetry output is used for DP, we should program BT.2020
Colorimetry to MSA and VSC SDP. It adds output_colorspace to
intel_crtc_state struct as a place holder of pipe's output colorspace.
In order to distinguish needed colorimetry for VSC SDP, it adds
intel_dp_needs_vsc_sdp
It attaches the colorspace connector property to a DisplayPort connector.
Based on colorspace change, modeset will be triggered to switch to a new
colorspace.
Based on colorspace property value create a VSC SDP packet with appropriate
colorspace. This would help to enable wider color gamut like
Hi Janusz,
On 9/2/19 4:37 PM, Janusz Krzysztofik wrote:
I am not saying that keeping data is not acceptable. I just want to
check whether there are any other solutions.
Then reverting 458b7c8e0dde and applying this patch still resolves the issue
for me. No errors appear when mappings are
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Jani
> Nikula
> Sent: Friday, August 30, 2019 7:06 PM
> To: Manna, Animesh ; intel-gfx@lists.freedesktop.org
> Cc: Thierry, Michel
> Subject: Re: [Intel-gfx] [PATCH v4 02/10]
On Mon, 2019-09-02 at 17:43 +0300, Ville Syrjälä wrote:
> On Fri, Aug 23, 2019 at 12:52:28PM +0300, Gwan-gyeong Mun wrote:
> > When BT.2020 Colorimetry output is used for DP, we should program
> > BT.2020
> > Colorimetry to MSA and VSC SDP. It adds output_colorspace to
> > intel_crtc_state struct
On Tue, 2019-08-27 at 01:14 +0530, Shankar, Uma wrote:
> > -Original Message-
> > From: Mun, Gwan-gyeong
> > Sent: Friday, August 23, 2019 3:23 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: dri-de...@lists.freedesktop.org; Shankar, Uma <
> > uma.shan...@intel.com>;
> > Sharma,
On Mon, 2019-09-02 at 17:44 +0300, Ville Syrjälä wrote:
> On Fri, Aug 23, 2019 at 12:52:29PM +0300, Gwan-gyeong Mun wrote:
> > In order to use colorspace property to Display Port connectors, it
> > extends
> > DRM_MODE_CONNECTOR_DisplayPort connector_type on
> > drm_mode_create_colorspace_property
On Mon, 2 Sep 2019 at 05:03, Chris Wilson wrote:
>
> The aliasing-ppgtt is not allowed to be smaller than the ggtt, nor
> should we advertise it as being any bigger, or else we may get sued for
> false advertisement.
>
> Testcase: igt/gem_exec_big
> Fixes: 0b718ba1e884 ("drm/i915/gtt: Downgrade
== Series Details ==
Series: series starting with [01/21] drm/i915: Restrict the aliasing-ppgtt to
the size of the ggtt
URL : https://patchwork.freedesktop.org/series/66109/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6818_full -> Patchwork_14255_full
Hi Baolu,
On Thursday, August 29, 2019 11:08:18 AM CEST Lu Baolu wrote:
> Hi,
>
> On 8/29/19 3:58 PM, Janusz Krzysztofik wrote:
> > Hi Baolu,
> >
> > On Thursday, August 29, 2019 3:43:31 AM CEST Lu Baolu wrote:
> >> Hi Janusz,
> >>
> >> On 8/28/19 10:17 PM, Janusz Krzysztofik wrote:
> We
On Mon, 2 Sep 2019 at 05:03, Chris Wilson wrote:
>
> The aliasing-ppgtt is constrained to be the same size as the Global GTT
> since it aliases the same address space. Simplifying gtt size reporting
> in this case.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
On Wed, 28 Aug 2019, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Reogranize the HDMI deep color state computation to just
> loop over possible bpc values. Avoids having to maintain
> so many variants of the clock etc.
>
> The current code also looks confused w.r.t. port_clock vs.
>
On 30/08/2019 18:48, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-08-30 15:47:23)
err_unpin:
- __i915_vma_unpin(vma);
+ mutex_lock(>drm.struct_mutex);
+ i915_vma_unpin_and_release(, 0);
+ mutex_unlock(>drm.struct_mutex);
Strangely unpin_and_release() doesn't
On Fri, Aug 23, 2019 at 06:11:26PM +0100, Chris Wilson wrote:
> obj->pin_global was original used as a means to keep the shrinker off
> the active scanout, but we use the vma->pin_count itself for that and
> the obj->frontbuffer to delay shrinking active framebuffers. The other
> role that
== Series Details ==
Series: drm: Add high-precision time to vblank trace event
URL : https://patchwork.freedesktop.org/series/66132/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
764d6d8263bc drm: Add high-precision time to vblank trace event
-:50:
On Fri, Aug 23, 2019 at 12:52:28PM +0300, Gwan-gyeong Mun wrote:
> When BT.2020 Colorimetry output is used for DP, we should program BT.2020
> Colorimetry to MSA and VSC SDP. It adds output_colorspace to
> intel_crtc_state struct as a place holder of pipe's output colorspace.
> In order to
== Series Details ==
Series: series starting with [1/2] drm/edid: Don't look for CEA data blocks in
CEA ext block rev < 3
URL : https://patchwork.freedesktop.org/series/66131/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6820 -> Patchwork_14257
On Fri, Aug 23, 2019 at 12:52:29PM +0300, Gwan-gyeong Mun wrote:
> In order to use colorspace property to Display Port connectors, it extends
> DRM_MODE_CONNECTOR_DisplayPort connector_type on
> drm_mode_create_colorspace_property function.
>
> Signed-off-by: Gwan-gyeong Mun
> ---
>
== Series Details ==
Series: series starting with [1/2] drm/edid: Don't look for CEA data blocks in
CEA ext block rev < 3
URL : https://patchwork.freedesktop.org/series/66131/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6820_full -> Patchwork_14257_full
== Series Details ==
Series: drm: Add high-precision time to vblank trace event
URL : https://patchwork.freedesktop.org/series/66132/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6820 -> Patchwork_14258
Summary
---
We haven't run into issues with programming the global OA/NOA
registers configuration from CPU so far, but HW engineers actually
recommend doing this from the command streamer. On TGL in particular
one of the clock domain in which some of that programming goes might
not be powered when we poke
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/i915_perf.c | 7 +++
2 files changed, 12 insertions(+)
diff --git
Listing configurations at the moment is supported only through sysfs.
This might cause issues for applications wanting to list
configurations from a container where sysfs isn't available.
This change adds a way to query the number of configurations and their
content through the i915 query uAPI.
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
configuration changes seem to indicate a 60~70us delay. We go with
500us as default for now which should
Reporting this version will help application figure out what level of
the support the running kernel provides.
v2: Add i915_perf_ioctl_version() (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_getparam.c | 4
At some point in time there was the idea that we could have multiple
stream from the same piece of HW but that never materialized and given
the hard time we already have making everything work with the
submission side, there is no real point having this list of 1 element
around.
Signed-off-by:
We want the ability to dispatch a set of command buffer to the
hardware, each with a different OA configuration. To achieve this, we
reuse a couple of fields from the execbuf2 struct (I CAN HAZ
execbuf3?) to notify what OA configuration should be used for a batch
buffer. This requires the process
Here we introduce a mechanism by which the execbuf part of the i915
driver will be able to request that a batch buffer containing the
programming for a particular OA config be created.
We'll execute these OA configuration buffers right before executing a
set of userspace commands so that a
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers). In Vulkan, queries are always limited in scope to a command
buffer. In OpenGL, the lack
Introduces a new parameters to execbuf so that we can specify syncobj
handles as well as timeline points.
v2: Reuse i915_user_extension_fn
v3: Check that the chained extension is only present once (Chris)
v4: Check that dma_fence_chain_find_seqno returns a non NULL fence (Lionel)
v5: Use
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
v2: Check for invalid flags in execbuffer2 (Lionel)
v3: Rename I915_EXEC_EXT -> I915_EXEC_USE_EXTENSIONS (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v1)
Hi all,
Some missing locks of the VMA that Chris spotted in the review. This
also simplifies a bit the execbuf code, again as recommended by Chris.
Cheers,
Lionel Landwerlin (11):
drm/i915: introduce a mechanism to extend execbuf2
drm/i915: add syncobj timeline support
drm/i915/perf: drop
From: Ville Syrjälä
CEA ext block revisions 1 and 2 do not contain the data block
collection. Instead that section of the extension block is
marked as reserved for 8 byte timing descriptors. Revision 3
changed it to contain the CEA data block collection instead.
Most places that iterate the
From: Ville Syrjälä
Let's make cea_db_offsets() a bit more convenient to use by
setting the start/end offsets to zero whenever the data block
collection isn't present. This makes it safe for the caller
to blindly iterate the data blocks even if there are none.
Cc: Jean Delvare
Signed-off-by:
On 05/08/2019 18:08, Andi Shyti wrote:
Hi Chris,
On Tue, Jul 30, 2019 at 02:30:27PM +0100, Chris Wilson wrote:
Push the ring creation flags from the outer GEM context to the inner
intel_cotnext to avoid an unsightly back-reference from inside the
backend.
Signed-off-by: Chris Wilson
looks
On 30/07/2019 14:30, Chris Wilson wrote:
Push the ring creation flags from the outer GEM context to the inner
intel_cotnext to avoid an unsightly back-reference from inside the
typo
backend.
No mention of the pointer overload trick.
Signed-off-by: Chris Wilson
---
Thanks for the review, Daniel. I noticed that my last name was missing
in the initial revision (my git config was messed up). I am sending v2
of this patch to fix this, including your r/b tag.
Cheers, Heinrich
___
Intel-gfx mailing list
Store the timestamp of the current vblank in the new field 'time' of the
vblank trace event. If the timestamp is calculated by a driver that
supports high-precision vblank timing, set the field 'high-prec' to
'true'.
User space can now access actual hardware vblank times via the tracing
== Series Details ==
Series: drm/i915: Vulkan performance query support (rev14)
URL : https://patchwork.freedesktop.org/series/60916/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK
On 24/07/2019 14:05, Tvrtko Ursulin wrote:
On 23/07/2019 16:49, Stuart Summers wrote:
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO
On Fri, Aug 30, 2019 at 03:30:23PM -0700, Matt Roper wrote:
> Most gen7 and gen8 platforms can't do plane scaling, so we need to
> ensure the test doesn't try to do plane scaling on those platforms. The
> legacy non-atomic subtest bakes these platform characteristics into the
> test itself since
Abstract away direct access to ->num_pipes to allow further
refactoring. No functional changes.
Cc: Chris Wilson
Cc: José Roberto de Souza
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 12 ++--
Prepare for making a distinction between not having display and having
disabled display. Add INTEL_DISPLAY_ENABLED() and use it where
HAS_DISPLAY() is used. This is initially duplication, as disabling
display still leads to ->pipe_mask = 0 and HAS_DISPLAY() being false.
Since
Deconflate not having display hardware from having disabled display
hardware, with some collateral improvements.
This doesn't actually fix any of the issues resulting from the two being
conflated, but unblocks fixing both independently.
Read the commit messages for details.
BR,
Jani.
Cc: Chris
Stop setting ->pipe_mask to zero when display is disabled, allowing us
to have different code paths for not actually having display hardware,
and having display hardware disabled. This lets us develop those two
avenues independently.
There are no functional changes for when there is no display.
Replace device info number of pipes with a bit mask of available
pipes. This will prove handy in the future. There's still a bunch of
future work to do to actually allow a non-consecutive mask of pipes, but
it's a start. No functional changes.
Cc: Chris Wilson
Cc: José Roberto de Souza
Cc:
== Series Details ==
Series: drm/i915: deconflate display disable from no display
URL : https://patchwork.freedesktop.org/series/66135/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a903450383fb drm/i915: add INTEL_NUM_PIPES() and use it
f3f10b13127d drm/i915: convert device
Refactor the GT power management interface to work through the GT now
that it is under the control of gt/
Based on a patch by Chris Wilson.
Signed-off-by: Andi Shyti
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt.c | 46
== Series Details ==
Series: drm/i915: deconflate display disable from no display
URL : https://patchwork.freedesktop.org/series/66135/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6821 -> Patchwork_14259
Summary
---
== Series Details ==
Series: drm: Add high-precision time to vblank trace event
URL : https://patchwork.freedesktop.org/series/66132/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6820_full -> Patchwork_14258_full
Summary
Add a helper instead of open coding the plurals in debug logs. Also
fixes the case for "0 display pipes available."
Signed-off-by: Jani Nikula
---
I stumbled upon the pipes one while working on ->num_pipes. I honestly
thought we'd have more users than this, but to my surprise couldn't find
On Mon, Sep 02, 2019 at 07:51:41PM +0300, Ville Syrjälä wrote:
> On Fri, Aug 30, 2019 at 03:30:23PM -0700, Matt Roper wrote:
> > Most gen7 and gen8 platforms can't do plane scaling, so we need to
> > ensure the test doesn't try to do plane scaling on those platforms. The
> > legacy non-atomic
== Series Details ==
Series: drm/i915: add plural() helper for logging plurals
URL : https://patchwork.freedesktop.org/series/66136/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6821 -> Patchwork_14260
Summary
---
== Series Details ==
Series: drm/i915: Hook up GT power management
URL : https://patchwork.freedesktop.org/series/66137/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a6b2b3196efe drm/i915: Hook up GT power management
-:58: CHECK:BRACES: Blank lines aren't necessary before a
== Series Details ==
Series: drm/i915: Hook up GT power management
URL : https://patchwork.freedesktop.org/series/66137/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6821 -> Patchwork_14261
Summary
---
**FAILURE**
Hi Lionel,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[cannot apply to v5.3-rc7 next-20190902]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day
== Series Details ==
Series: drm/i915: add plural() helper for logging plurals
URL : https://patchwork.freedesktop.org/series/66136/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6821_full -> Patchwork_14260_full
Summary
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