In case of tiled displays when the two tiles are sent across two CRTCs
over two separate DP SST connectors, we need a mechanism to synchronize
the two CRTCs and their corresponding transcoders.
So use the master-slave mode where there is one master corresponding
to last horizontal and vertical
As per the display enable sequence, we need to follow the enable sequence
for slaves first with DP_TP_CTL set to Idle and configure the transcoder
port sync register to select the corersponding master, then follow the
enable sequence for master leaving DP_TP_CTL to idle.
At this point the
In the transcoder port sync mode, the slave transcoders mask their vblanks
until master transcoder's vblank so while disabling them, make
sure slaves are disabled first and then the masters.
v4:
* Obtain slave state from master (Maarten)
v3:
* Rebase
v2:
* Use the intel_old_crtc_state_disables()
In case of tiled displays where different tiles are displayed across
different ports, we need to synchronize the transcoders involved.
This patch implements the transcoder port sync feature for
synchronizing one master transcoder with one or more slave
transcoders. This is only enbaled in slave
This clears the transcoder port sync bits of the TRANS_DDI_FUNC_CTL2
register during crtc_disable().
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 23
1 file
After the state is committed, we readout the HW registers and compare
the HW state with the SW state that we just committed.
For Transcdoer port sync, we add master_transcoder and the
salves bitmask to the crtc_state, hence we need to read those during
the HW state readout to avoid pipe state
This patch series addresses all review comments and now the enable and disable
paths follow the method of obtaining slave states from master and updating
master-slaves
in correct order during master modeset.
The ddb allocations and watermarks changes are not addressed here and will be
added
== Series Details ==
Series: Remaining patches to enable Transcoder Port Sync for tiled displays
URL : https://patchwork.freedesktop.org/series/66403/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b5030e9f1630 drm/i915/display/icl: Save Master transcoder in slave's crtc_state
== Series Details ==
Series: Remaining patches to enable Transcoder Port Sync for tiled displays
URL : https://patchwork.freedesktop.org/series/66403/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
___
Intel-gfx
== Series Details ==
Series: DC3CO Support for TGL (rev8)
URL : https://patchwork.freedesktop.org/series/64923/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6850 -> Patchwork_14319
Summary
---
**SUCCESS**
No
== Series Details ==
Series: DC3CO Support for TGL (rev8)
URL : https://patchwork.freedesktop.org/series/64923/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6850_full -> Patchwork_14319_full
Summary
---
**SUCCESS**
Drop the forcewake before libigt tries to wait on it.
Signed-off-by: Chris Wilson
---
benchmarks/gem_wsim.c | 47 +++
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 87f873b0e..337e13f91
Since we are just reading from each debugfs file, any that requires
initial setup may not be fully setup or be left in a state that results
in the file *expectedly* waiting. Use O_NONBLOCK to avoid waits on
external events as we are just peeking for a trivial check that the
files do not explode.
On Sat, Sep 07, 2019 at 10:44:39PM +0530, Anshuman Gupta wrote:
> Add max_dc_state and tgl_set_target_dc_state() API
> in order to enable DC3CO state with existing DC states.
> max_dc_state will enable/disable the desired DC state in
> DC_STATE_EN reg when "DC Off" power well gets disable/enable.
On Sat, Sep 07, 2019 at 10:44:40PM +0530, Anshuman Gupta wrote:
> DC3CO enabling B.Specs sequence requires to enable end configure
> exit scanlines to TRANS_EXITLINE register, programming this register
> has to be part of modeset sequence as this can't be change when
> transcoder or port is
On Sat, Sep 07, 2019 at 10:44:41PM +0530, Anshuman Gupta wrote:
> Add dc3co helper functions to enable/disable psr2 deep sleep.
> Adhere B.Specs by disallow DC3CO state before PSR2 exit.
> Enable PSR2 exitline event and program the desired scanlines
> to exit DC3CO in intel_psr_enable function at
On Sat, Sep 07, 2019 at 10:44:42PM +0530, Anshuman Gupta wrote:
> DC3CO is useful power state, when DMC detects PSR2 idle frame
> while an active video playback, playing 30fps video on 60hz panel
> is the classic example of this use case.
> DC5 and DC6 saves more power, but can't be entered during
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