== Series Details ==
Series: drm/i915/gtt: Make sure the gen6 ppgtt is bound before first use (rev2)
URL : https://patchwork.freedesktop.org/series/66551/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2989952e76ad drm/i915/gtt: Make sure the gen6 ppgtt is bound before first
== Series Details ==
Series: drm/i915/gtt: Make sure the gen6 ppgtt is bound before first use (rev2)
URL : https://patchwork.freedesktop.org/series/66551/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6874 -> Patchwork_14367
On Wed, 11 Sep 2019, Manasi Navare wrote:
> On Wed, Sep 11, 2019 at 12:08:00PM +0300, Jani Nikula wrote:
>> On Tue, 10 Sep 2019, Manasi Navare wrote:
>> > On Tue, Sep 10, 2019 at 11:07:30AM -0700, Manasi Navare wrote:
>> >> On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote:
>> >> > On
== Series Details ==
Series: DSB enablement. (rev6)
URL : https://patchwork.freedesktop.org/series/63013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6874 -> Patchwork_14369
Summary
---
**SUCCESS**
No
== Series Details ==
Series: DSB enablement. (rev6)
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/dsb: feature flag added for display state buffer.
Okay!
== Series Details ==
Series: DSB enablement. (rev6)
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9bb8863660ce drm/i915/dsb: feature flag added for display state buffer.
5d5acdf62c4f drm/i915/dsb: DSB context creation.
== Series Details ==
Series: drm/i915: Disable FBC if BIOS reserved memory (stolen) is unavailable
URL : https://patchwork.freedesktop.org/series/66549/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6874 -> Patchwork_14366
Hi,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Gwan-gyeong Mun
> Sent: torstai 12. syyskuuta 2019 6.25
> To: intel-gfx@lists.freedesktop.org
> Cc: imir...@alum.mit.edu; dri-de...@lists.freedesktop.org
> Subject: [Intel-gfx]
After we manipulate the context to allow replay after a GPU reset, force
that context to be reloaded. This should be a layer of paranoia, for if
the GPU was reset, the context will no longer be resident!
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 1
After a GPU reset, we need to drain all the CS events so that we have an
accurate picture of the execlists state at the time of the reset. Be
paranoid and force a read of the CSB write pointer from memory.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c |
== Series Details ==
Series: series starting with [1/4] drm/i915/tgl: Add missing ddi clock select
during DP init sequence
URL : https://patchwork.freedesktop.org/series/66556/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5fde471c1784 drm/i915/tgl: Add missing ddi clock
On 2019-09-12 at 00:15:32 +, Harry Wentland wrote:
> Adding a couple AMD guys.
>
> I know this is already merged but I have a few questions after some
> internal discussions.
>
> On 2019-05-07 12:27 p.m., Ramalingam C wrote:
> > On every hdcp revocation check request SRM is read from fw file
== Series Details ==
Series: drm/i915/dmc: Update ICL DMC version to v1.09
URL : https://patchwork.freedesktop.org/series/66560/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6874 -> Patchwork_14368
Summary
---
drm-misc-fixes-2019-09-12:
drm-misc-fixes for v5.3 final:
- Constify modes whitelist harder.
- Fix lima driver gem_wait ioctl.
The following changes since commit 424c38a4e32509ae82dc9d7300432295806cb911:
drm/selftests: modes: Add more unit tests for the cmdline parser (2019-08-30
10:21:56
== Series Details ==
Series: drm/i915/dp: Support for DP HDR outputs (rev6)
URL : https://patchwork.freedesktop.org/series/65656/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
eeb0d02345b0 drm/i915/dp: Extend program of VSC Header and DB for Colorimetry
Format
24ada68e93e8
Quoting Tvrtko Ursulin (2019-09-12 10:20:39)
>
> On 11/09/2019 17:38, Chris Wilson wrote:
> > As we track when we put the GT device to sleep upon idling, we can use
> > that callback to sample the current rc6 counters and record the
> > timestamp for estimating samples after that point while
Chris Wilson writes:
> After a GPU reset, we need to drain all the CS events so that we have an
> accurate picture of the execlists state at the time of the reset. Be
> paranoid and force a read of the CSB write pointer from memory.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
>
== Series Details ==
Series: series starting with [1/2] drm/connector: Share with non-atomic drivers
the function to get the single encoder
URL : https://patchwork.freedesktop.org/series/66547/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6874_full -> Patchwork_14365_full
== Series Details ==
Series: series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for
tgl/bxt/glk (rev2)
URL : https://patchwork.freedesktop.org/series/66537/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6875 -> Patchwork_14374
As we track when we put the GT device to sleep upon idling, we can use
that callback to sample the current rc6 counters and record the
timestamp for estimating samples after that point while asleep.
v2: Stick to using ktime_t
v3: Track user_wakerefs that interfere with the new
== Series Details ==
Series: series starting with [1/2] drm/i915/execlists: Add a paranoid flush of
the CSB pointers upon reset
URL : https://patchwork.freedesktop.org/series/66586/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
08e4e869b22e drm/i915/execlists: Add a paranoid
Quoting Chris Wilson (2019-09-12 11:41:31)
> + spin_lock_irqsave(>lock, flags);
> + if (intel_gt_pm_get_if_awake(gt)) {
> + val = __get_rc6(gt);
> + intel_gt_pm_put(gt);
As food for thought, what about
val = 0;
if (intel_gt_pm_get_if_awake(gt)) {
It refactors and renames a function which handled vsc sdp header and data
block setup for supporting colorimetry format.
Function intel_dp_setup_vsc_sdp handles vsc sdp header and data block
setup for pixel encoding / colorimetry format.
In order to use colorspace information of a connector, it
Support for HDR10 video was introduced in DisplayPort 1.4.
On GLK+ platform, in order to use DisplayPort HDR10, we need to support
BT.2020 colorimetry and HDR Static metadata.
It implements the CTA-861-G standard for transport of static HDR metadata.
It enables writing of HDR metadata infoframe
Because between HDMI and DP have different colorspaces, it renames
drm_mode_create_colorspace_property() function to
drm_mode_create_hdmi_colorspace_property() function for HDMI connector.
And it adds drm_mode_create_dp_colorspace_property() function for creating
of DP colorspace property.
In
When BT.2020 Colorimetry output is used for DP, we should program BT.2020
Colorimetry to MSA and VSC SDP. It adds output_colorspace to
intel_crtc_state struct as a place holder of pipe's output colorspace.
In order to distinguish needed colorimetry for VSC SDP, it adds
intel_dp_needs_vsc_sdp
Function intel_dp_setup_hdr_metadata_infoframe_sdp handles Infoframe SDP
header and data block setup for HDR Static Metadata. It enables writing of
HDR metadata infoframe SDP to panel. Support for HDR video was introduced
in DisplayPort 1.4. It implements the CTA-861-G standard for transport of
It attaches HDR metadata property to DP connector on GLK+.
It enables HDR metadata infoframe sdp on GLK+ to be used to send
HDR metadata to DP sink.
v2: Minor style fix
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 +
1 file
It attaches the colorspace connector property to a DisplayPort connector.
Based on colorspace change, modeset will be triggered to switch to a new
colorspace.
Based on colorspace property value create a VSC SDP packet with appropriate
colorspace. This would help to enable wider color gamut like
According to Bspec, GEN11 and prior GEN11 have different register size for
HDR Metadata Infoframe SDP packet. It adds new VIDEO_DIP_GMP_DATA_SIZE for
GEN11. And it makes handle different register size for
HDMI_PACKET_TYPE_GAMUT_METADATA on hsw_dip_data_size() for each GEN
platforms. It addresses
== Series Details ==
Series: DSB enablement. (rev6)
URL : https://patchwork.freedesktop.org/series/63013/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6874_full -> Patchwork_14369_full
Summary
---
**FAILURE**
Chris Wilson writes:
> Quoting Mika Kuoppala (2019-09-12 08:51:38)
>> Chris Wilson writes:
>>
>> > After a GPU reset, we need to drain all the CS events so that we have an
>> > accurate picture of the execlists state at the time of the reset. Be
>> > paranoid and force a read of the CSB write
Quoting Patchwork (2019-09-12 10:36:49)
> == Series Details ==
>
> Series: series starting with [1/4] drm/i915: Fix cdclk bypass freq readout
> for tgl/bxt/glk (rev2)
> URL : https://patchwork.freedesktop.org/series/66537/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from
On Thu, Sep 12, 2019 at 12:51 PM Martin Wilck wrote:
>
> Is there an alternative to reverting aa56a292ce62 ("drm/i915/userptr:
> Acquire the page lock around set_page_dirty()")? And if we do, what
> would be the consequences? Would other patches need to be reverted,
> too?
Looking at that
== Series Details ==
Series: Mdev: support mutiple kinds of devices
URL : https://patchwork.freedesktop.org/series/66588/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6877 -> Patchwork_14376
Summary
---
**SUCCESS**
== Series Details ==
Series: series starting with [1/4] drm/i915/tgl: Add missing ddi clock select
during DP init sequence
URL : https://patchwork.freedesktop.org/series/66556/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6874 -> Patchwork_14370
== Series Details ==
Series: series starting with [1/2] drm/i915/execlists: Add a paranoid flush of
the CSB pointers upon reset
URL : https://patchwork.freedesktop.org/series/66579/
State : failure
== Summary ==
Applying: drm/i915/execlists: Add a paranoid flush of the CSB pointers upon
== Series Details ==
Series: drm/i915: convert device info num_pipes to pipe_mask (rev2)
URL : https://patchwork.freedesktop.org/series/66567/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6875 -> Patchwork_14372
Summary
After we manipulate the context to allow replay after a GPU reset, force
that context to be reloaded. This should be a layer of paranoia, for if
the GPU was reset, the context will no longer be resident!
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 1
On Thu, Sep 12, 2019 at 05:40:12PM +0800, Jason Wang wrote:
> Currently, except for the crate and remove. The rest fields of
better:
Currently, except for create and remove, the rest of the field in ...
> mdev_parent_ops is just designed for vfio-mdev driver and may not help
> for kernel mdev
Quoting Tvrtko Ursulin (2019-09-12 10:55:00)
>
> On 12/09/2019 10:39, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-09-12 10:20:39)
> >> Don't we end up doing the irqsave spinlock needlessly when !CONFIG_PM?
> >
> > No, the intent is to serialise with i915_pmu_gt_parked and
> >
Quoting Chris Wilson (2019-09-12 11:13:39)
> +#if IS_ENABLED(CONFIG_PM)
> +
> +static inline s64 ktime_since(const ktime_t kt)
> +{
> + return ktime_to_ns(ktime_sub(ktime_get(), kt));
> +}
> +
> +void i915_pmu_gt_parked(struct drm_i915_private *i915)
> +{
> + struct i915_pmu *pmu =
On Wed, Sep 11, 2019 at 06:59:26PM +0100, Chris Wilson wrote:
> The FBC requires a couple of contiguous buffers, which we allocate from
> stolen memory. If stolen memory is unavailable, we cannot allocate those
> buffers and so cannot support FBC. Mark it so.
>
> Signed-off-by: Chris Wilson
>
Quoting Ville Syrjälä (2019-09-12 11:30:14)
> On Wed, Sep 11, 2019 at 06:59:26PM +0100, Chris Wilson wrote:
> > The FBC requires a couple of contiguous buffers, which we allocate from
> > stolen memory. If stolen memory is unavailable, we cannot allocate those
> > buffers and so cannot support
== Series Details ==
Series: drm/i915/dmc: Update ICL DMC version to v1.09
URL : https://patchwork.freedesktop.org/series/66560/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6874_full -> Patchwork_14368_full
Summary
== Series Details ==
Series: Mdev: support mutiple kinds of devices
URL : https://patchwork.freedesktop.org/series/66588/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6368bc7c0c50 mdev: device id support
1029a6c22da1 mdev: introduce device specific ops
-:303:
On Thu, Sep 12, 2019 at 11:23:09AM +, Martin Wilck wrote:
>
> There's a considerable risk that many users will start seeing this
> regression when 5.3 is released. I am not aware of a workaround.
>
> Is there an alternative to reverting aa56a292ce62 ("drm/i915/userptr:
> Acquire the page
Quoting Mika Kuoppala (2019-09-12 12:53:01)
> Chris Wilson writes:
>
> > After we manipulate the context to allow replay after a GPU reset, force
> > that context to be reloaded. This should be a layer of paranoia, for if
> > the GPU was reset, the context will no longer be resident!
> >
> >
On 9/12/2019 12:41 AM, Animesh Manna wrote:
Display State Buffer(DSB) is a new hardware capability, introduced
in GEN12 display. DSB allows a driver to batch-program display HW
registers.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
== Series Details ==
Series: drm/i915/dp: Support for DP HDR outputs (rev6)
URL : https://patchwork.freedesktop.org/series/65656/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6874 -> Patchwork_14371
Summary
---
Quoting Mika Kuoppala (2019-09-12 09:27:56)
> Chris Wilson writes:
>
> > Quoting Mika Kuoppala (2019-09-12 08:51:38)
> >> Chris Wilson writes:
> >>
> >> > After a GPU reset, we need to drain all the CS events so that we have an
> >> > accurate picture of the execlists state at the time of the
On 11/09/2019 17:38, Chris Wilson wrote:
As we track when we put the GT device to sleep upon idling, we can use
that callback to sample the current rc6 counters and record the
timestamp for estimating samples after that point while asleep.
v2: Stick to using ktime_t
v3: Track user_wakerefs
Drop the forcewake before libigt tries to wait on it.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 47 +++
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index
On 11/09/2019 17:38, Chris Wilson wrote:
As we track when we put the GT device to sleep upon idling, we can use
that callback to sample the current rc6 counters and record the
timestamp for estimating samples after that point while asleep.
v2: Stick to using ktime_t
v3: Track user_wakerefs
As we track when we put the GT device to sleep upon idling, we can use
that callback to sample the current rc6 counters and record the
timestamp for estimating samples after that point while asleep.
v2: Stick to using ktime_t
v3: Track user_wakerefs that interfere with the new
As we track when we put the GT device to sleep upon idling, we can use
that callback to sample the current rc6 counters and record the
timestamp for estimating samples after that point while asleep.
v2: Stick to using ktime_t
v3: Track user_wakerefs that interfere with the new
== Series Details ==
Series: drm/i915/pmu: Use GT parked for estimating RC6 while asleep (rev3)
URL : https://patchwork.freedesktop.org/series/56583/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6874_full -> Patchwork_14364_full
After a GPU reset, we need to drain all the CS events so that we have an
accurate picture of the execlists state at the time of the reset. Be
paranoid and force a read of the CSB write pointer from memory.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
---
On 12/09/2019 10:39, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-12 10:20:39)
On 11/09/2019 17:38, Chris Wilson wrote:
As we track when we put the GT device to sleep upon idling, we can use
that callback to sample the current rc6 counters and record the
timestamp for estimating
Chris Wilson writes:
> After we manipulate the context to allow replay after a GPU reset, force
> that context to be reloaded. This should be a layer of paranoia, for if
> the GPU was reset, the context will no longer be resident!
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
>
Quoting Mika Kuoppala (2019-09-12 08:51:38)
> Chris Wilson writes:
>
> > After a GPU reset, we need to drain all the CS events so that we have an
> > accurate picture of the execlists state at the time of the reset. Be
> > paranoid and force a read of the CSB write pointer from memory.
> >
> >
Currently, except for the crate and remove. The rest fields of
mdev_parent_ops is just designed for vfio-mdev driver and may not help
for kernel mdev driver. So follow the device id support by previous
patch, this patch introduces device specific ops which points to
device specific ops (e.g vfio
Mdev bus only support vfio driver right now, so it doesn't implement
match method. But in the future, we may add drivers other than vfio,
one example is virtio-mdev[1] driver. This means we need to add device
id support in bus match method to pair the mdev device and mdev driver
correctly.
So
Hi all:
During the development of virtio-mdev[1]. I find that mdev needs to be
extended to support devices other than vfio mdev device. So this
series tries to extend the mdev to be able to differ from different
devices by:
- device id and matching for mdev bus
- device speicfic callbacks and
== Series Details ==
Series: drm/i915: Disable FBC if BIOS reserved memory (stolen) is unavailable
URL : https://patchwork.freedesktop.org/series/66549/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6874_full -> Patchwork_14366_full
== Series Details ==
Series: series starting with [1/2] drm/i915/execlists: Add a paranoid flush of
the CSB pointers upon reset
URL : https://patchwork.freedesktop.org/series/66586/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6876 -> Patchwork_14375
As we track when we put the GT device to sleep upon idling, we can use
that callback to sample the current rc6 counters and record the
timestamp for estimating samples after that point while asleep.
v2: Stick to using ktime_t
v3: Track user_wakerefs that interfere with the new
Quoting Tvrtko Ursulin (2019-09-12 13:38:47)
>
> On 12/09/2019 12:32, Chris Wilson wrote:
> > + if (val)
> > + /*
> > + * If we are coming back from being runtime suspended we must
> > + * be careful not to report a larger value than returned
> > +
The userptr put_pages can be called from inside try_to_unmap, and so
enters with the page lock held on one of the object's backing pages. We
cannot take the page lock ourselves for fear of recursion.
Reported-by: Lionel Landwerlin
Reported-by: Martin Wilck
Reported-by: Leo Kraav
Fixes:
Quoting Arkadiusz Hiler (2019-09-12 13:54:18)
> Without it we get:
> Unclaimed read from register 0x1e1110
> WARNING: CPU: 2 PID: 1029 at drivers/gpu/drm/i915/intel_uncore.c:1101
> __unclaimed_reg_debug+0x40/0x50 [i915]
> Call Trace:
> fwtable_read32+0x233/0x300 [i915]
>
Quoting Dave Airlie (2019-08-13 22:20:52)
> On Sat, 10 Aug 2019 at 08:26, Matthew Auld wrote:
> >
> > In preparation for upcoming devices with device local memory, introduce the
> > concept of different memory regions, and a simple buddy allocator to manage
> > them in i915.
> >
> > One of the
== Series Details ==
Series: drm/i915/dp: Support for DP HDR outputs (rev6)
URL : https://patchwork.freedesktop.org/series/65656/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6874_full -> Patchwork_14371_full
Summary
Keep the engine awake to ensure that we don't inject any pm-idle
requests.
References: https://bugs.freedesktop.org/show_bug.cgi?id=08
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git
On 11/09/2019 17:50, Patchwork wrote:
== Series Details ==
Series: drm/i915/pmu: Skip busyness sampling when and where not needed
URL : https://patchwork.freedesktop.org/series/66541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6872 -> Patchwork_14363
== Series Details ==
Series: series starting with [1/4] drm/i915/tgl: Add missing ddi clock select
during DP init sequence
URL : https://patchwork.freedesktop.org/series/66556/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6874_full -> Patchwork_14370_full
On Thu, 12 Sep 2019, Animesh Manna wrote:
> This patch adds a function, which will internally get the gem buffer
> for DSB engine. The GEM buffer is from global GTT, and is mapped into
> CPU domain, contains the data + opcode to be feed to DSB engine.
>
> v1: Initial version.
>
> v2:
> - removed
Adding a couple AMD guys.
I know this is already merged but I have a few questions after some
internal discussions.
On 2019-05-07 12:27 p.m., Ramalingam C wrote:
> On every hdcp revocation check request SRM is read from fw file
> /lib/firmware/display_hdcp_srm.bin
>
According to section 5 of
On 12/09/2019 13:56, Chris Wilson wrote:
The userptr put_pages can be called from inside try_to_unmap, and so
enters with the page lock held on one of the object's backing pages. We
cannot take the page lock ourselves for fear of recursion.
Reported-by: Lionel Landwerlin
Reported-by: Martin
On Thu, 12 Sep 2019, "Sharma, Shashank" wrote:
> On 9/12/2019 12:41 AM, Animesh Manna wrote:
>> DSB support single register write through opcode 0x1. Generic
>> api created which accumulate all single register write in a batch
>> buffer and once DSB is triggered, it will program all the registers
On 9/12/2019 12:41 AM, Animesh Manna wrote:
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
We see failures where the context continues executing past a
preemption event, eventually leading to situations where a request has
executed before we have event submitted it to HW! It seems like tgl is
ignoring our RING_TAIL updates, but more likely is that there is a
missing update required for
Chris Wilson writes:
> We see failures where the context continues executing past a
> preemption event, eventually leading to situations where a request has
> executed before we have event submitted it to HW! It seems like tgl is
> ignoring our RING_TAIL updates, but more likely is that there is
On 9/12/2019 12:41 AM, Animesh Manna wrote:
Enabling DSB by setting 1 to has_dsb flag for gen12.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
== Series Details ==
Series: drm/i915/dp: Support for DP HDR outputs (rev7)
URL : https://patchwork.freedesktop.org/series/65656/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6881 -> Patchwork_14378
Summary
---
Hi Chris,
On Tue, 2019-09-10 at 17:20 +0300, Leho Kraav wrote:
> On Fri, Aug 09, 2019 at 01:53:43PM +0100, Chris Wilson wrote:
> > Quoting Martin Wilck (2019-08-09 13:41:42)
> > > This happened to me today, running kernel 5.3.0-rc3-1.g571863b-
> > > default
> > > (5.3-rc3 with just a few patches
On 9/12/2019 12:41 AM, Animesh Manna wrote:
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
v1: Initial version.
v2: Unused
On 9/12/2019 6:30 PM, Sharma, Shashank wrote:
On 9/12/2019 6:21 PM, Jani Nikula wrote:
On Thu, 12 Sep 2019, "Sharma, Shashank"
wrote:
On 9/12/2019 12:41 AM, Animesh Manna wrote:
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register
On Thu, 12 Sep 2019, Animesh Manna wrote:
> Gamma lut programming can be programmed using DSB
> where bulk register programming can be done using indexed
> register write which takes number of data and the mmio offset
> to be written.
>
> Currently enabled for 12-bit gamma LUT which is enabled by
On 9/12/2019 12:41 AM, Animesh Manna wrote:
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. DSB feature can be used for bulk register
programming e.g. gamma lut programming, HDR meta data programming.
v1: initial version.
v2: simplified code by using
We see failures where the context continues executing past a
preemption event, eventually leading to situations where a request has
executed before we have event submitted it to HW! It seems like tgl is
ignoring our RING_TAIL updates, but more likely is that there is a
missing update required for
From: Daniele Ceraolo Spurio
Gen12 has dual-subslices (DSS), which compared to gen11 subslices have
some duplicated resources/paths. Although DSS behave similarly to 2
subslices, instead of splitting this and presenting userspace with bits
not directly representative of hardware resources,
We think that we got rc6 problems sorted out. Flip the switch
and let CI expose our tendency to naive optimism.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_pci.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
From: Michel Thierry
The media ranges extend beyond what gen11 gives so we can't piggypack
on gen11 ranges, even on read side.
Introduce a table for gen12 and accessors for it.
v2: correctly implement gen12_fwtable_write/read (Daniele)
v3: update with ranges from bspec.
v4: avoid
From: Chris Wilson
We see failures where the context continues executing past a
preemption event, eventually leading to situations where a request has
executed before we have event submitted it to HW! It seems like tgl is
ignoring our RING_TAIL updates, but more likely is that there is a
missing
On 12/09/2019 16:38, Mika Kuoppala wrote:
From: Daniele Ceraolo Spurio
Gen12 has dual-subslices (DSS), which compared to gen11 subslices have
some duplicated resources/paths. Although DSS behave similarly to 2
subslices, instead of splitting this and presenting userspace with bits
not directly
On Wed, 11 Sep 2019, Jani Nikula wrote:
> Replace device info number of pipes with a bit mask of available
> pipes. This will prove handy in the future. There's still a bunch of
> future work to do to actually allow a non-consecutive mask of pipes, but
> it's a start. No functional changes.
>
>
Cover letter to use https://intel-gfx-ci.01.org/test-with.html
https://patchwork.freedesktop.org/patch/330337/?series=66602
Test-with: 20190912123320.13131-1-arkadiusz.hi...@intel.com
Arkadiusz Hiler (1):
drm/i915: Get the correct wakeref for reading HOTPLUG_EN et al.
Without it we get:
Unclaimed read from register 0x1e1110
WARNING: CPU: 2 PID: 1029 at drivers/gpu/drm/i915/intel_uncore.c:1101
__unclaimed_reg_debug+0x40/0x50 [i915]
Call Trace:
fwtable_read32+0x233/0x300 [i915]
i915_interrupt_info+0xa73/0xd60 [i915]
seq_read+0xdb/0x3c0
On 9/12/2019 6:21 PM, Jani Nikula wrote:
On Thu, 12 Sep 2019, "Sharma, Shashank" wrote:
On 9/12/2019 12:41 AM, Animesh Manna wrote:
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is
On 9/12/2019 6:37 PM, Animesh Manna wrote:
On 9/12/2019 6:30 PM, Sharma, Shashank wrote:
On 9/12/2019 6:21 PM, Jani Nikula wrote:
On Thu, 12 Sep 2019, "Sharma, Shashank"
wrote:
On 9/12/2019 12:41 AM, Animesh Manna wrote:
DSB support single register write through opcode 0x1. Generic
api
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