On Tue, 2019-09-24 at 16:00 +0300, Imre Deak wrote:
> On Mon, Sep 23, 2019 at 03:02:54PM -0700, Lucas De Marchi wrote:
> > On Mon, Sep 23, 2019 at 12:55 PM José Roberto de Souza
> > wrote:
> > > [...]
> > > + ln1 &= ~(DKL_DP_MODE_CFG_DP_X1_MODE |
> > > DKL_DP_MODE_CFG_DP_X2_MODE);
>
== Series Details ==
Series: drm/i915/dp: Fix DP MST error after unplugging TypeC cable (rev2)
URL : https://patchwork.freedesktop.org/series/66837/
State : failure
== Summary ==
Applying: drm/i915/dp: Fix DP MST error after unplugging TypeC cable
Using index info to reconstruct a base
Our semaphore time is measured by sampling a ring register, whereas our
busy time is measured exactly. This leaves a window of discrepancy that
we wish to keep small (at least within sample tolerance).
References: https://bugs.freedesktop.org/show_bug.cgi?id=111788
Signed-off-by: Chris Wilson
On Mon, Sep 23, 2019 at 03:04:06PM -0700, Lucas De Marchi wrote:
> On Mon, Sep 23, 2019 at 12:55 PM José Roberto de Souza
> wrote:
> >
> > From: Lucas De Marchi
> >
> > The final save operation into pll_state of the calculations done will
> > be different for DKL PHY. Prepare for that by
On Fri, Sep 20, 2019 at 01:42:17PM +0200, Maarten Lankhorst wrote:
> Now that we separated everything into uapi and hw, it's
> time to make the split definitive. Remove the union and
> make a copy of the hw state on modeset and fastset.
>
> Color blobs are copied in crtc atomic_check(), right
>
== Series Details ==
Series: i915/gem_map_gtt: Escape from slow forked GTT access
URL : https://patchwork.freedesktop.org/series/67161/
State : success
== Summary ==
CI Bug Log - changes from IGT_5201_full -> IGTPW_3495_full
Summary
== Series Details ==
Series: drm/i915/tgl: Swap engines for no rc6/rps (gpu powersave and reclocking)
URL : https://patchwork.freedesktop.org/series/67178/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6951 -> Patchwork_14519
On Tue, 2019-09-24 at 17:20 +0300, Imre Deak wrote:
> On Mon, Sep 23, 2019 at 12:55:05PM -0700, José Roberto de Souza
> wrote:
> > From: Lucas De Marchi
> >
> > The disable function can be the same as for MG phy since the same
> > registers are used. The others are different as registers
The memory type values have changed in TGL, so we need to translate them
differently than ICL. While we're moving it, fix up the ICL translation
for LPDDR4.
BSpec: 53998
v2: Fix up ICL LPDDR4 entry (Ville); Drop unused values from TGL (Ville)
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
On Tue, Sep 24, 2019 at 09:45:02AM +0100, Tvrtko Ursulin wrote:
>
> On 24/09/2019 00:51, john.c.harri...@intel.com wrote:
> > From: John Harrison
> >
> > With virtual engines, it is no longer possible to know which specific
> > physical engine a given request will be executed on at the time
From: Lucas De Marchi
The disable function can be the same as for MG phy since the same
registers are used. The others are different as registers changed,
also adding a empty dkl_pll_write() to be implemented later.
v2:
Setting the right HIP_INDEX_REG bits (José)
v3:
Masking non-computed
From: Vandita Kulkarni
Add a new function to write to dkl phy pll registers. As per the
bspec all the registers are read modify write.
Reviewed-by: Lucas De Marchi
Signed-off-by: Vandita Kulkarni
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
From: Clinton A Taylor
Add a helper function to return pin map for use during dkl phy
DP_MODE settings, PORT_TX_DFLEXPA1 exist on ICL but we don't need it.
The user of this function will come in future TC patches.
Reviewed-by: Lucas De Marchi
Cc: Lucas De Marchi
Signed-off-by: Clinton A
Extending ICL mg calculations to also support dkl calculations.
v3:
Fixing iref_trim calculation for 38400 refclock
BSpec: 49204
Reviewed-by: Lucas De Marchi
Signed-off-by: Vandita Kulkarni
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 29
From: Lucas De Marchi
The final save operation into pll_state of the calculations done will
be different for DKL PHY. Prepare for that by reindenting code so it's
easier to check for correctness. This one has no change in behavior.
Reviewed-by: Matt Roper
Signed-off-by: Lucas De Marchi
TGL added 2 more TC ports that currently are not being handled by
icl_pll_to_ddi_clk_sel(), so adding those.
Reviewed-by: Lucas De Marchi
Cc: Lucas De Marchi
Cc: Imre Deak
Reported-by: Imre Deak
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
1 file
== Series Details ==
Series: series starting with [v3,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync (rev2)
URL : https://patchwork.freedesktop.org/series/67043/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6952 ->
On Tue, 24 Sep 2019 21:53:29 +0800
Jason Wang wrote:
> Currently, except for the create and remove, the rest of
> mdev_parent_ops is designed for vfio-mdev driver only and may not help
> for kernel mdev driver. With the help of class id, this patch
> introduces device specific callbacks inside
On Tue, 24 Sep 2019 21:53:26 +0800
Jason Wang wrote:
> Mdev bus only supports vfio driver right now, so it doesn't implement
> match method. But in the future, we may add drivers other than vfio,
> the first driver could be virtio-mdev. This means we need to add
> device class id support in bus
On Tue, 24 Sep 2019 21:53:30 +0800
Jason Wang wrote:
> This patch implements basic support for mdev driver that supports
> virtio transport for kernel virtio driver.
>
> Signed-off-by: Jason Wang
> ---
> include/linux/mdev.h| 2 +
> include/linux/virtio_mdev.h | 145
From: Srinivasan S
This patch avoids DP MST payload error message in dmesg, as it is trying
to update the payload to the disconnected DP MST device. After DP MST
device is disconnected we should not be updating the payload and
hence remove the error.
v2: Removed the connector status check and
== Series Details ==
Series: drm/i915/dp: Fix DP MST error after unplugging TypeC cable (rev3)
URL : https://patchwork.freedesktop.org/series/66837/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6952 -> Patchwork_14524
On Fri, Sep 20, 2019 at 01:42:22PM +0200, Maarten Lankhorst wrote:
> Small changes to intel_dp_mode_valid(), allow listing modes that
> can only be supported in the bigjoiner configuration, which is
> not supported yet.
>
> Also unexport a few functions only used internally in intel_dp.c
>
>
On Fri, Sep 20, 2019 at 01:42:20PM +0200, Maarten Lankhorst wrote:
> Rename linked_plane to planar_linked_plane and slave to planar_slave,
> this will make it easier to keep apart bigjoiner linking and planar plane
> linking.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Matt Roper
Hi,
> -Original Message-
> From: Intel-gfx On Behalf Of Swati
> Sharma
> Sent: tiistai 24. syyskuuta 2019 16.58
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; daniel.vet...@ffwll.ch; Nautiyal,
> Ankit K
>
> Subject: [Intel-gfx] [PATCH] Revert "drm/i915/color: Extract
== Series Details ==
Series: drm/print: add and use drm_debug_enabled() (rev2)
URL : https://patchwork.freedesktop.org/series/66656/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6948_full -> Patchwork_14515_full
Summary
On Fri, Sep 20, 2019 at 01:42:19PM +0200, Maarten Lankhorst wrote:
> This can all be done from the intel_update_crtc function. Split out the
> pipe update into a separate function, just like is done for the planes.
>
> Signed-off-by: Maarten Lankhorst
The code here all looks logically correct,
== Series Details ==
Series: mdev based hardware virtio offloading support (rev3)
URL : https://patchwork.freedesktop.org/series/66989/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6948_full -> Patchwork_14516_full
On Tue, Sep 24, 2019 at 10:30:39PM -0700, Matt Roper wrote:
> On Fri, Sep 20, 2019 at 01:42:22PM +0200, Maarten Lankhorst wrote:
> > Small changes to intel_dp_mode_valid(), allow listing modes that
> > can only be supported in the bigjoiner configuration, which is
> > not supported yet.
> >
> >
Hi,
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: tiistai 24. syyskuuta 2019 15.18
> To: Sharma, Swati2 ; intel-gfx@lists.freedesktop.org
> Cc: daniel.vet...@ffwll.ch; Nautiyal, Ankit K
> Subject: Re: [Intel-gfx] [v4][PATCH 2/3] drm/i915/color: Extract
>
On Fri, Sep 20, 2019 at 01:42:21PM +0200, Maarten Lankhorst wrote:
> We cannot switch between HQ and normal mode on GLK+, so only
> add planes on platforms where it makes sense.
>
> We could probably restrict it even more to only add when scaler
> users toggles between 1 and 2, but lets just
According to the bspec, GLK/CNL have a smaller small joiner RAM buffer
than ICL+. This feels like something that could easily change again on
future platforms, so let's just add a function to return the proper
per-platform buffer size. That may also slightly simplify the upcoming
bigjoiner
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