== Series Details ==
Series: DC3CO Support for TGL (rev12)
URL : https://patchwork.freedesktop.org/series/64923/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6963_full -> Patchwork_14559_full
Summary
---
From: Ville Syrjälä
drm_atomic_crtc_state_for_each_plane_state() can't be used after
we have the uapi vs. hw split. Roll our own :(
Truthfully I'd like to nuke this thing entirely, but that
requires some more work so let's live with it for now.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
drm_atomic_add_affected_planes() can't be used in some cases
once we do the uapi vs. hw state split because we'll want
to consider the plane maks in the hw state rather than the
uapi state. Roll our own :(
Signed-off-by: Ville Syrjälä
---
On Tue, Sep 03, 2019 at 04:46:03PM -0400, Lyude Paul wrote:
> Finally! For a very long time, our MST helpers have had one very
> annoying issue: They don't know how to reprobe the topology state when
> coming out of suspend. This means that if a user has a machine connected
> to an MST topology
== Series Details ==
Series: series starting with [1/5] drm/i915: Switch
intel_legacy_cursor_update() to intel_ types
URL : https://patchwork.freedesktop.org/series/67337/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6969 -> Patchwork_14566
On Thu, Sep 26, 2019 at 08:26:18PM +0530, Anshuman Gupta wrote:
> DC3CO enabling B.Specs sequence requires to enable end configure
> exit scanlines to TRANS_EXITLINE register, programming this register
> has to be part of modeset sequence as this can't be change when
> transcoder or port is
From: Ville Syrjälä
Prepare the connector/encoder mask readout for the uapi vs. hw
state split. We'll want to do all readout into the hw state.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
From: Ville Syrjälä
Prefer the intel_ types in intel_legacy_cursor_update() over the
drm_ types. Should make it easier to adapt this to the uapi vs. hw
state split.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 86 ++--
1 file changed, 43
From: Ville Syrjälä
Prepare the mode readout for the uapi vs. hw state split.
We'll want to do all readout into the hw state.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Ville Syrjälä
Prepare the connector/encoder mask readout for the uapi vs. hw
state split. We'll want to do all readout into the hw state.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
== Series Details ==
Series: series starting with [1/5] drm/i915: Switch
intel_legacy_cursor_update() to intel_ types
URL : https://patchwork.freedesktop.org/series/67337/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6e83c3bdcc40 drm/i915: Switch intel_legacy_cursor_update()
On Fri, Sep 27, 2019 at 04:40:59PM +0300, Jani Nikula wrote:
> On Fri, 27 Sep 2019, Imre Deak wrote:
> > On Fri, Sep 27, 2019 at 02:07:43PM +0300, Imre Deak wrote:
> >> On Thu, Sep 26, 2019 at 08:26:17PM +0530, Anshuman Gupta wrote:
> >> > +void tgl_set_target_dc_state(struct drm_i915_private
On Fri, 27 Sep 2019, Imre Deak wrote:
> On Fri, Sep 27, 2019 at 02:07:43PM +0300, Imre Deak wrote:
>> On Thu, Sep 26, 2019 at 08:26:17PM +0530, Anshuman Gupta wrote:
>> > +void tgl_set_target_dc_state(struct drm_i915_private *dev_priv, u32 state)
>
> We need a documentation for exported
On Fri, Sep 27, 2019 at 10:56:16AM +0200, Maarten Lankhorst wrote:
> Op 26-09-2019 om 21:11 schreef Ville Syrjälä:
> > On Thu, Sep 26, 2019 at 07:09:22PM +0300, Ville Syrjälä wrote:
> >> On Thu, Sep 26, 2019 at 05:50:05PM +0200, Maarten Lankhorst wrote:
> >>> Op 26-09-2019 om 15:06 schreef Ville
Verify that the values we store in our nonpriv context image registers
are restored after a switch.
v2: Use explicit ordering to ensure we force the context switch back and
forth in between the register writes and their read.
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
---
Quoting Tvrtko Ursulin (2019-09-27 14:58:24)
>
> On 27/09/2019 13:32, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-09-27 13:25:23)
> >>
> >> On 27/09/2019 13:16, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2019-09-27 13:08:51)
>
> On 27/09/2019 12:25, Chris Wilson wrote:
>
On Fri, Sep 27, 2019 at 02:07:43PM +0300, Imre Deak wrote:
> On Thu, Sep 26, 2019 at 08:26:17PM +0530, Anshuman Gupta wrote:
> > Add target_dc_state and tgl_set_target_dc_state() API
> > in order to enable DC3CO state with existing DC states.
> > target_dc_state will enable/disable the desired DC
On 27/09/2019 13:32, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-27 13:25:23)
On 27/09/2019 13:16, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-27 13:08:51)
On 27/09/2019 12:25, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-27 12:10:29)
On 25/09/2019 11:01, Chris
On Fri, Sep 27, 2019 at 05:41:49PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 27, 2019 at 10:56:16AM +0200, Maarten Lankhorst wrote:
> > Op 26-09-2019 om 21:11 schreef Ville Syrjälä:
> > > On Thu, Sep 26, 2019 at 07:09:22PM +0300, Ville Syrjälä wrote:
> > >> On Thu, Sep 26, 2019 at 05:50:05PM
On Thu, Sep 26, 2019 at 08:26:19PM +0530, Anshuman Gupta wrote:
> Disallow DC3CO state before PSR2 exit.
> Store dc3co_exitline from crtc state to psr dev_priv
> structure to use it easily whenever it requires.
>
> v1: Moved calling of tgl_enable_psr2_transcoder_exitline() to
>
On Thu, Sep 26, 2019 at 08:26:21PM +0530, Anshuman Gupta wrote:
> Adding DC3CO counter in i915_dmc_info debugfs will be
> useful for DC3CO validation.
> DMC firmware uses DMC_DEBUG3 register as DC3CO counter
> register on TGL, as per B.Specs DMC_DEBUG3 is general
> purpose register.
>
> Cc: Jani
== Series Details ==
Series: drm/i915/userptr: Never allow userptr into the mappable GGTT
URL : https://patchwork.freedesktop.org/series/67349/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e7fbf6cde45c drm/i915/userptr: Never allow userptr into the mappable GGTT
-:25:
Quoting Tvrtko Ursulin (2019-09-25 16:59:26)
>
> On 25/09/2019 09:23, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-09-23 09:10:26)
> >>
> >> On 20/09/2019 17:35, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2019-09-20 17:22:42)
>
> On 02/09/2019 05:02, Chris Wilson wrote:
>
On 2019-09-27 at 19:38:49 +0300, Imre Deak wrote:
> On Thu, Sep 26, 2019 at 08:26:21PM +0530, Anshuman Gupta wrote:
> > Adding DC3CO counter in i915_dmc_info debugfs will be
> > useful for DC3CO validation.
> > DMC firmware uses DMC_DEBUG3 register as DC3CO counter
> > register on TGL, as per
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/tc: Update DP_MODE programming
URL : https://patchwork.freedesktop.org/series/67312/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6966_full -> Patchwork_14561_full
i915_gem_init_early doesn't need to return anything.
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.c | 5 +
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 4 +---
3 files changed, 3 insertions(+), 8 deletions(-)
diff --git
Some kernel internal objects may need to be allocated as a continuous
block, also thinking ahead the various kernel io_mapping interfaces seem
to expect it, although this is purely a limitation in the kernel
API...so perhaps something to be improved.
Signed-off-by: Matthew Auld
Cc: Joonas
Support memory regions, as defined by a given (start, end), and allow
creating GEM objects which are backed by said region. The immediate goal
here is to have something to represent our device memory, but later on
we also want to represent every memory domain with a region, so stolen,
shmem, and
From: Abdiel Janulgue
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
---
drivers/gpu/drm/i915/intel_region_lmem.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
Volatile objects are marked as DONTNEED while pinned, therefore once
unpinned the backing store can be discarded. This is limited to kernel
internal objects.
Signed-off-by: Matthew Auld
Signed-off-by: CQ Tang
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
From: Abdiel Janulgue
Exposes available regions for the platform. Shared memory will
always be available.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
2 files changed, 4
The basic LMEM bits, minus the uAPI, pruning, etc. The goal is to support
basic LMEM object creation within the kernel. From there we can start with the
dumb buffer support, and then the other display related bits.
We still have a few patches that deal with lack of MAPPABLE_APERTURE support,
Explosions during early driver init on the error path. Make sure we fail
gracefully.
[ 9547.672258] BUG: kernel NULL pointer dereference, address: 007c
[ 9547.672288] #PF: supervisor read access in kernel mode
[ 9547.672292] #PF: error_code(0x) - not-present page
[ 9547.672296]
Quoting Matthew Auld (2019-09-27 18:34:06)
> @@ -2692,13 +2693,15 @@ static int init_ggtt(struct i915_ggtt *ggtt)
> if (ret)
> return ret;
>
> - /* Reserve a mappable slot for our lockless error capture */
> - ret = drm_mm_insert_node_in_range(>vm.mm,
On 9/26/19 12:37 AM, Michal Wajdeczko wrote:
On Thu, 26 Sep 2019 01:03:20 +0200, Summers, Stuart
wrote:
On Wed, 2019-09-25 at 15:21 -0700, Daniele Ceraolo Spurio wrote:
The HuC FW has silently switched to encoding the version the same way
as
the GuC FW does, i.e. major.minor.patch instead
And pushed.
Daniele
On 9/26/19 8:30 AM, Patchwork wrote:
== Series Details ==
Series: drm/i915/dmc: Update ICL DMC version to v1.09 (rev2)
URL : https://patchwork.freedesktop.org/series/66560/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6958_full -> Patchwork_14538_full
Quoting Matthew Auld (2019-09-27 18:34:08)
> From: CQ Tang
>
> drm_mm_insert_node_in_range() treats range_start > range_end as a
> programmer error, such that we explode in insert_mappable_node. For now
> simply check for missing aperture on such paths.
range_start is 0.
range_end is 0.
== Series Details ==
Series: LMEM basics
URL : https://patchwork.freedesktop.org/series/67350/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6970 -> Patchwork_14569
Summary
---
**SUCCESS**
No regressions found.
For those mock tests that may wish to pretend triggering a GPU reset and
processing the cleanup.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 32 +--
Quoting Matthew Auld (2019-09-27 18:33:57)
> +static int igt_gpu_write_dw(struct intel_context *ce,
> + struct i915_vma *vma,
> + u32 dword,
> + u32 value)
> +{
> + int err;
> +
> +
Hi Dave and Daniel,
This should've gone out yesterday, but apparently I had some issue with my mutt
here.
Anyway, nothing that couldn't wait for rc2
Here goes drm-intel-next-fixes-2019-09-26:
- Fix concurrence on cases where requests where getting retired at same time as
resubmitted to HW
-
Quoting Matthew Auld (2019-09-27 18:33:50)
> +void
> +__intel_memory_region_put_block_buddy(struct i915_buddy_block *block)
> +{
> + struct list_head blocks;
LIST_HEAD(blocks); (and no INIT_LIST_HEAD required)
> +
> + INIT_LIST_HEAD();
> + list_add(>link, );
> +
== Series Details ==
Series: series starting with [v3,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync (rev4)
URL : https://patchwork.freedesktop.org/series/67043/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6971 ->
Quoting Matthew Auld (2019-09-27 18:33:56)
> +static int igt_lmem_write_cpu(void *arg)
> +{
> + struct drm_i915_private *i915 = arg;
> + struct intel_context *ce = i915->engine[BCS0]->kernel_context;
> + struct drm_i915_gem_object *obj;
> + struct rnd_state prng;
> +
Hi Chris,
On Fri, Sep 27, 2019 at 08:14:42PM +0100, Chris Wilson wrote:
> For those mock tests that may wish to pretend triggering a GPU reset and
> processing the cleanup.
The patch is OK, per se, but I think it should be split in two
parts:
- the i915 to gt conversion (that is the biggest
On Wed, Sep 25, 2019 at 11:01:24AM +0100, Chris Wilson wrote:
> Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
> that we can expose properties on each engine to the sysadmin.
>
> To start with we have basic analogues of the i915_query ioctl so that we
> can pretty print
Quoting Matthew Auld (2019-09-27 18:34:05)
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c
> b/drivers/gpu/drm/i915/selftests/i915_gem.c
> index 37593831b539..4951957a4d8d 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
> @@
Ville, Maarten
In this patch, I added a WARN ON for the case where the same trans could be
configured as master and slave.
Does this look good?
Manasi
On Thu, Sep 26, 2019 at 05:11:10PM -0700, Manasi Navare wrote:
> After the state is committed, we readout the HW registers and compare
> the
If we are mocking the device, skip trying to sanitize the pm HW state.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
Quoting Matthew Auld (2019-09-27 18:34:01)
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
> b/drivers/gpu/drm/i915/gem/i915_gem_region.c
> index 0aeaebb41050..77e89fabbddf 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
> @@
Quoting Ville Syrjala (2019-09-19 17:30:52)
> From: Ville Syrjälä
>
> Random smattering of patches to eliminate compiler warnings.
> Some I just suppressed out of lazyness, others I tried to
> silence by adjusting the code a bit.
Some of the aliasing pointer avoidance looked silly, but silly
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Provide a mock GPU reset
routine
URL : https://patchwork.freedesktop.org/series/67353/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6971 -> Patchwork_14571
Quoting Matthew Auld (2019-09-27 18:33:50)
> +struct drm_i915_gem_object *
> +i915_gem_object_create_region(struct intel_memory_region *mem,
> + resource_size_t size,
> + unsigned int flags)
> +{
> + struct drm_i915_gem_object *obj;
> +
Quoting Matthew Auld (2019-09-27 18:33:57)
> + i = 0;
> + engines = i915_gem_context_lock_engines(ctx);
> + do {
> + u32 rng = prandom_u32_state();
> + u32 dword = offset_in_page(rng) / 4;
> +
> + ce = engines->engines[order[i] %
If we are mocking the device, skip trying to sanitize the pm HW state.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
== Series Details ==
Series: series starting with [v3,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync (rev3)
URL : https://patchwork.freedesktop.org/series/67043/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6966_full ->
== Series Details ==
Series: drm/i915/guc: Update H2G enable logging action definition
URL : https://patchwork.freedesktop.org/series/67351/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6970 -> Patchwork_14570
Summary
Quoting Matthew Auld (2019-09-27 18:33:56)
> static const struct drm_i915_gem_object_ops i915_gem_object_internal_ops = {
> .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
> -I915_GEM_OBJECT_IS_SHRINKABLE,
> +I915_GEM_OBJECT_IS_SHRINKABLE |
> +
Hi Chris,
On Fri, Sep 27, 2019 at 08:14:43PM +0100, Chris Wilson wrote:
> If we are mocking the device, skip trying to sanitize the pm HW state.
>
> Signed-off-by: Chris Wilson
> Cc: Andi Shyti
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 3 ++-
> 1 file changed, 2 insertions(+), 1
Quoting Matthew Auld (2019-09-27 18:33:59)
> + mem->id = intel_region_map[i];
> + mem->type = type;
> + mem->instance =
> MEMORY_INSTANCE_FROM_REGION(intel_region_map[i]);
So why 3xu32 for a single u32 of information? Either one or two u32
would do,
Quoting Matthew Auld (2019-09-27 18:34:04)
> From: Daniele Ceraolo Spurio
>
> We can't fence anything without aperture.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Stuart Summers
> Cc: Matthew Auld
> ---
> drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 --
> 1 file
Quoting Andi Shyti (2019-09-27 21:41:19)
> Hi Chris,
>
> On Fri, Sep 27, 2019 at 08:14:42PM +0100, Chris Wilson wrote:
> > For those mock tests that may wish to pretend triggering a GPU reset and
> > processing the cleanup.
>
> The patch is OK, per se, but I think it should be split in two
>
Quoting Chris Wilson (2019-09-27 20:14:42)
> -static reset_func intel_get_gpu_reset(struct drm_i915_private *i915)
> +static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
> {
> - if (INTEL_GEN(i915) >= 8)
> + struct drm_i915_private *i915 = gt->i915;
> +
> + if
Unwedging the GPU requires a successful GPU reset before we restore the
default submission, or else we may see residual context switch events
that we were not expecting.
v2: Pull in the special-case reset_clobbers_display, and explain why it
should be safe in the context of unwedging.
v3: Just
Daniel Vetter uncovered a nasty cycle in using the mmu-notifiers to
invalidate userptr objects which also happen to be pulled into GGTT
mmaps. That is when we unbind the userptr object (on mmu invalidation),
we revoke all CPU mmaps, which may then recurse into mmu invalidation.
We looked for ways
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 5 +-
drivers/gpu/drm/i915/gem/i915_gem_region.c| 14 +++-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 68 ++-
drivers/gpu/drm/i915/i915_drv.h
From: Daniele Ceraolo Spurio
The following patches in the series will use it to avoid certain
operations when aperture is not available in HW.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
We currently define LMEM, or local memory, as just another memory
region, like system memory or stolen, which we can expose to userspace
and can be mapped to the CPU via some BAR.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/Makefile
From: CQ Tang
drm_mm_insert_node_in_range() treats range_start > range_end as a
programmer error, such that we explode in insert_mappable_node. For now
simply check for missing aperture on such paths.
Signed-off-by: CQ Tang
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem.c | 6
From: Abdiel Janulgue
Nothing to enumerate yet...
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 70 +--
Intended for upstream testing so that we can still exercise the LMEM
plumbing and !HAS_MAPPABLE_APERTURE paths. Smoke tested on Skull Canyon
device. This works by allocating an intel_memory_region for a reserved
portion of system memory, which we treat like LMEM. For the LMEMBAR we
steal the
Simple test writing to dwords across an object, using various engines in
a randomized order, checking that our writes land from the cpu.
Signed-off-by: Matthew Auld
---
.../drm/i915/selftests/intel_memory_region.c | 179 ++
1 file changed, 179 insertions(+)
diff --git
Signed-off-by: Matthew Auld
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 121 +-
1 file changed, 120 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index
We may be missing support for the mappable aperture on some platforms.
Signed-off-by: Matthew Auld
Cc: Daniele Ceraolo Spurio
---
.../drm/i915/gem/selftests/i915_gem_coherency.c| 5 -
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 6 ++
From: Abdiel Janulgue
We can create LMEM objects, but we also need to support mapping them
into kernel space for internal use.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Signed-off-by: Steve Hampson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 4
From: Daniele Ceraolo Spurio
If the aperture is not available in HW we can't use a ggtt slot and wc
copy, so fall back to regular kmap.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 19
From: Daniele Ceraolo Spurio
We can't fence anything without aperture.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
From: Michal Wajdeczko
HWS placement restrictions can't just rely on HAS_LLC flag.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Convert stolen memory over to a region object. Still leaves open the
question with what to do with pre-allocated objects...
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_region.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c |
From: Daniele Ceraolo Spurio
Skip both setup and cleanup of the aperture mapping if the HW doesn't
have an aperture bar.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 34 ++---
1 file changed, 21
On Wed, Sep 25, 2019 at 01:33:50PM -0700, James Ausmus wrote:
> In prep for newer platforms having more complicated ways to determine
> the SAGV block time, extract the setting to a separate function. While
> we're at it, update the if ladder to follow the new gen -> old gen order
> preference,
On Fri, 2019-09-27 at 17:24 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [CI,1/4] drm/i915/tc: Update DP_MODE
> programming
> URL : https://patchwork.freedesktop.org/series/67312/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from
Quoting Matthew Auld (2019-09-27 18:33:50)
> +void
> +intel_memory_region_destroy(struct intel_memory_region *mem)
> +{
> + if (mem->ops->release)
> + mem->ops->release(mem);
> +
mutex_destroy(>mm_lock);
> + kfree(mem);
> +}
== Series Details ==
Series: LMEM basics
URL : https://patchwork.freedesktop.org/series/67350/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: check for kernel_context
Okay!
Commit: drm/i915: simplify i915_gem_init_early
Okay!
Commit:
== Series Details ==
Series: drm/i915/gt: Only unwedge if we can reset first (rev2)
URL : https://patchwork.freedesktop.org/series/66637/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6969 -> Patchwork_14567
Summary
== Series Details ==
Series: drm/i915/userptr: Never allow userptr into the mappable GGTT
URL : https://patchwork.freedesktop.org/series/67349/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6969 -> Patchwork_14568
Summary
Quoting Matthew Auld (2019-09-27 18:33:49)
> i915_gem_init_early doesn't need to return anything.
>
> Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
Hi Alex,
> -Original Message-
> From: Alex Williamson
> Sent: Tuesday, September 24, 2019 6:07 PM
> To: Jason Wang
> Cc: k...@vger.kernel.org; linux-s...@vger.kernel.org; linux-
> ker...@vger.kernel.org; dri-de...@lists.freedesktop.org; intel-
> g...@lists.freedesktop.org;
On Wed, Sep 25, 2019 at 01:33:51PM -0700, James Ausmus wrote:
> Starting from TGL, we now need to read the SAGV block time via a PCODE
> mailbox, rather than having a static value.
>
> BSpec: 49326
>
> Cc: Ville Syrjälä
> Cc: Stanislav Lisovskiy
> Cc: Lucas De Marchi
> Signed-off-by: James
GuC enable logging H2G action definition changed some time ago from 0xE000
to 0x40. All current GuC FW blobs use this definition, so fix the action
definition in driver to match.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Robert M. Fosha
---
Quoting Matthew Auld (2019-09-27 18:33:50)
> +static void close_objects(struct list_head *objects)
> +{
> + struct drm_i915_private *i915 = NULL;
> + struct drm_i915_gem_object *obj, *on;
> +
> + list_for_each_entry_safe(obj, on, objects, st_link) {
> + i915 =
Quoting Matthew Auld (2019-09-27 18:33:51)
> struct drm_i915_gem_object *
> diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> index 4e1805aaeb99..f9fbf2865782 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> +++
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Matthew Auld
>Sent: Friday, September 27, 2019 1:34 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: daniel.vet...@ffwll.ch
>Subject: [Intel-gfx] [PATCH 04/22] drm/i915/region: support
Quoting Matthew Auld (2019-09-27 18:33:54)
> +const u32 intel_region_map[] = {
> + [INTEL_MEMORY_SMEM] = BIT(INTEL_SMEM + INTEL_MEMORY_TYPE_SHIFT) |
> BIT(0),
> + [INTEL_MEMORY_LMEM] = BIT(INTEL_LMEM + INTEL_MEMORY_TYPE_SHIFT) |
> BIT(0),
> + [INTEL_MEMORY_STOLEN] =
On Wed, Sep 25, 2019 at 01:33:51PM -0700, James Ausmus wrote:
> Starting from TGL, we now need to read the SAGV block time via a PCODE
> mailbox, rather than having a static value.
>
> BSpec: 49326
>
> Cc: Ville Syrjälä
Wrong address. I ignore all patches going there, so it's not doing you
any
== Series Details ==
Series: LMEM basics
URL : https://patchwork.freedesktop.org/series/67350/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ccc51e3ac24e drm/i915: check for kernel_context
dbbfe24cafca drm/i915: simplify i915_gem_init_early
f52b9b0685d8 drm/i915: introduce
On Thu, Sep 26, 2019 at 08:26:20PM +0530, Anshuman Gupta wrote:
> DC3CO is useful power state, when DMC detects PSR2 idle frame
> while an active video playback, playing 30fps video on 60hz panel
> is the classic example of this use case.
>
> B.Specs:49196 has a restriction to enable DC3CO only
On Thu, Sep 26, 2019 at 03:34:35PM +0300, Ville Syrjälä wrote:
> On Wed, Sep 25, 2019 at 01:33:52PM -0700, James Ausmus wrote:
> > For Gen12, BSpec no longer tells us to disable SAGV when > 1 pipe is
> > active. Update intel_can_enable_sagv to allow this, and loop through all
> > active planes on
Quoting Matthew Auld (2019-09-27 18:33:48)
> Explosions during early driver init on the error path. Make sure we fail
> gracefully.
Joonas would complain about the clearly not onion unwind here, but we
have thrown it in as a catch-all cleanup for what is quite a complicated
setup.
> [
Quoting Matthew Auld (2019-09-27 18:33:50)
> +struct drm_i915_gem_object *
> +i915_gem_object_create_region(struct intel_memory_region *mem,
> + resource_size_t size,
> + unsigned int flags)
> +{
> + struct drm_i915_gem_object *obj;
> +
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