[Intel-gfx] [PATCH] drm/i915: Stop programming DDI_BUF_TRANS_SELECT on recent platforms
The bits in DDI_BUF_CTL related to DP vswing emphasis were removed on
GLK since the relevant programming has moved to the PHY registers. The
bits still exist on BXT, but have a programming note indicating that
they're ignored. Let's stop programming them on gen9lp and and gen10+.
Bspec: 7534
Bspec: 49533
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_ddi.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3a538789c585..c63a1712515c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1148,6 +1148,8 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
/* Start the training iterating through available voltages and emphasis,
* testing each value twice. */
for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
+ u32 tmp;
+
/* Configure DP_TP_CTL with auto-training */
I915_WRITE(DP_TP_CTL(PORT_E),
DP_TP_CTL_FDI_AUTOTRAIN |
@@ -1159,10 +1161,10 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
* DDI E does not support port reversal, the functionality is
* achieved on the PCH side in FDI_RX_CTL, so no need to set the
* port reversal bit */
- I915_WRITE(DDI_BUF_CTL(PORT_E),
- DDI_BUF_CTL_ENABLE |
- ((crtc_state->fdi_lanes - 1) << 1) |
- DDI_BUF_TRANS_SELECT(i / 2));
+ tmp = DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1);
+ if (INTEL_GEN(dev_priv) <= 9 && !IS_GEN9_LP(dev_priv))
+ tmp |= DDI_BUF_TRANS_SELECT(i / 2);
+ I915_WRITE(DDI_BUF_CTL(PORT_E), tmp);
POSTING_READ(DDI_BUF_CTL(PORT_E));
udelay(600);
@@ -1238,13 +1240,16 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(>base);
struct intel_digital_port *intel_dig_port =
enc_to_dig_port(>base);
- intel_dp->DP = intel_dig_port->saved_port_bits |
- DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
+ intel_dp->DP = intel_dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
+ if (INTEL_GEN(dev_priv) <= 9 && !IS_GEN9_LP(dev_priv))
+ intel_dp->DP |= DDI_BUF_TRANS_SELECT(0);
+
}
static struct intel_encoder *
--
2.23.0
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[Intel-gfx] ✓ Fi.CI.IGT: success for dumb buffer patches
== Series Details == Series: dumb buffer patches URL : https://patchwork.freedesktop.org/series/71493/ State : success == Summary == CI Bug Log - changes from CI_DRM_7654_full -> Patchwork_15945_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_15945_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@vcs1-queued: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-iclb1/igt@gem_ctx_persiste...@vcs1-queued.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/shard-iclb8/igt@gem_ctx_persiste...@vcs1-queued.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-iclb7/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_eio@kms: - shard-snb: [PASS][5] -> [DMESG-FAIL][6] ([i915#436]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-snb1/igt@gem_...@kms.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/shard-snb1/igt@gem_...@kms.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110854]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-iclb4/igt@gem_exec_balan...@smoke.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/shard-iclb7/igt@gem_exec_balan...@smoke.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112080]) +10 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-iclb4/igt@gem_exec_paral...@vcs1-fds.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/shard-iclb7/igt@gem_exec_paral...@vcs1-fds.html * igt@gem_exec_reloc@basic-gtt-active: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#109]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-skl10/igt@gem_exec_re...@basic-gtt-active.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/shard-skl9/igt@gem_exec_re...@basic-gtt-active.html * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109276]) +18 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-iclb1/igt@gem_exec_sched...@independent-bsd2.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/shard-iclb8/igt@gem_exec_sched...@independent-bsd2.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#112146]) +9 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-iclb8/igt@gem_exec_sched...@preempt-other-chain-bsd.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/shard-iclb2/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_exec_schedule@preempt-queue-blt: - shard-tglb: [PASS][17] -> [INCOMPLETE][18] ([fdo#111677]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-tglb2/igt@gem_exec_sched...@preempt-queue-blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/shard-tglb9/igt@gem_exec_sched...@preempt-queue-blt.html * igt@gem_exec_schedule@preempt-queue-contexts-chain-blt: - shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([fdo#111606] / [fdo#111677]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-tglb6/igt@gem_exec_sched...@preempt-queue-contexts-chain-blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/shard-tglb5/igt@gem_exec_sched...@preempt-queue-contexts-chain-blt.html * igt@gem_exec_schedule@smoketest-all: - shard-tglb: [PASS][21] -> [INCOMPLETE][22] ([i915#463]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-tglb5/igt@gem_exec_sched...@smoketest-all.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/shard-tglb3/igt@gem_exec_sched...@smoketest-all.html * igt@gem_exec_schedule@smoketest-bsd2: - shard-tglb: [PASS][23] -> [INCOMPLETE][24] ([i915#707]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-tglb5/igt@gem_exec_sched...@smoketest-bsd2.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/shard-tglb3/igt@gem_exec_sched...@smoketest-bsd2.html * igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive: - shard-iclb: [PASS][25] -> [TIMEOUT][26] ([i915#530]) [25]:
[Intel-gfx] [PATCH 3/5] drm/i915/gt: Ignore stale context state upon resume
We leave the kernel_context on the HW as we suspend (and while idle).
There is no guarantee that is complete in memory, so we try to inhibit
restoration from the kernel_context. Reinforce the inhibition by
scrubbing the context.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 11 ++-
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 4f91151843d9..031d66ce5bb5 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2663,6 +2663,9 @@ static int execlists_context_alloc(struct intel_context
*ce)
static void execlists_context_reset(struct intel_context *ce)
{
+ CE_TRACE(ce, "reset\n");
+ GEM_BUG_ON(!intel_context_is_pinned(ce));
+
/*
* Because we emit WA_TAIL_DWORDS there may be a disparity
* between our bookkeeping in ce->ring->head and ce->ring->tail and
@@ -2679,8 +2682,14 @@ static void execlists_context_reset(struct intel_context
*ce)
* So to avoid that we reset the context images upon resume. For
* simplicity, we just zero everything out.
*/
- intel_ring_reset(ce->ring, 0);
+ intel_ring_reset(ce->ring, ce->ring->emit);
+
+ /* Scrub away the garbage */
+ execlists_init_reg_state(ce->lrc_reg_state,
+ce, ce->engine, ce->ring, true);
__execlists_update_reg_state(ce, ce->engine);
+
+ ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
}
static const struct intel_context_ops execlists_context_ops = {
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 066c4eddf5d0..843111b7b015 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1347,7 +1347,7 @@ static int ring_context_pin(struct intel_context *ce)
static void ring_context_reset(struct intel_context *ce)
{
- intel_ring_reset(ce->ring, 0);
+ intel_ring_reset(ce->ring, ce->ring->emit);
}
static const struct intel_context_ops ring_context_ops = {
--
2.25.0.rc0
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[Intel-gfx] [PATCH 2/5] drm/i915/gt: Clear LRC image inline
When creating the initial LRC image, we also want to clear the MI_NOOPs
and register values. Rather than use a blanket memset beforehand, apply
the clears inline, close the context image and force inhibition of the
uninitialised reminder.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c| 88 +++---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 13 ++--
2 files changed, 58 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 72490e326d66..4f91151843d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -549,9 +549,15 @@ static void hex2offsets(FILE *file)
}
*/
-static u32 *set_offsets(u32 *regs,
+static inline unsigned int dword_in_page(void *addr)
+{
+ return offset_in_page(addr) / sizeof(u32);
+}
+
+static void set_offsets(u32 *regs,
const u8 *data,
- const struct intel_engine_cs *engine)
+ const struct intel_engine_cs *engine,
+ bool clear)
#define NOP(x) (BIT(7) | (x))
#define LRI(count, flags) ((flags) << 6 | (count) | BUILD_BUG_ON_ZERO(count >=
BIT(6)))
#define POSTED BIT(0)
@@ -559,7 +565,7 @@ static u32 *set_offsets(u32 *regs,
#define REG16(x) \
(((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x1)), \
(((x) >> 2) & 0x7f)
-#define END() 0
+#define END(x) 0, (x)
{
const u32 base = engine->mmio_base;
@@ -567,7 +573,10 @@ static u32 *set_offsets(u32 *regs,
u8 count, flags;
if (*data & BIT(7)) { /* skip */
- regs += *data++ & ~BIT(7);
+ count = *data++ & ~BIT(7);
+ if (clear)
+ memset32(regs, MI_NOOP, count);
+ regs += count;
continue;
}
@@ -593,12 +602,25 @@ static u32 *set_offsets(u32 *regs,
offset |= v & ~BIT(7);
} while (v & BIT(7));
- *regs = base + (offset << 2);
+ regs[0] = base + (offset << 2);
+ if (clear)
+ regs[1] = 0;
regs += 2;
} while (--count);
}
- return regs;
+ if (clear) {
+ u8 count = *++data;
+
+ /* Clear past the tail for HW access */
+ GEM_BUG_ON(dword_in_page(regs) > count);
+ memset32(regs, MI_NOOP, count - dword_in_page(regs));
+
+ /* Close the batch; used mainly by live_lrc_layout() */
+ *regs = MI_BATCH_BUFFER_END;
+ if (INTEL_GEN(engine->i915) >= 10)
+ *regs |= BIT(0);
+ }
}
static const u8 gen8_xcs_offsets[] = {
@@ -633,7 +655,7 @@ static const u8 gen8_xcs_offsets[] = {
REG16(0x200),
REG(0x028),
- END(),
+ END(80)
};
static const u8 gen9_xcs_offsets[] = {
@@ -717,7 +739,7 @@ static const u8 gen9_xcs_offsets[] = {
REG16(0x67c),
REG(0x068),
- END(),
+ END(176)
};
static const u8 gen12_xcs_offsets[] = {
@@ -749,7 +771,7 @@ static const u8 gen12_xcs_offsets[] = {
REG16(0x274),
REG16(0x270),
- END(),
+ END(80)
};
static const u8 gen8_rcs_offsets[] = {
@@ -786,7 +808,7 @@ static const u8 gen8_rcs_offsets[] = {
LRI(1, 0),
REG(0xc8),
- END()
+ END(80)
};
static const u8 gen9_rcs_offsets[] = {
@@ -870,7 +892,7 @@ static const u8 gen9_rcs_offsets[] = {
REG16(0x67c),
REG(0x68),
- END()
+ END(176)
};
static const u8 gen11_rcs_offsets[] = {
@@ -911,7 +933,7 @@ static const u8 gen11_rcs_offsets[] = {
LRI(1, 0),
REG(0x0c8),
- END(),
+ END(80)
};
static const u8 gen12_rcs_offsets[] = {
@@ -952,7 +974,7 @@ static const u8 gen12_rcs_offsets[] = {
LRI(1, 0),
REG(0x0c8),
- END(),
+ END(80)
};
#undef END
@@ -1590,7 +1612,7 @@ static bool can_merge_rq(const struct i915_request *prev,
static void virtual_update_register_offsets(u32 *regs,
struct intel_engine_cs *engine)
{
- set_offsets(regs, reg_offsets(engine), engine);
+ set_offsets(regs, reg_offsets(engine), engine, false);
}
static bool virtual_matches(const struct virtual_engine *ve,
@@ -4104,15 +4126,19 @@ static u32 intel_lr_indirect_ctx_offset(const struct
intel_engine_cs *engine)
static void init_common_reg_state(u32 * const regs,
const struct intel_engine_cs *engine,
- const struct intel_ring *ring)
+ const struct intel_ring *ring,
+ bool inhibit)
{
- regs[CTX_CONTEXT_CONTROL] =
-
[Intel-gfx] [PATCH 1/5] drm/i915/gt: Include a bunch more rcs image state
Empirically the minimal context image we use for rcs is insufficient to
state the engine. This is demonstrated if we poison the context image
such that any uninitialised state is invalid, and so if the engine
samples beyond our defined region, will fail to start.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c| 161 +++--
drivers/gpu/drm/i915/gt/selftest_lrc.c | 7 ++
2 files changed, 161 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 00895f83f61e..72490e326d66 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -488,11 +488,72 @@ lrc_descriptor(struct intel_context *ce, struct
intel_engine_cs *engine)
return desc;
}
+/*
+static void hex2offsets(FILE *file)
+{
+ char *line = NULL;
+ size_t len = 0;
+ int lri = 0;
+ int nop = 0;
+
+ while (getline(, , file) > 0) {
+ unsigned x[8];
+ int n, i;
+ char *s;
+
+ s = strrchr(line, ']');
+ if (!s)
+ continue;
+
+ n = sscanf(s + 1, "%x %x %x %x %x %x %x %x",
+ [0], [1], [2], [3],
+ [4], [5], [6], [7]);
+ if (n <= 0)
+ continue;
+
+ for (i = 0; i < n; ) {
+ if (lri) {
+ unsigned int reg = x[i] & 0xfff;
+ if (reg > 0x200)
+ printf("REG16(%#x),\n", reg);
+ else
+ printf("REG(%#x),\n", reg);
+ if (!--lri)
+ printf("\n");
+ i += 2;
+ continue;
+ }
+ if (x[i] == 0) {
+ nop++;
+ i++;
+ continue;
+ }
+ if (nop) {
+ printf("NOP(%d),\n", nop);
+ nop = 0;
+ }
+ if (x[i] >> 24 == 0x11) {
+ lri = ((x[i] & 0xff) + 1) / 2;
+ printf("LRI(%d, %s),\n",
+ lri, (x[i] & (1 << 12) ? "POSTED" :
"0"));
+ i++;
+ continue;
+ }
+
+ printf("CMD(0x%x),\n", x[i++]);
+ }
+ }
+ printf("END()\n");
+
+ free(line);
+}
+*/
+
static u32 *set_offsets(u32 *regs,
const u8 *data,
const struct intel_engine_cs *engine)
#define NOP(x) (BIT(7) | (x))
-#define LRI(count, flags) ((flags) << 6 | (count))
+#define LRI(count, flags) ((flags) << 6 | (count) | BUILD_BUG_ON_ZERO(count >=
BIT(6)))
#define POSTED BIT(0)
#define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200))
#define REG16(x) \
@@ -695,10 +756,10 @@ static const u8 gen8_rcs_offsets[] = {
NOP(1),
LRI(14, POSTED),
REG16(0x244),
- REG(0x034),
- REG(0x030),
- REG(0x038),
- REG(0x03c),
+ REG(0x34),
+ REG(0x30),
+ REG(0x38),
+ REG(0x3c),
REG(0x168),
REG(0x140),
REG(0x110),
@@ -723,9 +784,93 @@ static const u8 gen8_rcs_offsets[] = {
NOP(13),
LRI(1, 0),
- REG(0x0c8),
+ REG(0xc8),
- END(),
+ END()
+};
+
+static const u8 gen9_rcs_offsets[] = {
+ NOP(1),
+ LRI(14, POSTED),
+ REG16(0x244),
+ REG(0x34),
+ REG(0x30),
+ REG(0x38),
+ REG(0x3c),
+ REG(0x168),
+ REG(0x140),
+ REG(0x110),
+ REG(0x11c),
+ REG(0x114),
+ REG(0x118),
+ REG(0x1c0),
+ REG(0x1c4),
+ REG(0x1c8),
+
+ NOP(3),
+ LRI(9, POSTED),
+ REG16(0x3a8),
+ REG16(0x28c),
+ REG16(0x288),
+ REG16(0x284),
+ REG16(0x280),
+ REG16(0x27c),
+ REG16(0x278),
+ REG16(0x274),
+ REG16(0x270),
+
+ NOP(13),
+ LRI(1, 0),
+ REG(0xc8),
+
+ NOP(13),
+ LRI(44, POSTED),
+ REG(0x28),
+ REG(0x9c),
+ REG(0xc0),
+ REG(0x178),
+ REG(0x17c),
+ REG16(0x358),
+ REG(0x170),
+ REG(0x150),
+ REG(0x154),
+ REG(0x158),
+ REG16(0x41c),
+ REG16(0x600),
+ REG16(0x604),
+ REG16(0x608),
+ REG16(0x60c),
+ REG16(0x610),
+ REG16(0x614),
+ REG16(0x618),
+ REG16(0x61c),
+ REG16(0x620),
+ REG16(0x624),
+ REG16(0x628),
+ REG16(0x62c),
+ REG16(0x630),
+ REG16(0x634),
+ REG16(0x638),
+
[Intel-gfx] [PATCH 4/5] drm/i915/gt: Discard stale context state from across idling
Before we idle, on parking, we switch to the kernel context such that we
have a scratch context loaded while the GPU idle, protecting any
precious user state. Be paranoid and assume that the idle state may have
been trashed, and reset the kernel_context image after idling.
Signed-off-by: Chris Wilson
Cc: Imre Deak
Reviewed-by: Matthew Auld
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 6 ++
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 8
drivers/gpu/drm/i915/gt/mock_engine.c | 5 +
3 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index cd82f0baef49..1b9f73948f22 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -20,6 +20,7 @@ static int __engine_unpark(struct intel_wakeref *wf)
{
struct intel_engine_cs *engine =
container_of(wf, typeof(*engine), wakeref);
+ struct intel_context *ce;
void *map;
ENGINE_TRACE(engine, "\n");
@@ -34,6 +35,11 @@ static int __engine_unpark(struct intel_wakeref *wf)
if (!IS_ERR_OR_NULL(map))
engine->pinned_default_state = map;
+ /* Discard stale context state from across idling */
+ ce = engine->kernel_context;
+ if (ce)
+ ce->ops->reset(ce);
+
if (engine->unpark)
engine->unpark(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 9b220c930ebc..d1c2f034296a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -213,16 +213,8 @@ int intel_gt_resume(struct intel_gt *gt)
intel_llc_enable(>llc);
for_each_engine(engine, gt, id) {
- struct intel_context *ce;
-
intel_engine_pm_get(engine);
- ce = engine->kernel_context;
- if (ce) {
- GEM_BUG_ON(!intel_context_is_pinned(ce));
- ce->ops->reset(ce);
- }
-
engine->serial++; /* kernel context lost */
err = engine->resume(engine);
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c
b/drivers/gpu/drm/i915/gt/mock_engine.c
index 4e1eafa94be9..d0e68ce9aa51 100644
--- a/drivers/gpu/drm/i915/gt/mock_engine.c
+++ b/drivers/gpu/drm/i915/gt/mock_engine.c
@@ -152,6 +152,10 @@ static int mock_context_pin(struct intel_context *ce)
return intel_context_active_acquire(ce);
}
+static void mock_context_reset(struct intel_context *ce)
+{
+}
+
static const struct intel_context_ops mock_context_ops = {
.alloc = mock_context_alloc,
@@ -161,6 +165,7 @@ static const struct intel_context_ops mock_context_ops = {
.enter = intel_context_enter_engine,
.exit = intel_context_exit_engine,
+ .reset = mock_context_reset,
.destroy = mock_context_destroy,
};
--
2.25.0.rc0
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/5] drm/i915/gt: Always poison the kernel_context image before unparking
Keep scrubbing the kernel_context image with poison before we reset it
in order to demonstrate that we will be resilient in the case where it
is accidentally overwritten on idle.
Suggested-by: Imre Deak
Signed-off-by: Chris Wilson
Cc: Imre Deak
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 2 ++
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 18 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
3 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 9527a659546c..ca1420fb8b53 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -17,6 +17,8 @@
#include "intel_engine_types.h"
#include "intel_sseu.h"
+#define CONTEXT_REDZONE POISON_INUSE
+
struct i915_gem_context;
struct i915_vma;
struct intel_context;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 1b9f73948f22..ea90ab3e396e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -37,8 +37,24 @@ static int __engine_unpark(struct intel_wakeref *wf)
/* Discard stale context state from across idling */
ce = engine->kernel_context;
- if (ce)
+ if (ce) {
+ GEM_BUG_ON(test_bit(CONTEXT_VALID_BIT, >flags));
+
+ /* First poison the image to verify we never fully trust it */
+ if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) && ce->state) {
+ struct drm_i915_gem_object *obj = ce->state->obj;
+ int type = i915_coherent_map_type(engine->i915);
+
+ map = i915_gem_object_pin_map(obj, type);
+ if (!IS_ERR(map)) {
+ memset(map, CONTEXT_REDZONE, obj->base.size);
+ i915_gem_object_flush_map(obj);
+ i915_gem_object_unpin_map(obj);
+ }
+ }
+
ce->ops->reset(ce);
+ }
if (engine->unpark)
engine->unpark(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 031d66ce5bb5..9e8440dbcbac 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2568,7 +2568,7 @@ set_redzone(void *vaddr, const struct intel_engine_cs
*engine)
vaddr += engine->context_size;
- memset(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE);
+ memset(vaddr, CONTEXT_REDZONE, I915_GTT_PAGE_SIZE);
}
static void
@@ -2579,7 +2579,7 @@ check_redzone(const void *vaddr, const struct
intel_engine_cs *engine)
vaddr += engine->context_size;
- if (memchr_inv(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE))
+ if (memchr_inv(vaddr, CONTEXT_REDZONE, I915_GTT_PAGE_SIZE))
dev_err_once(engine->i915->drm.dev,
"%s context redzone overwritten!\n",
engine->name);
--
2.25.0.rc0
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Flush the context worker
== Series Details == Series: drm/i915/selftests: Flush the context worker URL : https://patchwork.freedesktop.org/series/71495/ State : success == Summary == CI Bug Log - changes from CI_DRM_7655_full -> Patchwork_15946_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_7655_full and Patchwork_15946_full: ### New Piglit tests (9) ### * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-float_mat3-position-double_dmat3x2_array2: - Statuses : 1 fail(s) - Exec time: [0.15] s * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-float_mat4x3-double_dmat2x3-position: - Statuses : 1 fail(s) - Exec time: [0.12] s * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-byte_ivec3-double_dmat3x4: - Statuses : 1 fail(s) - Exec time: [0.13] s * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dmat2_array5-float_vec2: - Statuses : 1 fail(s) - Exec time: [0.14] s * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dmat4-double_dvec3: - Statuses : 1 fail(s) - Exec time: [0.11] s * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dvec4_array3-double_dmat2x3_array2: - Statuses : 1 fail(s) - Exec time: [0.15] s * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-uint_uvec4_array3-double_dvec3_array2-position: - Statuses : 1 fail(s) - Exec time: [0.16] s * spec@glsl-4.20@execution@vs_in@vs-input-double_dmat3x2-double_dvec3_array2-position: - Statuses : 1 fail(s) - Exec time: [0.13] s * spec@glsl-4.20@execution@vs_in@vs-input-ubyte_uint-short_ivec2-double_dvec2-position: - Statuses : 1 fail(s) - Exec time: [0.15] s Known issues Here are the changes found in Patchwork_15946_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@vcs1-queued: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7655/shard-iclb4/igt@gem_ctx_persiste...@vcs1-queued.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15946/shard-iclb5/igt@gem_ctx_persiste...@vcs1-queued.html * igt@gem_eio@unwedge-stress: - shard-snb: [PASS][3] -> [FAIL][4] ([i915#232]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7655/shard-snb7/igt@gem_...@unwedge-stress.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15946/shard-snb2/igt@gem_...@unwedge-stress.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7655/shard-iclb1/igt@gem_exec_paral...@vcs1-fds.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15946/shard-iclb6/igt@gem_exec_paral...@vcs1-fds.html * igt@gem_exec_schedule@preempt-contexts-bsd2: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +12 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7655/shard-iclb1/igt@gem_exec_sched...@preempt-contexts-bsd2.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15946/shard-iclb6/igt@gem_exec_sched...@preempt-contexts-bsd2.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7655/shard-iclb5/igt@gem_exec_sched...@preempt-other-chain-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15946/shard-iclb4/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#644]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7655/shard-glk3/igt@gem_pp...@flink-and-close-vma-leak.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15946/shard-glk1/igt@gem_pp...@flink-and-close-vma-leak.html - shard-apl: [PASS][13] -> [FAIL][14] ([i915#644]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7655/shard-apl2/igt@gem_pp...@flink-and-close-vma-leak.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15946/shard-apl6/igt@gem_pp...@flink-and-close-vma-leak.html - shard-kbl: [PASS][15] -> [FAIL][16] ([i915#644]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7655/shard-kbl6/igt@gem_pp...@flink-and-close-vma-leak.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15946/shard-kbl4/igt@gem_pp...@flink-and-close-vma-leak.html * igt@gem_sync@basic-all: - shard-tglb: [PASS][17] -> [INCOMPLETE][18] ([i915#470] / [i915#472]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7655/shard-tglb3/igt@gem_s...@basic-all.html [18]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Stop programming DDI_BUF_TRANS_SELECT on recent platforms
== Series Details == Series: drm/i915: Stop programming DDI_BUF_TRANS_SELECT on recent platforms URL : https://patchwork.freedesktop.org/series/71503/ State : success == Summary == CI Bug Log - changes from CI_DRM_7657 -> Patchwork_15950 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/index.html Known issues Here are the changes found in Patchwork_15950 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-icl-u2: [PASS][1] -> [FAIL][2] ([fdo#103375]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#111550]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_pm_rpm@module-reload: - fi-skl-lmem:[PASS][5] -> [DMESG-WARN][6] ([i915#592]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-skl-lmem/igt@i915_pm_...@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/fi-skl-lmem/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][7] -> [DMESG-FAIL][8] ([i915#553] / [i915#725]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-hsw-4770r/igt@i915_selftest@live_blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_hugepages: - fi-byt-j1900: [PASS][9] -> [DMESG-FAIL][10] ([i915#845]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-byt-j1900/igt@i915_selftest@live_hugepages.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/fi-byt-j1900/igt@i915_selftest@live_hugepages.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [INCOMPLETE][11] ([fdo#111736] / [i915#460]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@i915_module_load@reload-with-fault-injection: - fi-skl-6700k2: [INCOMPLETE][13] ([i915#671]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-skl-6700k2/igt@i915_module_l...@reload-with-fault-injection.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/fi-skl-6700k2/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_pm_rpm@module-reload: - fi-skl-guc: [INCOMPLETE][15] ([i915#151]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-skl-guc/igt@i915_pm_...@module-reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/fi-skl-guc/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_blt: - fi-ivb-3770:[DMESG-FAIL][17] ([i915#725]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-ivb-3770/igt@i915_selftest@live_blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/fi-ivb-3770/igt@i915_selftest@live_blt.html * igt@kms_busy@basic-flip-pipe-a: - fi-icl-u2: [INCOMPLETE][19] ([i915#140]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@kms_b...@basic-flip-pipe-a.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/fi-icl-u2/igt@kms_b...@basic-flip-pipe-a.html Warnings * igt@i915_module_load@reload-with-fault-injection: - fi-cfl-guc: [INCOMPLETE][21] ([i915#505] / [i915#671]) -> [DMESG-WARN][22] ([i915#889]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][23] ([i915#553] / [i915#725]) -> [DMESG-FAIL][24] ([i915#770]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-hsw-4770/igt@i915_selftest@live_blt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92]) +4 similar issues [25]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915/gt: Include a bunch more rcs image state
== Series Details == Series: series starting with [1/5] drm/i915/gt: Include a bunch more rcs image state URL : https://patchwork.freedesktop.org/series/71506/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3900059d08ce drm/i915/gt: Include a bunch more rcs image state -:22: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #22: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:492: +/* +static void hex2offsets(FILE *file) -:87: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'count' - possible side-effects? #87: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:556: +#define LRI(count, flags) ((flags) << 6 | (count) | BUILD_BUG_ON_ZERO(count >= BIT(6))) total: 0 errors, 1 warnings, 1 checks, 203 lines checked 0e75786dcac1 drm/i915/gt: Clear LRC image inline -:40: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #40: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:568: +#define END(x) 0, (x) total: 1 errors, 0 warnings, 0 checks, 239 lines checked 2f669a71fc28 drm/i915/gt: Ignore stale context state upon resume cc1692e8276b drm/i915/gt: Discard stale context state from across idling 9cc55ba3c653 drm/i915/gt: Always poison the kernel_context image before unparking ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/gt: Include a bunch more rcs image state
== Series Details == Series: series starting with [1/5] drm/i915/gt: Include a bunch more rcs image state URL : https://patchwork.freedesktop.org/series/71506/ State : success == Summary == CI Bug Log - changes from CI_DRM_7657 -> Patchwork_15951 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/index.html Known issues Here are the changes found in Patchwork_15951 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic: - fi-icl-dsi: [PASS][1] -> [DMESG-WARN][2] ([i915#109]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-dsi/igt@gem_exec_susp...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/fi-icl-dsi/igt@gem_exec_susp...@basic.html * igt@gem_exec_suspend@basic-s3: - fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#103375]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#111550]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_selftest@live_execlists: - fi-cfl-8700k: [PASS][7] -> [DMESG-FAIL][8] ([i915#841]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-cfl-8700k/igt@i915_selftest@live_execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/fi-cfl-8700k/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_gem: - fi-bwr-2160:[PASS][9] -> [FAIL][10] ([i915#878]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-bwr-2160/igt@i915_selftest@live_gem.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/fi-bwr-2160/igt@i915_selftest@live_gem.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [INCOMPLETE][11] ([fdo#111736] / [i915#460]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@i915_module_load@reload-with-fault-injection: - fi-cfl-guc: [INCOMPLETE][13] ([i915#505] / [i915#671]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_pm_rpm@module-reload: - fi-skl-guc: [INCOMPLETE][15] ([i915#151]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-skl-guc/igt@i915_pm_...@module-reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/fi-skl-guc/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][17] ([i915#553] / [i915#725]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-hsw-4770/igt@i915_selftest@live_blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@kms_busy@basic-flip-pipe-a: - fi-icl-u2: [INCOMPLETE][19] ([i915#140]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@kms_b...@basic-flip-pipe-a.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/fi-icl-u2/igt@kms_b...@basic-flip-pipe-a.html Warnings * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +5 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-kbl-x1275/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/fi-kbl-x1275/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_flip@basic-flip-vs-modeset: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-kbl-x1275/igt@kms_f...@basic-flip-vs-modeset.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/fi-kbl-x1275/igt@kms_f...@basic-flip-vs-modeset.html [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[Intel-gfx] ✓ Fi.CI.IGT: success for DP Phy compliance auto test (rev5)
== Series Details == Series: DP Phy compliance auto test (rev5) URL : https://patchwork.freedesktop.org/series/71121/ State : success == Summary == CI Bug Log - changes from CI_DRM_7656_full -> Patchwork_15948_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_7656_full and Patchwork_15948_full: ### New Piglit tests (6) ### * spec@arb_texture_multisample@texelfetch@2-vs-usampler2dms: - Statuses : 1 fail(s) - Exec time: [0.08] s * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-float_mat3x4-double_dvec3: - Statuses : 1 fail(s) - Exec time: [0.15] s * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-ubyte_uvec4-short_ivec4-position-double_dmat3x4: - Statuses : 1 fail(s) - Exec time: [0.16] s * spec@ext_transform_feedback@builtin-varyings gl_clipdistance[3]-no-subscript: - Statuses : 1 fail(s) - Exec time: [0.07] s * spec@glsl-1.50@execution@texturesize@tes-texturesize-isampler1darray: - Statuses : 1 fail(s) - Exec time: [0.09] s * spec@glsl-4.20@execution@vs_in@vs-input-position-double_dmat3-float_mat3: - Statuses : 1 fail(s) - Exec time: [0.15] s Known issues Here are the changes found in Patchwork_15948_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@processes: - shard-skl: [PASS][1] -> [FAIL][2] ([i915#570]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-skl3/igt@gem_ctx_persiste...@processes.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/shard-skl10/igt@gem_ctx_persiste...@processes.html * igt@gem_ctx_persistence@vcs1-queued: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb4/igt@gem_ctx_persiste...@vcs1-queued.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/shard-iclb7/igt@gem_ctx_persiste...@vcs1-queued.html * igt@gem_eio@in-flight-contexts-immediate: - shard-snb: [PASS][5] -> [INCOMPLETE][6] ([i915#82]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-snb6/igt@gem_...@in-flight-contexts-immediate.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/shard-snb6/igt@gem_...@in-flight-contexts-immediate.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([i915#469]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb3/igt@gem_...@unwedge-stress.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/shard-tglb1/igt@gem_...@unwedge-stress.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#110854]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb2/igt@gem_exec_balan...@smoke.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/shard-iclb8/igt@gem_exec_balan...@smoke.html * igt@gem_exec_create@madvise: - shard-tglb: [PASS][11] -> [INCOMPLETE][12] ([i915#435]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb1/igt@gem_exec_cre...@madvise.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/shard-tglb1/igt@gem_exec_cre...@madvise.html * igt@gem_exec_reloc@basic-active: - shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([i915#472]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb9/igt@gem_exec_re...@basic-active.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/shard-tglb8/igt@gem_exec_re...@basic-active.html * igt@gem_exec_schedule@preempt-queue-bsd: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#112146]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-iclb8/igt@gem_exec_sched...@preempt-queue-bsd.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/shard-iclb4/igt@gem_exec_sched...@preempt-queue-bsd.html * igt@gem_exec_schedule@preempt-queue-contexts-render: - shard-tglb: [PASS][17] -> [INCOMPLETE][18] ([fdo#111606] / [fdo#111677]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb8/igt@gem_exec_sched...@preempt-queue-contexts-render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/shard-tglb5/igt@gem_exec_sched...@preempt-queue-contexts-render.html * igt@gem_exec_schedule@preempt-queue-contexts-vebox: - shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([fdo#111677]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/shard-tglb2/igt@gem_exec_sched...@preempt-queue-contexts-vebox.html [20]:
Re: [Intel-gfx] [PATCH 2/3] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned
Quoting Imre Deak (2019-12-27 23:51:46)
> Currently the start address of a UV plane in a semiplanar YUV FB is tile
> size (4kB) aligned. I noticed, that enforcing only this alignment leads
> oddly to random memory corruptions on TGL while scanning out Y-tiled
> FBs. This issue can be easily reproduced with a UV plane that is not
> aligned to the plane's tile row size.
>
> Some experiments showed the correct alignment to be tile row size
> indeed. This also makes sense, since the de-tiling fence created for the
One would expect the implicit fence to follow the fence detiling HW
logic, which does not require tile-row alignment, just 4096 alignment
(since gen4). That suggests this logic is peculiar to the display engine.
> object - with its own stride and so "left" and "right" edge - applies to
> all the planes in the FB, so each tile row of all planes should be tile
> row aligned.
>
> In fact BSpec requires this alignment since SKL. On SKL we may enforce
> this due to the AUX plane x,y coords check, but on ICL and TGL we don't.
> For now enforce this only on TGL; I can follow up with any necessary
> change for ICL after more tests.
Considering the severity of the error, I strongly suggest we fix all
suspected machines and Cc:stable.
> BSpec requires a stricter alignment for linear UV planes too (kind of a
> tile row alignment), but it's unclear whether that's really needed
> (couldn't be explained with the de-tiling fence as above) and enforcing
> that could break existing user space; so avoid that too for now until
> more tests.
>
> Cc: Chris Wilson
> Cc: Ville Syrjälä
> Signed-off-by: Imre Deak
> ---
> +static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb,
> + int color_plane)
> +{
> + unsigned int tile_width, tile_height;
> +
> + intel_tile_dims(fb, color_plane, _width, _height);
> +
> + return fb->pitches[color_plane] * tile_height;
Ok, that is tile_row_size.
-Chris
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add support for non-power-of-2 FB plane alignment
Quoting Imre Deak (2019-12-27 23:51:45)
> At least one framebuffer plane on TGL - the UV plane of YUV semiplanar
> FBs - requires a non-power-of-2 alignment, so add support for this. This
> new alignment restriction applies only to an offset within an FB, so the
> GEM buffer itself containing the FB must still be power-of-2 aligned.
It's worth talking about virtual memory alignment (in the GGTT) here and
not the physical alignment of the backing store. The buffer itself plays
no part here.
> Add a check for this (in practice plane 0, since the plane 0 offset must
> be 0).
>
> Cc: Chris Wilson
> Cc: Ville Syrjälä
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 22 +---
> 1 file changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 624ba9be7293..d8970198c77e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2194,6 +2194,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
> return ERR_PTR(-EINVAL);
>
> alignment = intel_surf_alignment(fb, 0);
> + WARN_ON(!is_power_of_2(alignment));
Handle the error, if you are going to the trouble to warn, add the
return as well.
>
> /* Note that the w/a also requires 64 PTE of padding following the
> * bo. We currently fill all unused PTE with the shadow page and so
> @@ -2432,9 +2433,6 @@ static u32 intel_compute_aligned_offset(struct
> drm_i915_private *dev_priv,
> unsigned int cpp = fb->format->cpp[color_plane];
> u32 offset, offset_aligned;
>
> - if (alignment)
> - alignment--;
> -
> if (!is_surface_linear(fb, color_plane)) {
> unsigned int tile_size, tile_width, tile_height;
> unsigned int tile_rows, tiles, pitch_tiles;
> @@ -2456,17 +2454,24 @@ static u32 intel_compute_aligned_offset(struct
> drm_i915_private *dev_priv,
> *x %= tile_width;
>
> offset = (tile_rows * pitch_tiles + tiles) * tile_size;
> - offset_aligned = offset & ~alignment;
> +
> + offset_aligned = offset;
> + if (alignment)
> + offset_aligned = rounddown(offset_aligned, alignment);
>
> intel_adjust_tile_offset(x, y, tile_width, tile_height,
> tile_size, pitch_tiles,
> offset, offset_aligned);
> } else {
> offset = *y * pitch + *x * cpp;
> - offset_aligned = offset & ~alignment;
> -
> - *y = (offset & alignment) / pitch;
> - *x = ((offset & alignment) - *y * pitch) / cpp;
> + offset_aligned = offset;
> + if (alignment) {
> + offset_aligned = rounddown(offset_aligned, alignment);
> + *y = (offset % alignment) / pitch;
> + *x = ((offset % alignment) - *y * pitch) / cpp;
> + } else {
> + *y = *x = 0;
> + }
> }
>
> return offset_aligned;
> @@ -3738,6 +3743,7 @@ static int skl_check_main_surface(struct
> intel_plane_state *plane_state)
> intel_add_fb_offsets(, , plane_state, 0);
> offset = intel_plane_compute_aligned_offset(, , plane_state, 0);
> alignment = intel_surf_alignment(fb, 0);
> + WARN_ON(!is_power_of_2(alignment));
The other two are expected to handle !is_pot...
I would strongly suggest handling the WARNs, or else you may as well bug
out for the programming error.
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/7] drm/i915/gt: Ensure that all new contexts clear STOP_RING (rev3)
== Series Details == Series: series starting with [1/7] drm/i915/gt: Ensure that all new contexts clear STOP_RING (rev3) URL : https://patchwork.freedesktop.org/series/71479/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7653 -> Patchwork_15943 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_15943 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15943, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15943/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15943: ### IGT changes ### Possible regressions * igt@i915_selftest@live_gem_contexts: - fi-kbl-x1275: NOTRUN -> [DMESG-FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15943/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html Known issues Here are the changes found in Patchwork_15943 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][2] -> [TIMEOUT][3] ([i915#816]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7653/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15943/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@gem_exec_suspend@basic-s3: - fi-cml-s: [PASS][4] -> [DMESG-WARN][5] ([fdo#111764]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7653/fi-cml-s/igt@gem_exec_susp...@basic-s3.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15943/fi-cml-s/igt@gem_exec_susp...@basic-s3.html * igt@i915_module_load@reload-with-fault-injection: - fi-cfl-guc: [PASS][6] -> [DMESG-WARN][7] ([i915#889]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7653/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15943/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html - fi-skl-6770hq: [PASS][8] -> [DMESG-WARN][9] ([i915#889]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7653/fi-skl-6770hq/igt@i915_module_l...@reload-with-fault-injection.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15943/fi-skl-6770hq/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][10] -> [DMESG-FAIL][11] ([i915#725]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7653/fi-hsw-4770r/igt@i915_selftest@live_blt.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15943/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_execlists: - fi-kbl-soraka: [PASS][12] -> [DMESG-FAIL][13] ([i915#656]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7653/fi-kbl-soraka/igt@i915_selftest@live_execlists.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15943/fi-kbl-soraka/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_gem_contexts: - fi-hsw-4770r: [PASS][14] -> [DMESG-FAIL][15] ([i915#761]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7653/fi-hsw-4770r/igt@i915_selftest@live_gem_contexts.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15943/fi-hsw-4770r/igt@i915_selftest@live_gem_contexts.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][16] -> [FAIL][17] ([fdo#111096] / [i915#323]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7653/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15943/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][18] ([i915#725]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7653/fi-hsw-4770/igt@i915_selftest@live_blt.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15943/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-8700k: [INCOMPLETE][20] ([i915#424]) -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7653/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15943/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gt_lrc: - fi-skl-6600u: [DMESG-FAIL][22] ([i915#889]) -> [PASS][23] +7 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7653/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html
[Intel-gfx] [PATCH 3/3] drm/i915/dumb: return the allocated memory size
On successful allocation, instead returning the requested size
return the total size of allocated pages.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_gem.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7f39df3fab7f..5a53de797852 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -241,7 +241,9 @@ i915_gem_dumb_create(struct drm_file *file,
{
enum intel_memory_type mem_type = INTEL_MEMORY_SYSTEM;
int cpp = DIV_ROUND_UP(args->bpp, 8);
+ struct intel_memory_region *mr;
u32 format;
+ int ret;
switch (cpp) {
case 1:
@@ -270,8 +272,15 @@ i915_gem_dumb_create(struct drm_file *file,
if (HAS_LMEM(to_i915(dev)))
mem_type = INTEL_MEMORY_LOCAL;
- return i915_gem_create(file, to_i915(dev), mem_type,
- >size, >handle);
+ ret = i915_gem_create(file, to_i915(dev), mem_type,
+ >size, >handle);
+ if (ret)
+ goto out;
+
+ mr = intel_memory_region_by_type(to_i915(dev), mem_type);
+ args->size = ALIGN(args->size, mr->min_page_size);
+out:
+ return ret;
}
/**
--
2.20.1
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[Intel-gfx] [PATCH 1/3] drm/i915: lookup for mem_region of a mem_type
Lookup function to retrieve the pointer to a memory region of
a mem_type.
v2:
for_each_memory_region is used.
Signed-off-by: Ramalingam C
cc: Matthew Auld
Reviewed-by: Matthew Auld [v1]
---
drivers/gpu/drm/i915/intel_memory_region.c | 13 +
drivers/gpu/drm/i915/intel_memory_region.h | 3 +++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
b/drivers/gpu/drm/i915/intel_memory_region.c
index a6211cbec71e..7cb009a16b03 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -16,6 +16,19 @@ const u32 intel_region_map[] = {
[INTEL_REGION_STOLEN] = REGION_MAP(INTEL_MEMORY_STOLEN, 0),
};
+struct intel_memory_region *
+intel_memory_region_by_type(struct drm_i915_private *i915,
+ enum intel_memory_type mem_type)
+{
+ struct intel_memory_region *mr;
+ int id;
+
+ for_each_memory_region(mr, i915, id)
+ if (mr->type == mem_type)
+ return mr;
+ return NULL;
+}
+
static u64
intel_memory_region_free_pages(struct intel_memory_region *mem,
struct list_head *blocks)
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h
b/drivers/gpu/drm/i915/intel_memory_region.h
index 7f4bff8f8be1..232490d89a83 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -132,6 +132,9 @@ void intel_memory_region_put(struct intel_memory_region
*mem);
int intel_memory_regions_hw_probe(struct drm_i915_private *i915);
void intel_memory_regions_driver_release(struct drm_i915_private *i915);
+struct intel_memory_region *
+intel_memory_region_by_type(struct drm_i915_private *i915,
+ enum intel_memory_type mem_type);
__printf(2, 3) void
intel_memory_region_set_name(struct intel_memory_region *mem,
--
2.20.1
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[Intel-gfx] [PATCH 2/3] drm/i915: Create dumb buffer from LMEM
When LMEM is supported, dumb buffer preferred to be created from LMEM.
v2:
Parameters are reshuffled. [Chris]
v3:
s/region_id/mem_type
v4:
use the i915_gem_object_create_region [chris]
Signed-off-by: Ramalingam C
cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9ddcf17230e6..7f39df3fab7f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -45,6 +45,7 @@
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_ioctls.h"
#include "gem/i915_gem_mman.h"
+#include "gem/i915_gem_region.h"
#include "gt/intel_engine_user.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
@@ -201,10 +202,12 @@ i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
static int
i915_gem_create(struct drm_file *file,
struct drm_i915_private *dev_priv,
+ enum intel_memory_type mem_type,
u64 *size_p,
u32 *handle_p)
{
struct drm_i915_gem_object *obj;
+ struct intel_memory_region *mr;
u32 handle;
u64 size;
int ret;
@@ -213,8 +216,10 @@ i915_gem_create(struct drm_file *file,
if (size == 0)
return -EINVAL;
+ mr = intel_memory_region_by_type(dev_priv, mem_type);
+
/* Allocate the new object */
- obj = i915_gem_object_create_shmem(dev_priv, size);
+ obj = i915_gem_object_create_region(mr, size, 0);
if (IS_ERR(obj))
return PTR_ERR(obj);
@@ -234,6 +239,7 @@ i915_gem_dumb_create(struct drm_file *file,
struct drm_device *dev,
struct drm_mode_create_dumb *args)
{
+ enum intel_memory_type mem_type = INTEL_MEMORY_SYSTEM;
int cpp = DIV_ROUND_UP(args->bpp, 8);
u32 format;
@@ -260,7 +266,11 @@ i915_gem_dumb_create(struct drm_file *file,
args->pitch = ALIGN(args->pitch, 4096);
args->size = args->pitch * args->height;
- return i915_gem_create(file, to_i915(dev),
+
+ if (HAS_LMEM(to_i915(dev)))
+ mem_type = INTEL_MEMORY_LOCAL;
+
+ return i915_gem_create(file, to_i915(dev), mem_type,
>size, >handle);
}
@@ -279,7 +289,7 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
i915_gem_flush_free_objects(dev_priv);
- return i915_gem_create(file, dev_priv,
+ return i915_gem_create(file, dev_priv, INTEL_MEMORY_SYSTEM,
>size, >handle);
}
--
2.20.1
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[Intel-gfx] [PATCH 0/3] dumb buffer patches
Patches for getting the dumb buffer from LMEM. Ramalingam C (3): drm/i915: lookup for mem_region of a mem_type drm/i915: Create dumb buffer from LMEM drm/i915/dumb: return the allocated memory size drivers/gpu/drm/i915/i915_gem.c| 27 ++ drivers/gpu/drm/i915/intel_memory_region.c | 13 +++ drivers/gpu/drm/i915/intel_memory_region.h | 3 +++ 3 files changed, 39 insertions(+), 4 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915/psr: Share the computation of idle frames
On 2019-11-14 at 04:47:35 +0530, Souza, Jose wrote:
> On Wed, 2019-11-13 at 18:04 +0530, Anshuamn Gupta wrote:
> > Looks good to me, there is a minor comment see below.
> > On 2019-10-31 at 17:14:20 -0700, José Roberto de Souza wrote:
> > > Both activate functions and the dc3co disable function were doing
> > > the
> > > same thing, so better move to a function and share.
> > > Also while at it adding a WARN_ON to catch invalid values.
> > >
> > > Cc: Anshuman Gupta
> > > Cc: Imre Deak
> > Acked-by: Anshuman Gupta
Reviewed-by: Anshuman Gupta
> > > Signed-off-by: José Roberto de Souza
> > > ---
> > > drivers/gpu/drm/i915/display/intel_psr.c | 43 +++-
> > >
> > > 1 file changed, 19 insertions(+), 24 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 6a9f322d3fca..bb9b5349b72a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -451,22 +451,29 @@ static u32 intel_psr1_get_tp_time(struct
> > > intel_dp *intel_dp)
> > > return val;
> > > }
> > >
> > > -static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > > +static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
> > > {
> > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > - u32 max_sleep_time = 0x1f;
> > > - u32 val = EDP_PSR_ENABLE;
> > > + int idle_frames;
> > >
> > > /* Let's use 6 as the minimum to cover all known cases
> > > including the
> > >* off-by-one issue that HW has in some cases.
> > >*/
> > > - int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > > -
> > > - /* sink_sync_latency of 8 means source has to wait for more
> > > than 8
> > > - * frames, we'll go with 9 frames for now
> > > - */
> > > + idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > > idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency
> > > + 1);
> > > - val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
> > > +
> > > + WARN_ON(idle_frames > 0xf);
> > > +
> > > + return idle_frames;
> > there would be return type mismatch warning.
>
> There is not warning, the value will be truncated but if happens we
> will get the warn_on above.
>
>
> > > +}
> > > +
> > > +static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > > +{
> > > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > + u32 max_sleep_time = 0x1f;
> > > + u32 val = EDP_PSR_ENABLE;
> > > +
> > > + val |= psr_compute_idle_frames(intel_dp) <<
> > > EDP_PSR_IDLE_FRAME_SHIFT;
> > >
> > > val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
> > > if (IS_HASWELL(dev_priv))
> > > @@ -490,13 +497,7 @@ static void hsw_activate_psr2(struct intel_dp
> > > *intel_dp)
> > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > u32 val;
> > >
> > > - /* Let's use 6 as the minimum to cover all known cases
> > > including the
> > > - * off-by-one issue that HW has in some cases.
> > > - */
> > > - int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > > -
> > > - idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency
> > > + 1);
> > > - val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
> > > + val = psr_compute_idle_frames(intel_dp) <<
> > > EDP_PSR2_IDLE_FRAME_SHIFT;
> > >
> > > val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> > > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > > @@ -563,16 +564,10 @@ static void tgl_psr2_enable_dc3co(struct
> > > drm_i915_private *dev_priv)
> > >
> > > static void tgl_psr2_disable_dc3co(struct drm_i915_private
> > > *dev_priv)
> > > {
> > > - int idle_frames;
> > > + struct intel_dp *intel_dp = dev_priv->psr.dp;
> > >
> > > intel_display_power_set_target_dc_state(dev_priv,
> > > DC_STATE_EN_UPTO_DC6);
> > > - /*
> > > - * Restore PSR2 idle frame let's use 6 as the minimum to cover
> > > all known
> > > - * cases including the off-by-one issue that HW has in some
> > > cases.
> > > - */
> > > - idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > > - idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency
> > > + 1);
> > > - psr2_program_idle_frames(dev_priv, idle_frames);
> > > + psr2_program_idle_frames(dev_priv,
> > > psr_compute_idle_frames(intel_dp));
> > > }
> > >
> > > static void tgl_dc5_idle_thread(struct work_struct *work)
> > > --
> > > 2.23.0
> > >
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/dc3co: Avoid full modeset when EXITLINE needs to be changedy
On 2019-11-19 at 00:12:35 +0530, Souza, Jose wrote:
> On Sun, 2019-11-17 at 18:23 +0530, Anshuamn Gupta wrote:
> > On 2019-10-31 at 17:14:22 -0700, José Roberto de Souza wrote:
> > > A recent change in BSpec allow us to change EXTLINE while
> > > transcoder
> > > is enabled so this allow us to change it even when doing the first
> > > fastset after taking over previous hardware state set by BIOS.
> > > BIOS don't enable PSR, so if sink supports PSR it will be enabled
> > > on
> > > the first fastset, so moving the EXTLINE compute and set to PSR
> > > flows
> > > allow us to simplfy a bunch of code.
> > >
> > > This will save a lot of time in all the IGT tests that uses CRC, as
> > > when PSR2 is enabled CRCs are not generated, so we switch to PSR1,
> > > so
> > > the previous code would compute dc3co_exitline=0 causing a full
> > > modeset that would shutdown pipe, enable and train link.
> > >
> > > BSpec: 49196
> > > Cc: Imre Deak
> > > Cc: Anshuman Gupta
> > > Signed-off-by: José Roberto de Souza
> > > ---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 86
> > >
> > > drivers/gpu/drm/i915/display/intel_display.c | 1 -
> > > drivers/gpu/drm/i915/display/intel_psr.c | 47 +++
> > > 3 files changed, 47 insertions(+), 87 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index b51f244ad7a5..f52fb7619d46 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -3339,86 +3339,6 @@ static void
> > > intel_ddi_disable_fec_state(struct intel_encoder *encoder,
> > > POSTING_READ(intel_dp->regs.dp_tp_ctl);
> > > }
> > >
> > > -static void
> > > -tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state
> > > *cstate)
> > > -{
> > > - struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc-
> > > >dev);
> > > - u32 val;
> > > -
> > > - if (!cstate->dc3co_exitline)
> > > - return;
> > > -
> > > - val = I915_READ(EXITLINE(cstate->cpu_transcoder));
> > > - val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
> > > - I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
> > > -}
> > > -
> > > -static void
> > > -tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state
> > > *cstate)
> > > -{
> > > - u32 val, exit_scanlines;
> > > - struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc-
> > > >dev);
> > > -
> > > - if (!cstate->dc3co_exitline)
> > > - return;
> > > -
> > > - exit_scanlines = cstate->dc3co_exitline;
> > > - exit_scanlines <<= EXITLINE_SHIFT;
> > > - val = I915_READ(EXITLINE(cstate->cpu_transcoder));
> > > - val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
> > > - val |= exit_scanlines;
> > > - val |= EXITLINE_ENABLE;
> > > - I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
> > > -}
> > > -
> > > -static void tgl_dc3co_exitline_compute_config(struct intel_encoder
> > > *encoder,
> > > - struct intel_crtc_state
> > > *cstate)
> > > -{
> > > - u32 exit_scanlines;
> > > - struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc-
> > > >dev);
> > > - u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
> > > -
> > > - cstate->dc3co_exitline = 0;
> > > -
> > > - if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
> > > - return;
> > > -
> > > - /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
> > > - if (to_intel_crtc(cstate->base.crtc)->pipe != PIPE_A ||
> > > - encoder->port != PORT_A)
> > > - return;
> > > -
> > > - if (!cstate->has_psr2 || !cstate->base.active)
> > > - return;
> > > -
> > > - /*
> > > - * DC3CO Exit time 200us B.Spec 49196
> > > - * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line
> > > time) + 1
> > > - */
> > > - exit_scanlines =
> > > - intel_usecs_to_scanlines(>base.adjusted_mode,
> > > 200) + 1;
> > > -
> > > - if (WARN_ON(exit_scanlines > crtc_vdisplay))
> > > - return;
> > > -
> > > - cstate->dc3co_exitline = crtc_vdisplay - exit_scanlines;
> > > - DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", cstate-
> > > >dc3co_exitline);
> > > -}
> > > -
> > > -static void tgl_dc3co_exitline_get_config(struct intel_crtc_state
> > > *crtc_state)
> > > -{
> > > - u32 val;
> > > - struct drm_i915_private *dev_priv = to_i915(crtc_state-
> > > >base.crtc->dev);
> > > -
> > > - if (INTEL_GEN(dev_priv) < 12)
> > > - return;
> > > -
> > > - val = I915_READ(EXITLINE(crtc_state->cpu_transcoder));
> > > -
> > > - if (val & EXITLINE_ENABLE)
> > > - crtc_state->dc3co_exitline = val & EXITLINE_MASK;
> > > -}
> > > -
> > > static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
> > > const struct intel_crtc_state
> > > *crtc_state,
> > > const struct drm_connector_state
> > > *conn_state)
> > > @@ -3431,7 +3351,6 @@ static void tgl_ddi_pre_enable_dp(struct
> > > intel_encoder *encoder,
> >
Re: [Intel-gfx] [PATCH] drn/i915: Break up long i915_buddy_free_list() with a cond_resched()
On Sat, 21 Dec 2019 at 14:49, Chris Wilson wrote: > > In the selftests, we may feed very long lists of blocks to be freed on > culmination of the tests. This coupled with kasan and other > malloc-tracing can make the kmem_cache_free() operation time consuming, > and doing many of time trigger soft lockup warnings. Break the list up > with a cond_resched(). > > Signed-off-by: Chris Wilson > Cc: Matthew Auld Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/5] pinctrl: Allow modules to use pinctrl_[un]register_mappings
On Mon, Dec 16, 2019 at 9:51 PM Hans de Goede wrote: > Currently only the drivers/pinctrl/devicetree.c code allows registering > pinctrl-mappings which may later be unregistered, all other mappings > are assumed to be permanent. > > Non-dt platforms may also want to register pinctrl mappings from code which > is build as a module, which requires being able to unregister the mapping > when the module is unloaded to avoid dangling pointers. > > To allow unregistering the mappings the devicetree code uses 2 internal > functions: pinctrl_register_map and pinctrl_unregister_map. > > pinctrl_register_map allows the devicetree code to tell the core to > not memdup the mappings as it retains ownership of them and > pinctrl_unregister_map does the unregistering, note this only works > when the mappings where not memdupped. > > The only code relying on the memdup/shallow-copy done by > pinctrl_register_mappings is arch/arm/mach-u300/core.c this commit > replaces the __initdata with const, so that the shallow-copy is no > longer necessary. > > After that we can get rid of the internal pinctrl_unregister_map function > and just use pinctrl_register_mappings directly everywhere. > > This commit also renames pinctrl_unregister_map to > pinctrl_unregister_mappings so that its naming matches its > pinctrl_register_mappings counter-part and exports it. > > Together these 2 changes will allow non-dt platform code to > register pinctrl-mappings from modules without breaking things on > module unload (as they can now unregister the mapping on unload). > > Signed-off-by: Hans de Goede This v2 works fine for me, I applied it to this immutable branch in the pinctrl tree: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=ib-pinctrl-unreg-mappings And pulled that into the pinctrl "devel" branch for v5.6. Please pull this immutable branch into the Intel DRM tree and apply the rest of the stuff on top! Yours, Linus Walleij ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/7] drm/i915/gt: Ensure that all new contexts clear STOP_RING (rev4)
== Series Details == Series: series starting with [1/7] drm/i915/gt: Ensure that all new contexts clear STOP_RING (rev4) URL : https://patchwork.freedesktop.org/series/71479/ State : success == Summary == CI Bug Log - changes from CI_DRM_7654 -> Patchwork_15944 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/index.html Known issues Here are the changes found in Patchwork_15944 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_execlists: - fi-kbl-soraka: [PASS][1] -> [DMESG-FAIL][2] ([i915#656]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/fi-kbl-soraka/igt@i915_selftest@live_execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/fi-kbl-soraka/igt@i915_selftest@live_execlists.html * igt@kms_flip@basic-flip-vs-modeset: - fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([i915#140]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/fi-icl-dsi/igt@kms_f...@basic-flip-vs-modeset.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/fi-icl-dsi/igt@kms_f...@basic-flip-vs-modeset.html Warnings * igt@gem_exec_suspend@basic-s4-devices: - fi-kbl-x1275: [DMESG-WARN][5] ([fdo#107139] / [i915#62] / [i915#92]) -> [DMESG-WARN][6] ([fdo#107139] / [i915#62] / [i915#92] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/fi-kbl-x1275/igt@gem_exec_susp...@basic-s4-devices.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/fi-kbl-x1275/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_module_load@reload-with-fault-injection: - fi-bxt-dsi: [INCOMPLETE][7] ([fdo#103927]) -> [DMESG-WARN][8] ([i915#889]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/fi-bxt-dsi/igt@i915_module_l...@reload-with-fault-injection.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/fi-bxt-dsi/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [DMESG-FAIL][9] ([i915#553] / [i915#725]) -> [DMESG-FAIL][10] ([i915#725]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/fi-hsw-4770r/igt@i915_selftest@live_blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/fi-kbl-x1275/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/fi-kbl-x1275/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html * igt@kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/fi-kbl-x1275/igt@kms_force_connector_ba...@force-edid.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/fi-kbl-x1275/igt@kms_force_connector_ba...@force-edid.html [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139 [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#889]: https://gitlab.freedesktop.org/drm/intel/issues/889 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 34) -- Missing(16): fi-ilk-m540 fi-hsw-4200u fi-skl-6770hq fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-snb-2520m fi-kbl-7500u fi-ctg-p8600 fi-ivb-3770 fi-skl-lmem fi-byt-n2820 fi-byt-clapper fi-kbl-r fi-skl-6600u fi-snb-2600 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7654 -> Patchwork_15944 CI-20190529: 20190529 CI_DRM_7654: 210953b34f70efe0aadec97353d15cb63ee2fb4d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5354: f4e9a41fd8a13a43fd3042dcf09f40af84e7b138 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15944: 315f119daedfce6aa88067a77d88965e87dae612 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 315f119daedf drm/i915/gt: Always poison the kernel_context image before unparking 123c7d00449e drm/i915/gt: Discard stale context state from across idling
Re: [Intel-gfx] [PATCH 4/7] drm/i915/gt: Do not restore invalid RS state
On Sun, 29 Dec 2019 at 18:32, Chris Wilson wrote: > > Only restore valid resource streamer state from the context image, i.e. > avoid restoring if we know the image is invalid. > > Closes: https://gitlab.freedesktop.org/drm/intel/issues/446 > Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [bug] i915 flickering display after some of the 5.5rc3 patches
Hi Blaž, On Fri, 27 Dec 2019, Blaž Hrastnik wrote: > Hi! I'm using a Surface Laptop 3 (Intel version, i7-1065G7) which is > running the i915 driver. I have a screen flicker issue in 5.5rc that I [...] > It works on commit "x86/intel: Disable HPET on Intel Ice Lake > platforms". But it doesn't work on "drm/i915: extend audio CDCLK>=2*BCLK > constraint to more platforms" [...] > - https://patchwork.freedesktop.org/patch/334111/ thanks for the report. The flicker seems to be a side-effect of #334111, "drm/i915: extend audio CDCLK>=2*BCLK constraint to more platforms" One of the platforms the constraint was extended to, was your i7-1065G7, so there's a clear link. Fixing this is a bit more complicated. To give some context, my patches relate to HDMI/DP audio support, and specifically to fix issues in audio driver probe. When audio driver is probed (or audio device opened, as happens when you start a desktop session), audio driver will ask for display audio codec to be powered up. With my patch, this may lead to bumping up the CDCLK clock, to ensure error-free communication with audio. Same sequence happens in reverse when audio communication stops and audio driver releases resources from i915. Unfortunately the changes to CDCLK clock can lead to modeset changes and visible flicker. We've discussed the options with Ville (cc'ed) a bit, but no clear consensus yet. I've filed a ticket for this for easier tracking: https://gitlab.freedesktop.org/drm/intel/issues/913 Reverting #334111 will remove the flicker, but you may hit issue in audio driver probe (original bug here: https://github.com/thesofproject/linux/issues/1184 ). Br, Kai___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/7] drm/i915/gt: Ensure that all new contexts clear STOP_RING
On Sun, 29 Dec 2019 at 18:32, Chris Wilson wrote: > > Set up the RING_MI_NODE in new contexts to clear the STOP_RING bit, just > in case they find it still set after a reset (as they are the first > contexts to be run). > > Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/7] drm/i915/gt: Avoid using tag 0 for the very first submission
On Sun, 29 Dec 2019 at 18:32, Chris Wilson wrote: > > Assume that the HW starts off with tag 0 "active" and so avoid using tag > 0 for our own first ELSP submission. > > Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: Flush the context worker
When cleaning up the mock device, remember to flush the context worker
to free the residual GEM contexts before shutting down the device.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/802
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem.c | 4 ++--
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 ++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9ddcf17230e6..a3d701b50a6b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1172,6 +1172,8 @@ void i915_gem_driver_remove(struct drm_i915_private
*dev_priv)
void i915_gem_driver_release(struct drm_i915_private *dev_priv)
{
+ i915_gem_driver_release__contexts(dev_priv);
+
intel_gt_driver_release(_priv->gt);
intel_wa_list_free(_priv->gt_wa_list);
@@ -1179,8 +1181,6 @@ void i915_gem_driver_release(struct drm_i915_private
*dev_priv)
intel_uc_cleanup_firmwares(_priv->gt.uc);
i915_gem_cleanup_userptr(dev_priv);
- i915_gem_driver_release__contexts(dev_priv);
-
i915_gem_drain_freed_objects(dev_priv);
WARN_ON(!list_empty(_priv->gem.contexts.list));
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index ac641f5360e1..bddead3fc855 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -58,6 +58,8 @@ static void mock_device_release(struct drm_device *dev)
mock_device_flush(i915);
intel_gt_driver_remove(>gt);
+ i915_gem_driver_release__contexts(i915);
+
i915_gem_drain_workqueue(i915);
i915_gem_drain_freed_objects(i915);
--
2.25.0.rc0
___
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Intel-gfx@lists.freedesktop.org
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Re: [Intel-gfx] [PATCH 3/7] drm/i915/gt: Avoid using the GPU before initialisation
On Sun, 29 Dec 2019 at 18:32, Chris Wilson wrote: > > Mark the GT as wedged so that we are not tempted to use it prior to > initialisation. > > Signed-off-by: Chris Wilson > Cc: Andi Shyti Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for dumb buffer patches
== Series Details == Series: dumb buffer patches URL : https://patchwork.freedesktop.org/series/71493/ State : success == Summary == CI Bug Log - changes from CI_DRM_7654 -> Patchwork_15945 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/index.html Known issues Here are the changes found in Patchwork_15945 that come from known issues: ### IGT changes ### Issues hit * igt@gem_sync@basic-all: - fi-tgl-y: [PASS][1] -> [INCOMPLETE][2] ([i915#470] / [i915#472]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/fi-tgl-y/igt@gem_s...@basic-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/fi-tgl-y/igt@gem_s...@basic-all.html * igt@i915_selftest@live_blt: - fi-ivb-3770:[PASS][3] -> [DMESG-FAIL][4] ([i915#725]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/fi-ivb-3770/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/fi-ivb-3770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_reset: - fi-cfl-guc: [PASS][5] -> [DMESG-FAIL][6] ([i915#889]) +7 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/fi-cfl-guc/igt@i915_selftest@live_reset.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/fi-cfl-guc/igt@i915_selftest@live_reset.html * igt@i915_selftest@live_workarounds: - fi-cfl-guc: [PASS][7] -> [DMESG-WARN][8] ([i915#889]) +23 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/fi-cfl-guc/igt@i915_selftest@live_workarounds.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/fi-cfl-guc/igt@i915_selftest@live_workarounds.html Possible fixes * igt@gem_exec_parallel@basic: - fi-byt-n2820: [FAIL][9] ([i915#774]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/fi-byt-n2820/igt@gem_exec_paral...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/fi-byt-n2820/igt@gem_exec_paral...@basic.html * igt@i915_selftest@live_blt: - fi-byt-n2820: [DMESG-FAIL][11] ([i915#725]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/fi-byt-n2820/igt@i915_selftest@live_blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/fi-byt-n2820/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_requests: - fi-bwr-2160:[FAIL][13] ([i915#878]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/fi-bwr-2160/igt@i915_selftest@live_requests.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/fi-bwr-2160/igt@i915_selftest@live_requests.html Warnings * igt@gem_exec_suspend@basic-s4-devices: - fi-kbl-x1275: [DMESG-WARN][15] ([fdo#107139] / [i915#62] / [i915#92]) -> [DMESG-WARN][16] ([fdo#107139] / [i915#62] / [i915#92] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/fi-kbl-x1275/igt@gem_exec_susp...@basic-s4-devices.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/fi-kbl-x1275/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-guc: [SKIP][17] ([fdo#109271]) -> [FAIL][18] ([i915#704]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/fi-kbl-x1275/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/fi-kbl-x1275/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html * igt@kms_flip@basic-flip-vs-modeset: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +8 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/fi-kbl-x1275/igt@kms_f...@basic-flip-vs-modeset.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15945/fi-kbl-x1275/igt@kms_f...@basic-flip-vs-modeset.html [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470 [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#704]: https://gitlab.freedesktop.org/drm/intel/issues/704 [i915#725]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Flush the context worker
== Series Details == Series: drm/i915/selftests: Flush the context worker URL : https://patchwork.freedesktop.org/series/71495/ State : success == Summary == CI Bug Log - changes from CI_DRM_7655 -> Patchwork_15946 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15946/index.html Known issues Here are the changes found in Patchwork_15946 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][1] -> [TIMEOUT][2] ([i915#816]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7655/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15946/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_blt: - fi-ivb-3770:[PASS][3] -> [DMESG-FAIL][4] ([i915#725]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7655/fi-ivb-3770/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15946/fi-ivb-3770/igt@i915_selftest@live_blt.html Possible fixes * igt@i915_selftest@live_blt: - fi-hsw-4770r: [DMESG-FAIL][5] ([i915#725]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7655/fi-hsw-4770r/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15946/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gt_heartbeat: - fi-bsw-kefka: [DMESG-FAIL][7] ([i915#541]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7655/fi-bsw-kefka/igt@i915_selftest@live_gt_heartbeat.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15946/fi-bsw-kefka/igt@i915_selftest@live_gt_heartbeat.html Warnings * igt@gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][10] ([i915#62] / [i915#92]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7655/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15946/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7655/fi-kbl-x1275/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15946/fi-kbl-x1275/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (43 -> 41) -- Additional (5): fi-bdw-5557u fi-bwr-2160 fi-kbl-7500u fi-gdg-551 fi-blb-e6850 Missing(7): fi-kbl-soraka fi-hsw-4200u fi-byt-squawks fi-glk-dsi fi-bsw-cyan fi-bdw-samus fi-skl-6700k2 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7655 -> Patchwork_15946 CI-20190529: 20190529 CI_DRM_7655: 458613cd0994e87b92a0da86c12afddcc1f81655 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5355: 2ead76177f2546d3eec0abbd0d9e47cd36588199 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15946: c96352841329ae8960a3d786ab045def2d4f4854 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c96352841329 drm/i915/selftests: Flush the context worker == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15946/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 2/9] drm/dp: get/set phy compliance pattern
On 24-12-2019 01:23, Harry Wentland wrote:
On 2019-12-23 12:03 p.m., Animesh Manna wrote:
During phy compliance auto test mode source need to read
requested test pattern from sink through DPCD. After processing
the request source need to set the pattern. So set/get method
added in drm layer as it is DP protocol.
v2: As per review feedback from Manasi on RFC version,
- added dp revision as function argument in set_phy_pattern api.
- used int for link_rate and u8 for lane_count to align with existing code.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/drm_dp_helper.c | 93 +
include/drm/drm_dp_helper.h | 31 +++
2 files changed, 124 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 2c7870aef469..91c80973aa83 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1371,3 +1371,96 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_S
return num_bpc;
}
EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+/**
+ * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data)
+{
+ int err;
+ u8 rate, lanes;
+
+ err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, );
+ if (err < 0)
+ return err;
+ data->link_rate = drm_dp_bw_code_to_link_rate(rate);
+
+ err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, );
+ if (err < 0)
+ return err;
+ data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
+
+ if (lanes & DP_ENHANCED_FRAME_CAP)
+ data->enahanced_frame_cap = true;
+
+ err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, >phy_pattern);
+ if (err < 0)
+ return err;
+
+ switch (data->phy_pattern) {
+ case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
+ err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
+ >custom80, 10);
Using sizeof(data->custom80) might be safer.
+ if (err < 0)
+ return err;
+
+ break;
+ case DP_PHY_TEST_PATTERN_CP2520:
+ err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
+ >hbr2_reset, 2);
Same here, using sizeof(data->hbr2_reset).
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
+
+/**
+ * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data, u8 dp_rev)
+{
+ int err, i;
+ u8 link_config[2];
+ u8 test_pattern;
+
+ link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
+ link_config[1] = data->num_lanes;
+ if (data->enahanced_frame_cap)
+ link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+ err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
+ if (err < 0)
+ return err;
+
+ test_pattern = data->phy_pattern;
+ if (dp_rev < 0x12) {
+ test_pattern = (test_pattern << 2) &
+ DP_LINK_QUAL_PATTERN_11_MASK;
+ err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
+test_pattern);
+ if (err < 0)
+ return err;
+ } else {
+ for (i = 0; i < data->num_lanes; i++) {
+ err = drm_dp_dpcd_writeb(aux,
+DP_LINK_QUAL_LANE0_SET + i,
+test_pattern);
+ if (err < 0)
+ return err;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index d6e560870fb1..42a364748308 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -700,6 +700,15 @@
# define DP_TEST_COUNT_MASK 0xf
#define DP_PHY_TEST_PATTERN 0x248
+# define DP_PHY_TEST_PATTERN_SEL_MASK 0x7
+# define DP_PHY_TEST_PATTERN_NONE 0x0
+# define DP_PHY_TEST_PATTERN_D10_2 0x1
+# define DP_PHY_TEST_PATTERN_ERROR_COUNT0x2
+# define DP_PHY_TEST_PATTERN_PRBS7 0x3
+# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
+# define
Re: [Intel-gfx] [PATCH 1/6] drm/i915/selftests: Flush the context worker
Chris Wilson writes:
> When cleaning up the mock device, remember to flush the context worker
> to free the residual GEM contexts before shutting down the device.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/802
> Signed-off-by: Chris Wilson
> Cc: Matthew Auld
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_gem.c | 4 ++--
> drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 ++
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 9ddcf17230e6..a3d701b50a6b 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1172,6 +1172,8 @@ void i915_gem_driver_remove(struct drm_i915_private
> *dev_priv)
>
> void i915_gem_driver_release(struct drm_i915_private *dev_priv)
> {
> + i915_gem_driver_release__contexts(dev_priv);
> +
> intel_gt_driver_release(_priv->gt);
>
> intel_wa_list_free(_priv->gt_wa_list);
> @@ -1179,8 +1181,6 @@ void i915_gem_driver_release(struct drm_i915_private
> *dev_priv)
> intel_uc_cleanup_firmwares(_priv->gt.uc);
> i915_gem_cleanup_userptr(dev_priv);
>
> - i915_gem_driver_release__contexts(dev_priv);
> -
> i915_gem_drain_freed_objects(dev_priv);
>
> WARN_ON(!list_empty(_priv->gem.contexts.list));
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index 2b01094e4318..3b8986983afc 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -58,6 +58,8 @@ static void mock_device_release(struct drm_device *dev)
> mock_device_flush(i915);
> intel_gt_driver_remove(>gt);
>
> + i915_gem_driver_release__contexts(i915);
> +
> i915_gem_drain_workqueue(i915);
> i915_gem_drain_freed_objects(i915);
>
> --
> 2.25.0.rc0
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Flush the context worker
Quoting Mika Kuoppala (2019-12-30 16:00:22)
> Chris Wilson writes:
>
> > When cleaning up the mock device, remember to flush the context worker
> > to free the residual GEM contexts before shutting down the device.
> >
> > Closes: https://gitlab.freedesktop.org/drm/intel/issues/802
> > Signed-off-by: Chris Wilson
> > Cc: Matthew Auld
> > ---
> > drivers/gpu/drm/i915/i915_gem.c | 4 ++--
> > drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 ++
> > 2 files changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c
> > b/drivers/gpu/drm/i915/i915_gem.c
> > index 9ddcf17230e6..a3d701b50a6b 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -1172,6 +1172,8 @@ void i915_gem_driver_remove(struct drm_i915_private
> > *dev_priv)
> >
> > void i915_gem_driver_release(struct drm_i915_private *dev_priv)
> > {
> > + i915_gem_driver_release__contexts(dev_priv);
> > +
> > intel_gt_driver_release(_priv->gt);
> >
> > intel_wa_list_free(_priv->gt_wa_list);
> > @@ -1179,8 +1181,6 @@ void i915_gem_driver_release(struct drm_i915_private
> > *dev_priv)
> > intel_uc_cleanup_firmwares(_priv->gt.uc);
> > i915_gem_cleanup_userptr(dev_priv);
> >
> > - i915_gem_driver_release__contexts(dev_priv);
> > -
>
> Have I missed some memo on double underscores?
Nah, it's something I've tried that has caught on. For situations like
this where we are calling a subroutine for a subphase, and not operating
on a subobject.
We could do i915_gem_contexts_driver_release(>gem.contexts) which is
probably more sensible now that we have i915->gem.contexts.
-Chris
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Re: [Intel-gfx] [PATCH 3/6] drm/i915/gt: Leave RING_BB_STATE to default value
Chris Wilson writes: > Do not reset RING_BB_STATE, leaving it to the default state value. This > prevents bdw/bsw from getting confused when executing batches from the > GGTT. Happily setting up ro registers through ctx image, stamped my me... Reviewed-by: Mika Kuoppala > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c > b/drivers/gpu/drm/i915/gt/intel_lrc.c > index f0618e6aabd5..2bf6dc6d528d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -3982,7 +3982,6 @@ static void init_common_reg_state(u32 * const regs, > regs[CTX_CONTEXT_CONTROL] = ctl; > > regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID; > - regs[CTX_BB_STATE] = RING_BB_PPGTT; > } > > static void init_wa_bb_reg_state(u32 * const regs, > -- > 2.25.0.rc0 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 7/7] drm/i915/gt: Always poison the kernel_context image before unparking
On Sun, 29 Dec 2019 at 18:32, Chris Wilson wrote: > > Keep scrubbing the kernel_context image with poison before we reset it > in order to demonstrate that we will be resilient in the case where it > is accidentally overwritten on idle. > > Suggested-by: Imre Deak > Signed-off-by: Chris Wilson > Cc: Imre Deak Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/6] drm/i915/gt: Discard stale context state from across idling
Chris Wilson writes:
> Before we idle, on parking, we switch to the kernel context such that we
> have a scratch context loaded while the GPU idle, protecting any
> precious user state. Be paranoid and assume that the idle state may have
> been trashed, and reset the kernel_context image after idling.
>
> Signed-off-by: Chris Wilson
> Cc: Imre Deak
> ---
> drivers/gpu/drm/i915/gt/intel_engine_pm.c | 6 ++
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 8
> drivers/gpu/drm/i915/gt/mock_engine.c | 5 +
> 3 files changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> index cd82f0baef49..1b9f73948f22 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> @@ -20,6 +20,7 @@ static int __engine_unpark(struct intel_wakeref *wf)
> {
> struct intel_engine_cs *engine =
> container_of(wf, typeof(*engine), wakeref);
> + struct intel_context *ce;
> void *map;
>
> ENGINE_TRACE(engine, "\n");
> @@ -34,6 +35,11 @@ static int __engine_unpark(struct intel_wakeref *wf)
> if (!IS_ERR_OR_NULL(map))
> engine->pinned_default_state = map;
>
> + /* Discard stale context state from across idling */
> + ce = engine->kernel_context;
> + if (ce)
> + ce->ops->reset(ce);
> +
Expect the worst, sure.
Checksum would get us datapoints tho.
Reviewed-by: Mika Kuoppala
> if (engine->unpark)
> engine->unpark(engine);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index 9b220c930ebc..d1c2f034296a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -213,16 +213,8 @@ int intel_gt_resume(struct intel_gt *gt)
> intel_llc_enable(>llc);
>
> for_each_engine(engine, gt, id) {
> - struct intel_context *ce;
> -
> intel_engine_pm_get(engine);
>
> - ce = engine->kernel_context;
> - if (ce) {
> - GEM_BUG_ON(!intel_context_is_pinned(ce));
> - ce->ops->reset(ce);
> - }
> -
> engine->serial++; /* kernel context lost */
> err = engine->resume(engine);
>
> diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c
> b/drivers/gpu/drm/i915/gt/mock_engine.c
> index 4e1eafa94be9..d0e68ce9aa51 100644
> --- a/drivers/gpu/drm/i915/gt/mock_engine.c
> +++ b/drivers/gpu/drm/i915/gt/mock_engine.c
> @@ -152,6 +152,10 @@ static int mock_context_pin(struct intel_context *ce)
> return intel_context_active_acquire(ce);
> }
>
> +static void mock_context_reset(struct intel_context *ce)
> +{
> +}
> +
> static const struct intel_context_ops mock_context_ops = {
> .alloc = mock_context_alloc,
>
> @@ -161,6 +165,7 @@ static const struct intel_context_ops mock_context_ops = {
> .enter = intel_context_enter_engine,
> .exit = intel_context_exit_engine,
>
> + .reset = mock_context_reset,
> .destroy = mock_context_destroy,
> };
>
> --
> 2.25.0.rc0
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH v3 2/9] drm/dp: get/set phy compliance pattern
On 30-12-2019 21:41, Harry Wentland wrote:
On 2019-12-30 11:05 a.m., Manna, Animesh wrote:
On 24-12-2019 01:23, Harry Wentland wrote:
On 2019-12-23 12:03 p.m., Animesh Manna wrote:
During phy compliance auto test mode source need to read
requested test pattern from sink through DPCD. After processing
the request source need to set the pattern. So set/get method
added in drm layer as it is DP protocol.
v2: As per review feedback from Manasi on RFC version,
- added dp revision as function argument in set_phy_pattern api.
- used int for link_rate and u8 for lane_count to align with
existing code.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/drm_dp_helper.c | 93
+
include/drm/drm_dp_helper.h | 31 +++
2 files changed, 124 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c
b/drivers/gpu/drm/drm_dp_helper.c
index 2c7870aef469..91c80973aa83 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1371,3 +1371,96 @@ int
drm_dp_dsc_sink_supported_input_bpcs(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_S
return num_bpc;
}
EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+/**
+ * drm_dp_get_phy_test_pattern() - get the requested pattern from
the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data)
+{
+ int err;
+ u8 rate, lanes;
+
+ err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, );
+ if (err < 0)
+ return err;
+ data->link_rate = drm_dp_bw_code_to_link_rate(rate);
+
+ err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, );
+ if (err < 0)
+ return err;
+ data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
+
+ if (lanes & DP_ENHANCED_FRAME_CAP)
+ data->enahanced_frame_cap = true;
+
+ err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN,
>phy_pattern);
+ if (err < 0)
+ return err;
+
+ switch (data->phy_pattern) {
+ case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
+ err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
+ >custom80, 10);
Using sizeof(data->custom80) might be safer.
+ if (err < 0)
+ return err;
+
+ break;
+ case DP_PHY_TEST_PATTERN_CP2520:
+ err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
+ >hbr2_reset, 2);
Same here, using sizeof(data->hbr2_reset).
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
+
+/**
+ * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data, u8 dp_rev)
+{
+ int err, i;
+ u8 link_config[2];
+ u8 test_pattern;
+
+ link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
+ link_config[1] = data->num_lanes;
+ if (data->enahanced_frame_cap)
+ link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+ err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
+ if (err < 0)
+ return err;
+
+ test_pattern = data->phy_pattern;
+ if (dp_rev < 0x12) {
+ test_pattern = (test_pattern << 2) &
+ DP_LINK_QUAL_PATTERN_11_MASK;
+ err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
+ test_pattern);
+ if (err < 0)
+ return err;
+ } else {
+ for (i = 0; i < data->num_lanes; i++) {
+ err = drm_dp_dpcd_writeb(aux,
+ DP_LINK_QUAL_LANE0_SET + i,
+ test_pattern);
+ if (err < 0)
+ return err;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index d6e560870fb1..42a364748308 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -700,6 +700,15 @@
# define DP_TEST_COUNT_MASK 0xf
#define DP_PHY_TEST_PATTERN 0x248
+# define DP_PHY_TEST_PATTERN_SEL_MASK 0x7
+# define DP_PHY_TEST_PATTERN_NONE 0x0
+# define DP_PHY_TEST_PATTERN_D10_2 0x1
+# define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
+# define DP_PHY_TEST_PATTERN_PRBS7 0x3
+# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
+# define DP_PHY_TEST_PATTERN_CP2520 0x5
+
+#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
@@ -1570,4 +1579,26 @@ static inline void
[Intel-gfx] [CI 2/2] drm/i915/gt: Leave RING_BB_STATE to default value
Do not reset RING_BB_STATE, leaving it to the default state value. This prevents bdw/bsw from getting confused when executing batches from the GGTT. Signed-off-by: Chris Wilson Acked-by: Matthew Auld Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_lrc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 14e7e179855f..00895f83f61e 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3968,7 +3968,6 @@ static void init_common_reg_state(u32 * const regs, CTX_CTRL_RS_CTX_ENABLE); regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID; - regs[CTX_BB_STATE] = RING_BB_PPGTT; } static void init_wa_bb_reg_state(u32 * const regs, -- 2.25.0.rc0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DP Phy compliance auto test (rev5)
== Series Details ==
Series: DP Phy compliance auto test (rev5)
URL : https://patchwork.freedesktop.org/series/71121/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8a55c99e987a drm/amd/display: Align macro name as per DP spec
b46d414a1888 drm/dp: get/set phy compliance pattern
eaa338c1dc20 drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
d7fed7271de6 drm/i915/dp: Preparation for DP phy compliance auto test
24a9becfee75 drm/i915/dsb: Send uevent to testapp.
82604acfc432 drm/i915/dp: Add debugfs entry for DP phy compliance.
379c984a0e16 drm/i915/dp: Register definition for DP compliance register
8b30e6e85d43 drm/i915/dp: Update the pattern as per request
ebbce9a8cc0e drm/i915/dp: [FIXME] Program vswing, pre-emphasis, test-pattern
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#11:
series. Some temporary fix added and the patch is under-development, not for
-:40: ERROR:SPACING: space required before the open parenthesis '('
#40: FILE: drivers/gpu/drm/i915/display/intel_display.c:15219:
+ if(dev_priv->dp_phy_comp) {
-:66: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional
statements (8, 8)
#66: FILE: drivers/gpu/drm/i915/display/intel_display.c:15456:
+ if (!dev_priv->dp_phy_comp) {
i915_sw_fence_init(>commit_ready,
-:80: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional
statements (8, 8)
#80: FILE: drivers/gpu/drm/i915/display/intel_display.c:15501:
+ if (!dev_priv->dp_phy_comp) {
if (ret) {
-:97: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional
statements (8, 8)
#97: FILE: drivers/gpu/drm/i915/display/intel_display.c:15529:
+ if (!dev_priv->dp_phy_comp) {
i915_sw_fence_commit(>commit_ready);
-:97: WARNING:BRACES: braces {} are not necessary for single statement blocks
#97: FILE: drivers/gpu/drm/i915/display/intel_display.c:15529:
+ if (!dev_priv->dp_phy_comp) {
i915_sw_fence_commit(>commit_ready);
+ }
total: 1 errors, 5 warnings, 0 checks, 181 lines checked
___
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[Intel-gfx] [CI 1/2] drm/i915/selftests: Flush the context worker
When cleaning up the mock device, remember to flush the context worker
to free the residual GEM contexts before shutting down the device.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/802
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem.c | 4 ++--
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 ++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9ddcf17230e6..a3d701b50a6b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1172,6 +1172,8 @@ void i915_gem_driver_remove(struct drm_i915_private
*dev_priv)
void i915_gem_driver_release(struct drm_i915_private *dev_priv)
{
+ i915_gem_driver_release__contexts(dev_priv);
+
intel_gt_driver_release(_priv->gt);
intel_wa_list_free(_priv->gt_wa_list);
@@ -1179,8 +1181,6 @@ void i915_gem_driver_release(struct drm_i915_private
*dev_priv)
intel_uc_cleanup_firmwares(_priv->gt.uc);
i915_gem_cleanup_userptr(dev_priv);
- i915_gem_driver_release__contexts(dev_priv);
-
i915_gem_drain_freed_objects(dev_priv);
WARN_ON(!list_empty(_priv->gem.contexts.list));
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 2b01094e4318..3b8986983afc 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -58,6 +58,8 @@ static void mock_device_release(struct drm_device *dev)
mock_device_flush(i915);
intel_gt_driver_remove(>gt);
+ i915_gem_driver_release__contexts(i915);
+
i915_gem_drain_workqueue(i915);
i915_gem_drain_freed_objects(i915);
--
2.25.0.rc0
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[Intel-gfx] ✓ Fi.CI.BAT: success for DP Phy compliance auto test (rev5)
== Series Details == Series: DP Phy compliance auto test (rev5) URL : https://patchwork.freedesktop.org/series/71121/ State : success == Summary == CI Bug Log - changes from CI_DRM_7656 -> Patchwork_15948 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/index.html Known issues Here are the changes found in Patchwork_15948 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-bsw-nick:[PASS][1] -> [DMESG-FAIL][2] ([i915#723]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-bsw-nick/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/fi-bsw-nick/igt@i915_selftest@live_blt.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-j1900: [TIMEOUT][3] ([i915#816]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@i915_module_load@reload-with-fault-injection: - fi-bxt-dsi: [INCOMPLETE][5] ([fdo#103927]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-bxt-dsi/igt@i915_module_l...@reload-with-fault-injection.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/fi-bxt-dsi/igt@i915_module_l...@reload-with-fault-injection.html - fi-cfl-8700k: [INCOMPLETE][7] ([i915#505]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-cfl-8700k/igt@i915_module_l...@reload-with-fault-injection.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/fi-cfl-8700k/igt@i915_module_l...@reload-with-fault-injection.html - fi-skl-6770hq: [INCOMPLETE][9] ([i915#671]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-skl-6770hq/igt@i915_module_l...@reload-with-fault-injection.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/fi-skl-6770hq/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_selftest@live_blt: - fi-byt-j1900: [DMESG-FAIL][11] ([i915#725]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-byt-j1900/igt@i915_selftest@live_blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/fi-byt-j1900/igt@i915_selftest@live_blt.html - fi-hsw-4770:[DMESG-FAIL][13] ([i915#563]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-hsw-4770/igt@i915_selftest@live_blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/fi-hsw-4770/igt@i915_selftest@live_blt.html Warnings * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-kbl-x1275/igt@kms_cursor_leg...@basic-flip-before-cursor-varying-size.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/fi-kbl-x1275/igt@kms_cursor_leg...@basic-flip-before-cursor-varying-size.html * igt@kms_flip@basic-flip-vs-modeset: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +9 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-kbl-x1275/igt@kms_f...@basic-flip-vs-modeset.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15948/fi-kbl-x1275/igt@kms_f...@basic-flip-vs-modeset.html [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [i915#505]: https://gitlab.freedesktop.org/drm/intel/issues/505 [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#671]: https://gitlab.freedesktop.org/drm/intel/issues/671 [i915#723]: https://gitlab.freedesktop.org/drm/intel/issues/723 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (46 -> 38) -- Additional (4): fi-hsw-4770r fi-tgl-y fi-byt-n2820 fi-bwr-2160 Missing(12): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-whl-u fi-ivb-3770 fi-skl-6600u fi-bdw-samus fi-byt-clapper fi-skl-6700k2 fi-snb-2600 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7656 -> Patchwork_15948 CI-20190529: 20190529 CI_DRM_7656: 635576de746ef28c1635b4cf4fb12f4db1104f8b @
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915/selftests: Flush the context worker
== Series Details == Series: series starting with [CI,1/2] drm/i915/selftests: Flush the context worker URL : https://patchwork.freedesktop.org/series/71500/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7656 -> Patchwork_15949 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_15949 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15949, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15949/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15949: ### IGT changes ### Possible regressions * igt@i915_selftest@live_sanitycheck: - fi-skl-lmem:NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15949/fi-skl-lmem/igt@i915_selftest@live_sanitycheck.html Known issues Here are the changes found in Patchwork_15949 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload-with-fault-injection: - fi-cfl-guc: [PASS][2] -> [INCOMPLETE][3] ([i915#505] / [i915#671]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15949/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html * igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling: - fi-icl-dsi: [PASS][4] -> [DMESG-WARN][5] ([i915#109]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-icl-dsi/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15949/fi-icl-dsi/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html Possible fixes * igt@i915_module_load@reload-with-fault-injection: - fi-bxt-dsi: [INCOMPLETE][6] ([fdo#103927]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-bxt-dsi/igt@i915_module_l...@reload-with-fault-injection.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15949/fi-bxt-dsi/igt@i915_module_l...@reload-with-fault-injection.html - fi-cfl-8700k: [INCOMPLETE][8] ([i915#505]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-cfl-8700k/igt@i915_module_l...@reload-with-fault-injection.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15949/fi-cfl-8700k/igt@i915_module_l...@reload-with-fault-injection.html - fi-skl-6700k2: [INCOMPLETE][10] ([i915#671]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-skl-6700k2/igt@i915_module_l...@reload-with-fault-injection.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15949/fi-skl-6700k2/igt@i915_module_l...@reload-with-fault-injection.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][12] ([fdo#111096] / [i915#323]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15949/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Warnings * igt@i915_module_load@reload-with-fault-injection: - fi-skl-lmem:[INCOMPLETE][14] ([i915#671]) -> [DMESG-WARN][15] ([i915#889]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-skl-lmem/igt@i915_module_l...@reload-with-fault-injection.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15949/fi-skl-lmem/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][16] ([i915#563]) -> [DMESG-FAIL][17] ([i915#770]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-hsw-4770/igt@i915_selftest@live_blt.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15949/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][18] ([i915#62] / [i915#92]) -> [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-kbl-x1275/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15949/fi-kbl-x1275/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html * igt@kms_flip@basic-flip-vs-modeset: - fi-kbl-x1275: [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][21] ([i915#62] / [i915#92]) +5 similar issues [20]:
Re: [Intel-gfx] [PATCH] drm/i915: save AUD_FREQ_CNTRL state at audio domain suspend
Hey Matt, On Tue, 24 Dec 2019, Matt Roper wrote: > > When audio power domain is suspended, the display driver must > > save state of AUD_FREQ_CNTRL on Tiger Lake and Ice Lake > > systems. The initial value of the register is set by BIOS and > > I realize this patch landed several months ago, but I was just glancing > through places in the driver where we call out specific platforms with > IS_FOO() rather than using generation tests and noticed this one. > Should this programming be specific to just ICL and TGL, or should it > also apply to other recent platforms like EHL/JSL? > > Our convention in i915 is to usually just assume that future platforms > will follow the lead of the current latest platform until we find out > otherwise. So we may want to add another patch to change the test to this is a valid point. The current check is very limited as the issue has been only observed on these platforms (but was very severe on these devices so a quick response was needed). I did observe originally that specs would indicate the register should be saved on many other platforms as well. I was hesitant to add this to the patch, as there are many platforms that have been shipping for years with no issues reported on this. But, but, I think we should just proceed and extend the check to all documented platforms, past and future (basicly INTEL_GEN>=9). I can make a patch and let's see how it fares in CI. Br, Kai ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/6] drm/i915/gt: Ignore stale context state upon resume
Quoting Chris Wilson (2019-12-30 16:01:10) > We leave the kernel_context on the HW as we suspend (and while idle). > There is no guarantee that is complete in memory, so we try to inhibit > restoration from the kernel_context. Reinforce the inhibition by > scrubbing the context. > > Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 7/9] drm/i915/dp: Register definition for DP compliance register
DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 030a3f3e69af..a536d920324c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9794,6 +9794,26 @@ enum skl_power_gate {
#define DDI_BUF_BALANCE_LEG_ENABLE(1 << 31)
#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A,
_DDI_BUF_TRANS_B) + (i) * 8 + 4)
+/* DDI DP Compliance Control */
+#define DDI_DP_COMP_CTL_A 0x605F0
+#define DDI_DP_COMP_CTL_B 0x615F0
+#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, \
+DDI_DP_COMP_CTL_B)
+#define DDI_DP_COMP_CTL_ENABLE(1 << 31)
+#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
+#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
+#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
+#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
+#define DDI_DP_COMP_CTL_HBR2_RESET(0xFC << 0)
+
+/* DDI DP Compliance Pattern */
+#define DDI_DP_COMP_PAT_A 0x605F4
+#define DDI_DP_COMP_PAT_B 0x615F4
+#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, \
+DDI_DP_COMP_PAT_B) + (i) * 4)
+
/* Sideband Interface (SBI) is programmed indirectly, via
* SBI_ADDR, which contains the register offset; and SBI_DATA,
* which contains the payload */
--
2.24.0
___
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[Intel-gfx] [PATCH v3 5/9] drm/i915/dsb: Send uevent to testapp.
Send uevent to testapp and set test_active flag. To align with link
compliance design existing intel_dp_compliance tool will be used to
get the phy request in userspace through uevent.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index fa67b8f88e65..cbefda9b6204 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5013,6 +5013,9 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp)
if (test_result != DP_TEST_ACK)
DRM_ERROR("Phy test preparation failed\n");
+ /* Set test active flag here so userspace doesn't interrupt things */
+ intel_dp->compliance.test_active = 1;
+
return test_result;
}
@@ -5338,8 +5341,11 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
intel_psr_short_pulse(intel_dp);
- if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
- DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
+ if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING ||
+ intel_dp->compliance.test_type ==
+ DP_TEST_LINK_PHY_TEST_PATTERN) {
+ DRM_DEBUG_KMS("Compliance Test requested, test-type = 0x%lx\n",
+ intel_dp->compliance.test_type);
/* Send a Hotplug Uevent to userspace to start modeset */
drm_kms_helper_hotplug_event(_priv->drm);
}
--
2.24.0
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[Intel-gfx] [PATCH v3 0/9] DP Phy compliance auto test
Driver changes mainly to process the request coming from Test equipment as short pulse hpd interrupt to change link-pattern/v-swing/pre-emphasis Complete auto test suite takes much lesser time than manual run. Overall design: -- Automate test request will come to source device as HDP short pulse interrupt from test scope. Read DPCD 0x201, Check for bit 1 for automated test request. If set continue and read DPCD 0x218. Check for bit 3 for phy test pattern, If set continue. Get the requested test pattern through DPCD 0x248. Compute requested voltage swing level and pre-emphasis level from DPCD 0x206 and 0x207 Set signal level through vswing programming sequence. Write DDI_COMP_CTL and DDI_COMP_PATx as per requested pattern. Configure the link and write the new test pattern through DPCD. High level patch description. - patch 1: drm level api added to get/set test pattern as per vesa DP spec. This maybe useful for other driver so added in drm layer. patch 2: Fix for a compilation issue. patch 3: vswing/preemphasis adjustment calculation is needed during phy compliance request processing along with existing link training process, so moved the same function in intel_dp.c. patch 4: Parse the test scope request regarding rquested test pattern, vswing level, preemphasis level. patch 5: Notify testapp through uevent. patch 6: Added debugfs entry for phy compliance. patch 7: Register difnition of DP compliance register added. patch 8: Function added to update the pattern in source side. patch 9: This patch os mainly processing the request. Currently through prototyping patch able to run DP compliance where vswing, preemphasis and test pattern is changing fine but complete test is under process. As per feedback redesigned the code. Could not test due to unavailability of test scope, so sending as RFC again to get design feedback. v1: Redesigned the code as per review feedback from Manasi on RFC. v2: Addressed review comments from Manasi. v3: Addressed review commnets from Harry, Ville, Jani. Animesh Manna (9): drm/amd/display: Align macro name as per DP spec drm/dp: get/set phy compliance pattern drm/i915/dp: Move vswing/pre-emphasis adjustment calculation drm/i915/dp: Preparation for DP phy compliance auto test drm/i915/dsb: Send uevent to testapp. drm/i915/dp: Add debugfs entry for DP phy compliance. drm/i915/dp: Register definition for DP compliance register drm/i915/dp: Update the pattern as per request drm/i915/dp: [FIXME] Program vswing, pre-emphasis, test-pattern .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +- drivers/gpu/drm/drm_dp_helper.c | 94 + drivers/gpu/drm/i915/display/intel_display.c | 24 ++- .../drm/i915/display/intel_display_types.h| 1 + drivers/gpu/drm/i915/display/intel_dp.c | 197 +- drivers/gpu/drm/i915/display/intel_dp.h | 6 + .../drm/i915/display/intel_dp_link_training.c | 36 +--- drivers/gpu/drm/i915/i915_debugfs.c | 12 +- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 20 ++ include/drm/drm_dp_helper.h | 33 ++- 11 files changed, 387 insertions(+), 40 deletions(-) -- 2.24.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 6/6] drm/i915/gt: Always poison the kernel_context image before unparking
Chris Wilson writes:
> Keep scrubbing the kernel_context image with poison before we reset it
> in order to demonstrate that we will be resilient in the case where it
> is accidentally overwritten on idle.
>
> Suggested-by: Imre Deak
> Signed-off-by: Chris Wilson
> Cc: Imre Deak
> ---
> drivers/gpu/drm/i915/gt/intel_context_types.h | 2 ++
> drivers/gpu/drm/i915/gt/intel_engine_pm.c | 18 +-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
> 3 files changed, 21 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
> b/drivers/gpu/drm/i915/gt/intel_context_types.h
> index 9527a659546c..ca1420fb8b53 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> @@ -17,6 +17,8 @@
> #include "intel_engine_types.h"
> #include "intel_sseu.h"
>
> +#define CONTEXT_REDZONE POISON_INUSE
> +
> struct i915_gem_context;
> struct i915_vma;
> struct intel_context;
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> index 1b9f73948f22..ea90ab3e396e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> @@ -37,8 +37,24 @@ static int __engine_unpark(struct intel_wakeref *wf)
>
> /* Discard stale context state from across idling */
> ce = engine->kernel_context;
> - if (ce)
> + if (ce) {
> + GEM_BUG_ON(test_bit(CONTEXT_VALID_BIT, >flags));
> +
> + /* First poison the image to verify we never fully trust it */
> + if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) && ce->state) {
> + struct drm_i915_gem_object *obj = ce->state->obj;
> + int type = i915_coherent_map_type(engine->i915);
> +
> + map = i915_gem_object_pin_map(obj, type);
> + if (!IS_ERR(map)) {
> + memset(map, CONTEXT_REDZONE, obj->base.size);
Just pondering if the dword granularity would suffice.
Reviewed-by: Mika Kuoppala
> + i915_gem_object_flush_map(obj);
> + i915_gem_object_unpin_map(obj);
> + }
> + }
> +
> ce->ops->reset(ce);
> + }
>
> if (engine->unpark)
> engine->unpark(engine);
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 6d26d84812b6..f81e70cfd194 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2409,7 +2409,7 @@ set_redzone(void *vaddr, const struct intel_engine_cs
> *engine)
>
> vaddr += engine->context_size;
>
> - memset(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE);
> + memset(vaddr, CONTEXT_REDZONE, I915_GTT_PAGE_SIZE);
> }
>
> static void
> @@ -2420,7 +2420,7 @@ check_redzone(const void *vaddr, const struct
> intel_engine_cs *engine)
>
> vaddr += engine->context_size;
>
> - if (memchr_inv(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE))
> + if (memchr_inv(vaddr, CONTEXT_REDZONE, I915_GTT_PAGE_SIZE))
> dev_err_once(engine->i915->drm.dev,
>"%s context redzone overwritten!\n",
>engine->name);
> --
> 2.25.0.rc0
>
> ___
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Re: [Intel-gfx] [PATCH 5/6] drm/i915/gt: Discard stale context state from across idling
Quoting Mika Kuoppala (2019-12-30 16:30:21)
> Chris Wilson writes:
>
> > Before we idle, on parking, we switch to the kernel context such that we
> > have a scratch context loaded while the GPU idle, protecting any
> > precious user state. Be paranoid and assume that the idle state may have
> > been trashed, and reset the kernel_context image after idling.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Imre Deak
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine_pm.c | 6 ++
> > drivers/gpu/drm/i915/gt/intel_gt_pm.c | 8
> > drivers/gpu/drm/i915/gt/mock_engine.c | 5 +
> > 3 files changed, 11 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > index cd82f0baef49..1b9f73948f22 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > @@ -20,6 +20,7 @@ static int __engine_unpark(struct intel_wakeref *wf)
> > {
> > struct intel_engine_cs *engine =
> > container_of(wf, typeof(*engine), wakeref);
> > + struct intel_context *ce;
> > void *map;
> >
> > ENGINE_TRACE(engine, "\n");
> > @@ -34,6 +35,11 @@ static int __engine_unpark(struct intel_wakeref *wf)
> > if (!IS_ERR_OR_NULL(map))
> > engine->pinned_default_state = map;
> >
> > + /* Discard stale context state from across idling */
> > + ce = engine->kernel_context;
> > + if (ce)
> > + ce->ops->reset(ce);
> > +
>
> Expect the worst, sure.
> Checksum would get us datapoints tho.
Inject yet-another request to the kernel_context on parking to force a
context switch [to itself] and so ensure the image is saved to HW. Wait
for parking, compute the CRC. Then on unpark compute the CRC again...
The design is all based around that we don't trust the HW and try to
avoid caring about what's in the scratch kernel_context, so other than
validating HW... Not a terrible idea, but we can probably cook up
something more targeted if we thought about it.
-Chris
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915/selftests: Flush the context worker
== Series Details == Series: series starting with [1/6] drm/i915/selftests: Flush the context worker URL : https://patchwork.freedesktop.org/series/71497/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7656 -> Patchwork_15947 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_15947 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15947, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15947/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15947: ### IGT changes ### Possible regressions * igt@debugfs_test@read_all_entries: - fi-cml-s: [PASS][1] -> [SKIP][2] +21 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-cml-s/igt@debugfs_test@read_all_entries.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15947/fi-cml-s/igt@debugfs_test@read_all_entries.html * igt@gem_ringfill@basic-default: - fi-icl-u2: [PASS][3] -> [SKIP][4] +63 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-icl-u2/igt@gem_ringf...@basic-default.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15947/fi-icl-u2/igt@gem_ringf...@basic-default.html * igt@gem_ringfill@basic-default-forked: - fi-tgl-y: NOTRUN -> [SKIP][5] +65 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15947/fi-tgl-y/igt@gem_ringf...@basic-default-forked.html * igt@gem_ringfill@basic-default-interruptible: - fi-icl-y: [PASS][6] -> [SKIP][7] +63 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-icl-y/igt@gem_ringf...@basic-default-interruptible.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15947/fi-icl-y/igt@gem_ringf...@basic-default-interruptible.html * igt@gem_sync@basic-all: - fi-icl-guc: [PASS][8] -> [SKIP][9] +63 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-icl-guc/igt@gem_s...@basic-all.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15947/fi-icl-guc/igt@gem_s...@basic-all.html * igt@gem_sync@basic-each: - fi-cml-u2: [PASS][10] -> [SKIP][11] +63 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-cml-u2/igt@gem_s...@basic-each.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15947/fi-cml-u2/igt@gem_s...@basic-each.html * igt@gem_wait@basic-busy-all: - fi-icl-u3: [PASS][12] -> [SKIP][13] +63 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-icl-u3/igt@gem_w...@basic-busy-all.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15947/fi-icl-u3/igt@gem_w...@basic-busy-all.html * igt@i915_module_load@reload: - fi-kbl-8809g: [PASS][14] -> [DMESG-WARN][15] +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-kbl-8809g/igt@i915_module_l...@reload.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15947/fi-kbl-8809g/igt@i915_module_l...@reload.html - fi-cml-u2: [PASS][16] -> [DMESG-WARN][17] +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-cml-u2/igt@i915_module_l...@reload.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15947/fi-cml-u2/igt@i915_module_l...@reload.html - fi-cfl-8700k: [PASS][18] -> [DMESG-WARN][19] +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-cfl-8700k/igt@i915_module_l...@reload.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15947/fi-cfl-8700k/igt@i915_module_l...@reload.html - fi-apl-guc: [PASS][20] -> [DMESG-WARN][21] +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-apl-guc/igt@i915_module_l...@reload.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15947/fi-apl-guc/igt@i915_module_l...@reload.html - fi-bxt-dsi: [PASS][22] -> [DMESG-WARN][23] +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-bxt-dsi/igt@i915_module_l...@reload.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15947/fi-bxt-dsi/igt@i915_module_l...@reload.html - fi-whl-u: [PASS][24] -> [DMESG-WARN][25] +1 similar issue [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-whl-u/igt@i915_module_l...@reload.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15947/fi-whl-u/igt@i915_module_l...@reload.html - fi-skl-6600u: [PASS][26] -> [DMESG-WARN][27] +1 similar issue [26]:
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Flush the context worker
Chris Wilson writes:
> When cleaning up the mock device, remember to flush the context worker
> to free the residual GEM contexts before shutting down the device.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/802
> Signed-off-by: Chris Wilson
> Cc: Matthew Auld
> ---
> drivers/gpu/drm/i915/i915_gem.c | 4 ++--
> drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 ++
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 9ddcf17230e6..a3d701b50a6b 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1172,6 +1172,8 @@ void i915_gem_driver_remove(struct drm_i915_private
> *dev_priv)
>
> void i915_gem_driver_release(struct drm_i915_private *dev_priv)
> {
> + i915_gem_driver_release__contexts(dev_priv);
> +
> intel_gt_driver_release(_priv->gt);
>
> intel_wa_list_free(_priv->gt_wa_list);
> @@ -1179,8 +1181,6 @@ void i915_gem_driver_release(struct drm_i915_private
> *dev_priv)
> intel_uc_cleanup_firmwares(_priv->gt.uc);
> i915_gem_cleanup_userptr(dev_priv);
>
> - i915_gem_driver_release__contexts(dev_priv);
> -
Have I missed some memo on double underscores?
Reviewed-by: Mika Kuoppala
> i915_gem_drain_freed_objects(dev_priv);
>
> WARN_ON(!list_empty(_priv->gem.contexts.list));
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index ac641f5360e1..bddead3fc855 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -58,6 +58,8 @@ static void mock_device_release(struct drm_device *dev)
> mock_device_flush(i915);
> intel_gt_driver_remove(>gt);
>
> + i915_gem_driver_release__contexts(i915);
> +
> i915_gem_drain_workqueue(i915);
> i915_gem_drain_freed_objects(i915);
>
> --
> 2.25.0.rc0
>
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[Intel-gfx] [PATCH 2/6] drm/i915/gt: Clear LRC image inline
When creating the initial LRC image, we also want to clear the MI_NOOPs
and register values. Rather than use a blanket memset beforehand, apply
the clears inline, close the context image and force inhibition of the
uninitialised reminder.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c| 52 +++---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 11 +++---
2 files changed, 35 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 14e7e179855f..f0618e6aabd5 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -488,9 +488,10 @@ lrc_descriptor(struct intel_context *ce, struct
intel_engine_cs *engine)
return desc;
}
-static u32 *set_offsets(u32 *regs,
+static void set_offsets(u32 *regs,
const u8 *data,
- const struct intel_engine_cs *engine)
+ const struct intel_engine_cs *engine,
+ bool clear)
#define NOP(x) (BIT(7) | (x))
#define LRI(count, flags) ((flags) << 6 | (count))
#define POSTED BIT(0)
@@ -506,7 +507,10 @@ static u32 *set_offsets(u32 *regs,
u8 count, flags;
if (*data & BIT(7)) { /* skip */
- regs += *data++ & ~BIT(7);
+ count = *data++ & ~BIT(7);
+ if (clear)
+ memset32(regs, 0, count);
+ regs += count;
continue;
}
@@ -532,12 +536,18 @@ static u32 *set_offsets(u32 *regs,
offset |= v & ~BIT(7);
} while (v & BIT(7));
- *regs = base + (offset << 2);
+ regs[0] = base + (offset << 2);
+ if (clear)
+ regs[1] = MI_NOOP;
regs += 2;
} while (--count);
}
- return regs;
+ if (clear) { /* Close the batch; used mainly by live_lrc_layout() */
+ *regs = MI_BATCH_BUFFER_END;
+ if (INTEL_GEN(engine->i915) >= 10)
+ *regs |= BIT(0);
+ }
}
static const u8 gen8_xcs_offsets[] = {
@@ -1443,7 +1453,7 @@ static bool can_merge_rq(const struct i915_request *prev,
static void virtual_update_register_offsets(u32 *regs,
struct intel_engine_cs *engine)
{
- set_offsets(regs, reg_offsets(engine), engine);
+ set_offsets(regs, reg_offsets(engine), engine, false);
}
static bool virtual_matches(const struct virtual_engine *ve,
@@ -3957,15 +3967,19 @@ static u32 intel_lr_indirect_ctx_offset(const struct
intel_engine_cs *engine)
static void init_common_reg_state(u32 * const regs,
const struct intel_engine_cs *engine,
- const struct intel_ring *ring)
+ const struct intel_ring *ring,
+ bool inhibit)
{
- regs[CTX_CONTEXT_CONTROL] =
- _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
- _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH);
+ u32 ctl;
+
+ ctl = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH);
+ ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
+ if (inhibit)
+ ctl |= CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT;
if (INTEL_GEN(engine->i915) < 11)
- regs[CTX_CONTEXT_CONTROL] |=
- _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
- CTX_CTRL_RS_CTX_ENABLE);
+ ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
+ CTX_CTRL_RS_CTX_ENABLE);
+ regs[CTX_CONTEXT_CONTROL] = ctl;
regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
regs[CTX_BB_STATE] = RING_BB_PPGTT;
@@ -4024,7 +4038,7 @@ static void execlists_init_reg_state(u32 *regs,
const struct intel_context *ce,
const struct intel_engine_cs *engine,
const struct intel_ring *ring,
-bool close)
+bool inhibit)
{
/*
* A context is actually a big batch buffer with several
@@ -4036,15 +4050,9 @@ static void execlists_init_reg_state(u32 *regs,
*
* Must keep consistent with virtual_update_register_offsets().
*/
- u32 *bbe = set_offsets(regs, reg_offsets(engine), engine);
-
- if (close) { /* Close the batch; used mainly by live_lrc_layout() */
- *bbe = MI_BATCH_BUFFER_END;
- if (INTEL_GEN(engine->i915) >= 10)
- *bbe |= BIT(0);
-
[Intel-gfx] [PATCH 3/6] drm/i915/gt: Leave RING_BB_STATE to default value
Do not reset RING_BB_STATE, leaving it to the default state value. This prevents bdw/bsw from getting confused when executing batches from the GGTT. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_lrc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index f0618e6aabd5..2bf6dc6d528d 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3982,7 +3982,6 @@ static void init_common_reg_state(u32 * const regs, regs[CTX_CONTEXT_CONTROL] = ctl; regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID; - regs[CTX_BB_STATE] = RING_BB_PPGTT; } static void init_wa_bb_reg_state(u32 * const regs, -- 2.25.0.rc0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/6] drm/i915/selftests: Flush the context worker
When cleaning up the mock device, remember to flush the context worker
to free the residual GEM contexts before shutting down the device.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/802
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem.c | 4 ++--
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 ++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9ddcf17230e6..a3d701b50a6b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1172,6 +1172,8 @@ void i915_gem_driver_remove(struct drm_i915_private
*dev_priv)
void i915_gem_driver_release(struct drm_i915_private *dev_priv)
{
+ i915_gem_driver_release__contexts(dev_priv);
+
intel_gt_driver_release(_priv->gt);
intel_wa_list_free(_priv->gt_wa_list);
@@ -1179,8 +1181,6 @@ void i915_gem_driver_release(struct drm_i915_private
*dev_priv)
intel_uc_cleanup_firmwares(_priv->gt.uc);
i915_gem_cleanup_userptr(dev_priv);
- i915_gem_driver_release__contexts(dev_priv);
-
i915_gem_drain_freed_objects(dev_priv);
WARN_ON(!list_empty(_priv->gem.contexts.list));
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 2b01094e4318..3b8986983afc 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -58,6 +58,8 @@ static void mock_device_release(struct drm_device *dev)
mock_device_flush(i915);
intel_gt_driver_remove(>gt);
+ i915_gem_driver_release__contexts(i915);
+
i915_gem_drain_workqueue(i915);
i915_gem_drain_freed_objects(i915);
--
2.25.0.rc0
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[Intel-gfx] [PATCH 6/6] drm/i915/gt: Always poison the kernel_context image before unparking
Keep scrubbing the kernel_context image with poison before we reset it
in order to demonstrate that we will be resilient in the case where it
is accidentally overwritten on idle.
Suggested-by: Imre Deak
Signed-off-by: Chris Wilson
Cc: Imre Deak
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 2 ++
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 18 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
3 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 9527a659546c..ca1420fb8b53 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -17,6 +17,8 @@
#include "intel_engine_types.h"
#include "intel_sseu.h"
+#define CONTEXT_REDZONE POISON_INUSE
+
struct i915_gem_context;
struct i915_vma;
struct intel_context;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 1b9f73948f22..ea90ab3e396e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -37,8 +37,24 @@ static int __engine_unpark(struct intel_wakeref *wf)
/* Discard stale context state from across idling */
ce = engine->kernel_context;
- if (ce)
+ if (ce) {
+ GEM_BUG_ON(test_bit(CONTEXT_VALID_BIT, >flags));
+
+ /* First poison the image to verify we never fully trust it */
+ if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) && ce->state) {
+ struct drm_i915_gem_object *obj = ce->state->obj;
+ int type = i915_coherent_map_type(engine->i915);
+
+ map = i915_gem_object_pin_map(obj, type);
+ if (!IS_ERR(map)) {
+ memset(map, CONTEXT_REDZONE, obj->base.size);
+ i915_gem_object_flush_map(obj);
+ i915_gem_object_unpin_map(obj);
+ }
+ }
+
ce->ops->reset(ce);
+ }
if (engine->unpark)
engine->unpark(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6d26d84812b6..f81e70cfd194 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2409,7 +2409,7 @@ set_redzone(void *vaddr, const struct intel_engine_cs
*engine)
vaddr += engine->context_size;
- memset(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE);
+ memset(vaddr, CONTEXT_REDZONE, I915_GTT_PAGE_SIZE);
}
static void
@@ -2420,7 +2420,7 @@ check_redzone(const void *vaddr, const struct
intel_engine_cs *engine)
vaddr += engine->context_size;
- if (memchr_inv(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE))
+ if (memchr_inv(vaddr, CONTEXT_REDZONE, I915_GTT_PAGE_SIZE))
dev_err_once(engine->i915->drm.dev,
"%s context redzone overwritten!\n",
engine->name);
--
2.25.0.rc0
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[Intel-gfx] [PATCH 5/6] drm/i915/gt: Discard stale context state from across idling
Before we idle, on parking, we switch to the kernel context such that we
have a scratch context loaded while the GPU idle, protecting any
precious user state. Be paranoid and assume that the idle state may have
been trashed, and reset the kernel_context image after idling.
Signed-off-by: Chris Wilson
Cc: Imre Deak
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 6 ++
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 8
drivers/gpu/drm/i915/gt/mock_engine.c | 5 +
3 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index cd82f0baef49..1b9f73948f22 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -20,6 +20,7 @@ static int __engine_unpark(struct intel_wakeref *wf)
{
struct intel_engine_cs *engine =
container_of(wf, typeof(*engine), wakeref);
+ struct intel_context *ce;
void *map;
ENGINE_TRACE(engine, "\n");
@@ -34,6 +35,11 @@ static int __engine_unpark(struct intel_wakeref *wf)
if (!IS_ERR_OR_NULL(map))
engine->pinned_default_state = map;
+ /* Discard stale context state from across idling */
+ ce = engine->kernel_context;
+ if (ce)
+ ce->ops->reset(ce);
+
if (engine->unpark)
engine->unpark(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 9b220c930ebc..d1c2f034296a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -213,16 +213,8 @@ int intel_gt_resume(struct intel_gt *gt)
intel_llc_enable(>llc);
for_each_engine(engine, gt, id) {
- struct intel_context *ce;
-
intel_engine_pm_get(engine);
- ce = engine->kernel_context;
- if (ce) {
- GEM_BUG_ON(!intel_context_is_pinned(ce));
- ce->ops->reset(ce);
- }
-
engine->serial++; /* kernel context lost */
err = engine->resume(engine);
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c
b/drivers/gpu/drm/i915/gt/mock_engine.c
index 4e1eafa94be9..d0e68ce9aa51 100644
--- a/drivers/gpu/drm/i915/gt/mock_engine.c
+++ b/drivers/gpu/drm/i915/gt/mock_engine.c
@@ -152,6 +152,10 @@ static int mock_context_pin(struct intel_context *ce)
return intel_context_active_acquire(ce);
}
+static void mock_context_reset(struct intel_context *ce)
+{
+}
+
static const struct intel_context_ops mock_context_ops = {
.alloc = mock_context_alloc,
@@ -161,6 +165,7 @@ static const struct intel_context_ops mock_context_ops = {
.enter = intel_context_enter_engine,
.exit = intel_context_exit_engine,
+ .reset = mock_context_reset,
.destroy = mock_context_destroy,
};
--
2.25.0.rc0
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[Intel-gfx] [PATCH 4/6] drm/i915/gt: Ignore stale context state upon resume
We leave the kernel_context on the HW as we suspend (and while idle).
There is no guarantee that is complete in memory, so we try to inhibit
restoration from the kernel_context. Reinforce the inhibition by
scrubbing the context.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 11 ++-
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 2bf6dc6d528d..6d26d84812b6 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2504,6 +2504,9 @@ static int execlists_context_alloc(struct intel_context
*ce)
static void execlists_context_reset(struct intel_context *ce)
{
+ CE_TRACE(ce, "reset\n");
+ GEM_BUG_ON(!intel_context_is_pinned(ce));
+
/*
* Because we emit WA_TAIL_DWORDS there may be a disparity
* between our bookkeeping in ce->ring->head and ce->ring->tail and
@@ -2520,8 +2523,14 @@ static void execlists_context_reset(struct intel_context
*ce)
* So to avoid that we reset the context images upon resume. For
* simplicity, we just zero everything out.
*/
- intel_ring_reset(ce->ring, 0);
+ intel_ring_reset(ce->ring, ce->ring->emit);
+
+ /* Scrub away the garbage */
+ execlists_init_reg_state(ce->lrc_reg_state,
+ce, ce->engine, ce->ring, true);
__execlists_update_reg_state(ce, ce->engine);
+
+ ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
}
static const struct intel_context_ops execlists_context_ops = {
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 066c4eddf5d0..843111b7b015 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1347,7 +1347,7 @@ static int ring_context_pin(struct intel_context *ce)
static void ring_context_reset(struct intel_context *ce)
{
- intel_ring_reset(ce->ring, 0);
+ intel_ring_reset(ce->ring, ce->ring->emit);
}
static const struct intel_context_ops ring_context_ops = {
--
2.25.0.rc0
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Re: [Intel-gfx] [PATCH 5/7] drm/i915/gt: Ignore stale context state upon resume
On Sun, 29 Dec 2019 at 18:32, Chris Wilson wrote:
>
> We leave the kernel_context on the HW as we suspend (and while idle).
> There is no guarantee that is complete in memory, so we try to inhibit
> restoration from the kernel_context. Reinforce the inhibition by
> scrubbing the context.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 17 +++--
> drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
> 2 files changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 14e7e179855f..b1508dbd1063 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2494,6 +2494,11 @@ static int execlists_context_alloc(struct
> intel_context *ce)
>
> static void execlists_context_reset(struct intel_context *ce)
> {
> + u32 *regs;
> +
> + CE_TRACE(ce, "reset\n");
> + GEM_BUG_ON(!intel_context_is_pinned(ce));
> +
> /*
> * Because we emit WA_TAIL_DWORDS there may be a disparity
> * between our bookkeeping in ce->ring->head and ce->ring->tail and
> @@ -2510,8 +2515,17 @@ static void execlists_context_reset(struct
> intel_context *ce)
> * So to avoid that we reset the context images upon resume. For
> * simplicity, we just zero everything out.
> */
> - intel_ring_reset(ce->ring, 0);
> + intel_ring_reset(ce->ring, ce->ring->emit);
> +
> + regs = memset(ce->lrc_reg_state, 0, PAGE_SIZE);
> + execlists_init_reg_state(regs, ce, ce->engine, ce->ring, true);
> __execlists_update_reg_state(ce, ce->engine);
> +
> + /* Avoid trying to reload the garbage */
> + regs[CTX_CONTEXT_CONTROL] |=
> + _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
> +
> + ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
> }
>
> static const struct intel_context_ops execlists_context_ops = {
> @@ -3968,7 +3982,6 @@ static void init_common_reg_state(u32 * const regs,
> CTX_CTRL_RS_CTX_ENABLE);
>
> regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
> - regs[CTX_BB_STATE] = RING_BB_PPGTT;
Zero clue what that does...
Otherwise,
Reviewed-by: Matthew Auld
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Re: [Intel-gfx] [PATCH 3/6] drm/i915/gt: Leave RING_BB_STATE to default value
Quoting Chris Wilson (2019-12-30 16:01:09) > Do not reset RING_BB_STATE, leaving it to the default state value. This > prevents bdw/bsw from getting confused when executing batches from the > GGTT. > > Signed-off-by: Chris Wilson Acked-by: Matthew Auld -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/7] drm/i915/gt: Ignore stale context state upon resume
Quoting Matthew Auld (2019-12-30 16:06:47)
> On Sun, 29 Dec 2019 at 18:32, Chris Wilson wrote:
> > static const struct intel_context_ops execlists_context_ops = {
> > @@ -3968,7 +3982,6 @@ static void init_common_reg_state(u32 * const regs,
> > CTX_CTRL_RS_CTX_ENABLE);
> >
> > regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
> > - regs[CTX_BB_STATE] = RING_BB_PPGTT;
>
> Zero clue what that does...
It's supposed to be a readonly bit that shows the state of the current
batch buffer, and is supposed to be only set by MI_BB_START. Broadwell
and Braswell disagree with the bspec. C'est la vie.
I broke it out into a separate patch for clarity.
-Chris
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Re: [Intel-gfx] [PATCH 6/7] drm/i915/gt: Discard stale context state from across idling
On Sun, 29 Dec 2019 at 18:32, Chris Wilson wrote: > > Before we idle, on parking, we switch to the kernel context such that we > have a scratch context loaded while the GPU idle, protecting any > precious user state. Be paranoid and assume that the idle state may have > been trashed, and reset the kernel_context image after idling. > > Signed-off-by: Chris Wilson > Cc: Imre Deak Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 6/6] drm/i915/gt: Always poison the kernel_context image before unparking
Quoting Mika Kuoppala (2019-12-30 16:23:20)
> Chris Wilson writes:
>
> > Keep scrubbing the kernel_context image with poison before we reset it
> > in order to demonstrate that we will be resilient in the case where it
> > is accidentally overwritten on idle.
> >
> > Suggested-by: Imre Deak
> > Signed-off-by: Chris Wilson
> > Cc: Imre Deak
> > ---
> > drivers/gpu/drm/i915/gt/intel_context_types.h | 2 ++
> > drivers/gpu/drm/i915/gt/intel_engine_pm.c | 18 +-
> > drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
> > 3 files changed, 21 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > index 9527a659546c..ca1420fb8b53 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > @@ -17,6 +17,8 @@
> > #include "intel_engine_types.h"
> > #include "intel_sseu.h"
> >
> > +#define CONTEXT_REDZONE POISON_INUSE
> > +
> > struct i915_gem_context;
> > struct i915_vma;
> > struct intel_context;
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > index 1b9f73948f22..ea90ab3e396e 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > @@ -37,8 +37,24 @@ static int __engine_unpark(struct intel_wakeref *wf)
> >
> > /* Discard stale context state from across idling */
> > ce = engine->kernel_context;
> > - if (ce)
> > + if (ce) {
> > + GEM_BUG_ON(test_bit(CONTEXT_VALID_BIT, >flags));
> > +
> > + /* First poison the image to verify we never fully trust it */
> > + if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) && ce->state) {
> > + struct drm_i915_gem_object *obj = ce->state->obj;
> > + int type = i915_coherent_map_type(engine->i915);
> > +
> > + map = i915_gem_object_pin_map(obj, type);
> > + if (!IS_ERR(map)) {
> > + memset(map, CONTEXT_REDZONE, obj->base.size);
>
> Just pondering if the dword granularity would suffice.
Pure debug, so convenience of memchr_inv() rules.
-Chris
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[Intel-gfx] [PATCH v3 6/9] drm/i915/dp: Add debugfs entry for DP phy compliance.
These debugfs entry will help testapp to understand the test request
during dp phy compliance mode.
Acked-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0ac98e39eb75..a903ed0632cb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3177,6 +3177,16 @@ static int i915_displayport_test_data_show(struct
seq_file *m, void *data)
intel_dp->compliance.test_data.vdisplay);
seq_printf(m, "bpc: %u\n",
intel_dp->compliance.test_data.bpc);
+ } else if (intel_dp->compliance.test_type ==
+ DP_TEST_LINK_PHY_TEST_PATTERN) {
+ seq_printf(m, "pattern: %d\n",
+
intel_dp->compliance.test_data.phytest.phy_pattern);
+ seq_printf(m, "Number of lanes: %d\n",
+
intel_dp->compliance.test_data.phytest.num_lanes);
+ seq_printf(m, "Link Rate: %d\n",
+
intel_dp->compliance.test_data.phytest.link_rate);
+ seq_printf(m, "level: %02x\n",
+ intel_dp->train_set[0]);
}
} else
seq_puts(m, "0");
@@ -3209,7 +3219,7 @@ static int i915_displayport_test_type_show(struct
seq_file *m, void *data)
if (encoder && connector->status == connector_status_connected)
{
intel_dp = enc_to_intel_dp(>base);
- seq_printf(m, "%02lx", intel_dp->compliance.test_type);
+ seq_printf(m, "%02lx\n",
intel_dp->compliance.test_type);
} else
seq_puts(m, "0");
}
--
2.24.0
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[Intel-gfx] [PATCH v3 4/9] drm/i915/dp: Preparation for DP phy compliance auto test
During DP phy compliance auto test mode, sink will request
combination of different test pattern with differnt level of
vswing, pre-emphasis. Function added to prepare for it.
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 24 +++
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 630a94892b7b..32f0740e4569 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1208,6 +1208,7 @@ struct intel_dp_compliance_data {
u8 video_pattern;
u16 hdisplay, vdisplay;
u8 bpc;
+ struct drm_dp_phy_test_params phytest;
};
struct intel_dp_compliance {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2a27ee106089..fa67b8f88e65 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4986,9 +4986,33 @@ static u8 intel_dp_autotest_edid(struct intel_dp
*intel_dp)
return test_result;
}
+static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
+{
+ struct drm_dp_phy_test_params *data =
+ _dp->compliance.test_data.phytest;
+
+ if (drm_dp_get_phy_test_pattern(_dp->aux, data)) {
+ DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
+ return DP_TEST_NAK;
+ }
+
+ /*
+* link_mst is set to false to avoid executing mst related code
+* during compliance testing.
+*/
+ intel_dp->link_mst = false;
+
+ return DP_TEST_ACK;
+}
+
static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
{
u8 test_result = DP_TEST_NAK;
+
+ test_result = intel_dp_prepare_phytest(intel_dp);
+ if (test_result != DP_TEST_ACK)
+ DRM_ERROR("Phy test preparation failed\n");
+
return test_result;
}
--
2.24.0
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[Intel-gfx] [PATCH v3 2/9] drm/dp: get/set phy compliance pattern
During phy compliance auto test mode source need to read
requested test pattern from sink through DPCD. After processing
the request source need to set the pattern. So set/get method
added in drm layer as it is DP protocol.
v2: As per review feedback from Manasi on RFC version,
- added dp revision as function argument in set_phy_pattern api.
- used int for link_rate and u8 for lane_count to align with existing code.
v3: As per review feedback from Harry,
- used sizeof() instead of magic number.
- corrected kernel-doc for drm_dp_phy_test_params structure.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/drm_dp_helper.c | 94 +
include/drm/drm_dp_helper.h | 31 +++
2 files changed, 125 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 2c7870aef469..8a0786dd262d 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1371,3 +1371,97 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_S
return num_bpc;
}
EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+/**
+ * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data)
+{
+ int err;
+ u8 rate, lanes;
+
+ err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, );
+ if (err < 0)
+ return err;
+ data->link_rate = drm_dp_bw_code_to_link_rate(rate);
+
+ err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, );
+ if (err < 0)
+ return err;
+ data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
+
+ if (lanes & DP_ENHANCED_FRAME_CAP)
+ data->enhanced_frame_cap = true;
+
+ err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, >phy_pattern);
+ if (err < 0)
+ return err;
+
+ switch (data->phy_pattern) {
+ case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
+ err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
+ >custom80, sizeof(data->custom80));
+ if (err < 0)
+ return err;
+
+ break;
+ case DP_PHY_TEST_PATTERN_CP2520:
+ err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
+ >hbr2_reset,
+ sizeof(data->hbr2_reset));
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
+
+/**
+ * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data, u8 dp_rev)
+{
+ int err, i;
+ u8 link_config[2];
+ u8 test_pattern;
+
+ link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
+ link_config[1] = data->num_lanes;
+ if (data->enhanced_frame_cap)
+ link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+ err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
+ if (err < 0)
+ return err;
+
+ test_pattern = data->phy_pattern;
+ if (dp_rev < 0x12) {
+ test_pattern = (test_pattern << 2) &
+ DP_LINK_QUAL_PATTERN_11_MASK;
+ err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
+test_pattern);
+ if (err < 0)
+ return err;
+ } else {
+ for (i = 0; i < data->num_lanes; i++) {
+ err = drm_dp_dpcd_writeb(aux,
+DP_LINK_QUAL_LANE0_SET + i,
+test_pattern);
+ if (err < 0)
+ return err;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index d6e560870fb1..3d0e9e0d55cf 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -700,6 +700,15 @@
# define DP_TEST_COUNT_MASK0xf
#define DP_PHY_TEST_PATTERN 0x248
+# define DP_PHY_TEST_PATTERN_SEL_MASK 0x7
+# define DP_PHY_TEST_PATTERN_NONE 0x0
+# define DP_PHY_TEST_PATTERN_D10_2 0x1
+# define DP_PHY_TEST_PATTERN_ERROR_COUNT0x2
+# define DP_PHY_TEST_PATTERN_PRBS7 0x3
+# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
[Intel-gfx] [PATCH v3 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
vswing/pre-emphasis adjustment calculation is needed in processing
of auto phy compliance request other than link training, so moved
the same function in intel_dp.c.
No functional change.
v1: initial patch.
v2:
- used "intel_dp" prefix in function name. (Jani)
- used array notation instead pointer for link_status. (Ville)
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 34 ++
drivers/gpu/drm/i915/display/intel_dp.h | 4 +++
.../drm/i915/display/intel_dp_link_training.c | 36 ++-
3 files changed, 40 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 991f343579ef..2a27ee106089 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4110,6 +4110,40 @@ ivb_cpu_edp_signal_levels(u8 train_set)
}
}
+void
+intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+ const u8 link_status[DP_LINK_STATUS_SIZE])
+{
+ u8 v = 0;
+ u8 p = 0;
+ int lane;
+ u8 voltage_max;
+ u8 preemph_max;
+
+ for (lane = 0; lane < intel_dp->lane_count; lane++) {
+ u8 this_v = drm_dp_get_adjust_request_voltage(link_status,
+ lane);
+ u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status,
+ lane);
+
+ if (this_v > v)
+ v = this_v;
+ if (this_p > p)
+ p = this_p;
+ }
+
+ voltage_max = intel_dp_voltage_max(intel_dp);
+ if (v >= voltage_max)
+ v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
+
+ preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
+ if (p >= preemph_max)
+ p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+ for (lane = 0; lane < 4; lane++)
+ intel_dp->train_set[lane] = v | p;
+}
+
void
intel_dp_set_signal_levels(struct intel_dp *intel_dp)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 3da166054788..83eadc87af26 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -9,6 +9,7 @@
#include
#include
+#include
#include "i915_reg.h"
@@ -91,6 +92,9 @@ void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
u8 dp_train_pat);
void
+intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+ const u8 link_status[DP_LINK_STATUS_SIZE]);
+void
intel_dp_set_signal_levels(struct intel_dp *intel_dp);
void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
u8
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 2a1130dd1ad0..e8ff9e279800 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8
link_status[DP_LINK_STATUS_SIZE])
link_status[3], link_status[4], link_status[5]);
}
-static void
-intel_get_adjust_train(struct intel_dp *intel_dp,
- const u8 link_status[DP_LINK_STATUS_SIZE])
-{
- u8 v = 0;
- u8 p = 0;
- int lane;
- u8 voltage_max;
- u8 preemph_max;
-
- for (lane = 0; lane < intel_dp->lane_count; lane++) {
- u8 this_v = drm_dp_get_adjust_request_voltage(link_status,
lane);
- u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status,
lane);
-
- if (this_v > v)
- v = this_v;
- if (this_p > p)
- p = this_p;
- }
-
- voltage_max = intel_dp_voltage_max(intel_dp);
- if (v >= voltage_max)
- v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
-
- preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
- if (p >= preemph_max)
- p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
-
- for (lane = 0; lane < 4; lane++)
- intel_dp->train_set[lane] = v | p;
-}
-
static bool
intel_dp_set_link_train(struct intel_dp *intel_dp,
u8 dp_train_pat)
@@ -215,7 +183,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp
*intel_dp)
voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
/* Update training set as requested by target */
- intel_get_adjust_train(intel_dp, link_status);
+ intel_dp_get_adjust_train(intel_dp, link_status);
if (!intel_dp_update_link_train(intel_dp)) {
DRM_ERROR("failed to update link training\n");
return false;
@@ -325,7 +293,7 @@
[Intel-gfx] [PATCH v3 1/9] drm/amd/display: Align macro name as per DP spec
[Why]: Aligh with DP spec wanted to follow same naming convention. [How]: Changed the macro name of the dpcd address used for getting requested test-pattern. Cc: Harry Wentland Cc: Alex Deucher Reviewed-by: Harry Wentland Signed-off-by: Animesh Manna --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +- include/drm/drm_dp_helper.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 42aa889fd0f5..1a6109be2fce 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2491,7 +2491,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link) /* get phy test pattern and pattern parameters from DP receiver */ core_link_read_dpcd( link, - DP_TEST_PHY_PATTERN, + DP_PHY_TEST_PATTERN, _test_pattern.raw, sizeof(dpcd_test_pattern)); core_link_read_dpcd( diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 8f8f3632e697..d6e560870fb1 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -699,7 +699,7 @@ # define DP_TEST_CRC_SUPPORTED (1 << 5) # define DP_TEST_COUNT_MASK0xf -#define DP_TEST_PHY_PATTERN 0x248 +#define DP_PHY_TEST_PATTERN 0x248 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_00x250 #defineDP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 #defineDP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252 -- 2.24.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 8/9] drm/i915/dp: Update the pattern as per request
As per request from DP phy compliance test few special
test pattern need to set by source. Added function
to set pattern in DP_COMP_CTL register. It will be
called along with other test parameters like vswing,
pre-emphasis programming in atomic_commit_tail path.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 55 +
1 file changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index cbefda9b6204..7c3f65e5d88b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5005,6 +5005,61 @@ static u8 intel_dp_prepare_phytest(struct intel_dp
*intel_dp)
return DP_TEST_ACK;
}
+static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_dp_phy_test_params *data =
+ _dp->compliance.test_data.phytest;
+ u32 temp;
+
+ switch (data->phy_pattern) {
+ case DP_PHY_TEST_PATTERN_NONE:
+ DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
+ I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), 0x0);
+ break;
+ case DP_PHY_TEST_PATTERN_D10_2:
+ DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
+ I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+ DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
+ break;
+ case DP_PHY_TEST_PATTERN_ERROR_COUNT:
+ DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
+ I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+ DDI_DP_COMP_CTL_ENABLE |
+ DDI_DP_COMP_CTL_SCRAMBLED_0);
+ break;
+ case DP_PHY_TEST_PATTERN_PRBS7:
+ DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
+ I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+ DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
+ break;
+ case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
+ DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern\n");
+ temp = ((data->custom80[0] << 24) | (data->custom80[1] << 16) |
+ (data->custom80[2] << 8) | (data->custom80[3]));
+ I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 0), temp);
+ temp = ((data->custom80[4] << 24) | (data->custom80[5] << 16) |
+ (data->custom80[6] << 8) | (data->custom80[7]));
+ I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 1), temp);
+ temp = ((data->custom80[8] << 8) | data->custom80[9]);
+ I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 2), temp);
+ I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+ DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80);
+ break;
+ case DP_PHY_TEST_PATTERN_CP2520:
+ DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
+ temp = ((data->hbr2_reset[1] << 8) | data->hbr2_reset[0]);
+ I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+ DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
+ temp);
+ break;
+ default:
+ WARN(1, "Invalid Phy Test PAttern\n");
+ }
+}
+
static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
{
u8 test_result = DP_TEST_NAK;
--
2.24.0
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[Intel-gfx] [PATCH v3 9/9] drm/i915/dp: [FIXME] Program vswing, pre-emphasis, test-pattern
This patch process phy compliance request by programming requested
vswing, pre-emphasis and test pattern.
Note: FIXME tag added as design discusion is ongoing in previous patch
series. Some temporary fix added and the patch is under-development, not for
review.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display.c | 24 ++-
drivers/gpu/drm/i915/display/intel_dp.c | 74
drivers/gpu/drm/i915/display/intel_dp.h | 2 +
drivers/gpu/drm/i915/i915_drv.h | 2 +
4 files changed, 101 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index da5266e76738..c00be1eb67d6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14480,6 +14480,9 @@ static int intel_atomic_check(struct drm_device *dev,
int ret, i;
bool any_ms = false;
+ if (dev_priv->dp_phy_comp)
+ return 0;
+
/* Catch I915_MODE_FLAG_INHERITED */
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
@@ -15207,10 +15210,23 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
struct intel_crtc *crtc;
+ const struct drm_connector_state *conn_state;
+ struct drm_connector *conn;
u64 put_domains[I915_MAX_PIPES] = {};
intel_wakeref_t wakeref = 0;
int i;
+ if(dev_priv->dp_phy_comp) {
+ for_each_new_connector_in_state(>base, conn, conn_state,
i) {
+ struct intel_encoder *encoder =
+ to_intel_encoder(conn_state->best_encoder);
+ struct intel_dp *intel_dp =
enc_to_intel_dp(>base);
+
+ intel_dp_process_phy_request(intel_dp);
+ }
+ goto dp_phy_comp1;
+ }
+
intel_atomic_commit_fence_wait(state);
drm_atomic_helper_wait_for_dependencies(>base);
@@ -15345,6 +15361,7 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
if (state->modeset && intel_can_enable_sagv(state))
intel_enable_sagv(dev_priv);
+dp_phy_comp1:
drm_atomic_helper_commit_hw_done(>base);
if (state->modeset) {
@@ -15436,6 +15453,7 @@ static int intel_atomic_commit(struct drm_device *dev,
state->wakeref = intel_runtime_pm_get(_priv->runtime_pm);
drm_atomic_state_get(>base);
+ if (!dev_priv->dp_phy_comp) {
i915_sw_fence_init(>commit_ready,
intel_atomic_commit_ready);
@@ -15474,11 +15492,13 @@ static int intel_atomic_commit(struct drm_device *dev,
intel_runtime_pm_put(_priv->runtime_pm, state->wakeref);
return ret;
}
+ }
ret = drm_atomic_helper_setup_commit(>base, nonblock);
if (!ret)
ret = drm_atomic_helper_swap_state(>base, true);
+ if (!dev_priv->dp_phy_comp) {
if (ret) {
i915_sw_fence_commit(>commit_ready);
@@ -15489,6 +15509,7 @@ static int intel_atomic_commit(struct drm_device *dev,
dev_priv->wm.distrust_bios_wm = false;
intel_shared_dpll_swap_state(state);
intel_atomic_track_fbs(state);
+ }
if (state->global_state_changed) {
assert_global_state_locked(dev_priv);
@@ -15505,8 +15526,9 @@ static int intel_atomic_commit(struct drm_device *dev,
drm_atomic_state_get(>base);
INIT_WORK(>base.commit_work, intel_atomic_commit_work);
-
+ if (!dev_priv->dp_phy_comp) {
i915_sw_fence_commit(>commit_ready);
+ }
if (nonblock && state->modeset) {
queue_work(dev_priv->modeset_wq, >base.commit_work);
} else if (nonblock) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7c3f65e5d88b..c3454053a212 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5060,9 +5060,82 @@ static inline void intel_dp_phy_pattern_update(struct
intel_dp *intel_dp)
}
}
+static void
+intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum port port = intel_dig_port->base.port;
+ u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
+
+ ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
+ dp_tp_ctl_value = I915_READ(TGL_DP_TP_CTL(port));
+ trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
+
+
Re: [Intel-gfx] [PATCH 5/6] drm/i915/gt: Discard stale context state from across idling
Quoting Chris Wilson (2019-12-30 16:01:11) > Before we idle, on parking, we switch to the kernel context such that we > have a scratch context loaded while the GPU idle, protecting any > precious user state. Be paranoid and assume that the idle state may have > been trashed, and reset the kernel_context image after idling. > > Signed-off-by: Chris Wilson > Cc: Imre Deak Reviewed-by: Matthew Auld -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915/selftests: Flush the context worker
Quoting Patchwork (2019-12-30 16:53:38) > == Series Details == > > Series: series starting with [1/6] drm/i915/selftests: Flush the context > worker > URL : https://patchwork.freedesktop.org/series/71497/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_7656 -> Patchwork_15947 > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_15947 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_15947, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15947/index.html > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_15947: > > ### IGT changes ### > > Possible regressions > > * igt@debugfs_test@read_all_entries: > - fi-cml-s: [PASS][1] -> [SKIP][2] +21 similar issues >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7656/fi-cml-s/igt@debugfs_test@read_all_entries.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15947/fi-cml-s/igt@debugfs_test@read_all_entries.html IPEHR: 0x5a5a5a5a Didn't clear enough... -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add support for non-power-of-2 FB plane alignment
On Mon, Dec 30, 2019 at 10:48:31AM +, Chris Wilson wrote:
> Quoting Imre Deak (2019-12-27 23:51:45)
> > At least one framebuffer plane on TGL - the UV plane of YUV semiplanar
> > FBs - requires a non-power-of-2 alignment, so add support for this. This
> > new alignment restriction applies only to an offset within an FB, so the
> > GEM buffer itself containing the FB must still be power-of-2 aligned.
>
> It's worth talking about virtual memory alignment (in the GGTT) here and
> not the physical alignment of the backing store. The buffer itself plays
> no part here.
Yes, this new restriction is about the GGTT mapping and display
specific. In fact other engines have other restrictions when
reading/writing the same YUV surfaces - for instance via a PPGTT map.
And yes, the page physical addresses can be anything.
Will improve the commit log.
> > Add a check for this (in practice plane 0, since the plane 0 offset must
> > be 0).
> >
> > Cc: Chris Wilson
> > Cc: Ville Syrjälä
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 22 +---
> > 1 file changed, 14 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 624ba9be7293..d8970198c77e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -2194,6 +2194,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
> > return ERR_PTR(-EINVAL);
> >
> > alignment = intel_surf_alignment(fb, 0);
> > + WARN_ON(!is_power_of_2(alignment));
>
> Handle the error, if you are going to the trouble to warn, add the
> return as well.
Ok.
> >
> > /* Note that the w/a also requires 64 PTE of padding following the
> > * bo. We currently fill all unused PTE with the shadow page and so
> > @@ -2432,9 +2433,6 @@ static u32 intel_compute_aligned_offset(struct
> > drm_i915_private *dev_priv,
> > unsigned int cpp = fb->format->cpp[color_plane];
> > u32 offset, offset_aligned;
> >
> > - if (alignment)
> > - alignment--;
> > -
> > if (!is_surface_linear(fb, color_plane)) {
> > unsigned int tile_size, tile_width, tile_height;
> > unsigned int tile_rows, tiles, pitch_tiles;
> > @@ -2456,17 +2454,24 @@ static u32 intel_compute_aligned_offset(struct
> > drm_i915_private *dev_priv,
> > *x %= tile_width;
> >
> > offset = (tile_rows * pitch_tiles + tiles) * tile_size;
> > - offset_aligned = offset & ~alignment;
> > +
> > + offset_aligned = offset;
> > + if (alignment)
> > + offset_aligned = rounddown(offset_aligned,
> > alignment);
> >
> > intel_adjust_tile_offset(x, y, tile_width, tile_height,
> > tile_size, pitch_tiles,
> > offset, offset_aligned);
> > } else {
> > offset = *y * pitch + *x * cpp;
> > - offset_aligned = offset & ~alignment;
> > -
> > - *y = (offset & alignment) / pitch;
> > - *x = ((offset & alignment) - *y * pitch) / cpp;
> > + offset_aligned = offset;
> > + if (alignment) {
> > + offset_aligned = rounddown(offset_aligned,
> > alignment);
> > + *y = (offset % alignment) / pitch;
> > + *x = ((offset % alignment) - *y * pitch) / cpp;
> > + } else {
> > + *y = *x = 0;
> > + }
> > }
> >
> > return offset_aligned;
> > @@ -3738,6 +3743,7 @@ static int skl_check_main_surface(struct
> > intel_plane_state *plane_state)
> > intel_add_fb_offsets(, , plane_state, 0);
> > offset = intel_plane_compute_aligned_offset(, , plane_state, 0);
> > alignment = intel_surf_alignment(fb, 0);
> > + WARN_ON(!is_power_of_2(alignment));
>
> The other two are expected to handle !is_pot...
Not sure what the alignment of the address we write to the main surface
address register should be, the spec doesn't say anything about that. I
assume now that not wrapping around the right edge of the detiler fence
we add is enough (which is also checked in intel_fill_fb_info()).
> I would strongly suggest handling the WARNs, or else you may as well bug
> out for the programming error.
Ok, will change those.
> Reviewed-by: Chris Wilson
> -Chris
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Re: [Intel-gfx] [PATCH 2/3] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned
On Mon, Dec 30, 2019 at 10:53:21AM +, Chris Wilson wrote:
> Quoting Imre Deak (2019-12-27 23:51:46)
> > Currently the start address of a UV plane in a semiplanar YUV FB is tile
> > size (4kB) aligned. I noticed, that enforcing only this alignment leads
> > oddly to random memory corruptions on TGL while scanning out Y-tiled
> > FBs. This issue can be easily reproduced with a UV plane that is not
> > aligned to the plane's tile row size.
> >
> > Some experiments showed the correct alignment to be tile row size
> > indeed. This also makes sense, since the de-tiling fence created for the
>
> One would expect the implicit fence to follow the fence detiling HW
> logic, which does not require tile-row alignment, just 4096 alignment
> (since gen4). That suggests this logic is peculiar to the display engine.
Not sure what's an implicit fence, I only considered the fence we add
(which is added at offset 0 for the whole object via the set_tiling
IOCTL). But I suppose you mean the display would use its own fence even
if we don't add one (since an explicit fence for display is not needed
for a while now). Not sure what's the exact reason for the spec's
tile-row alignment restriction for UV surface addresses, maybe it's
required both by an implicit or explicit fence. Note that I haven't seen
the memory corruption if I didn't add the explicit fence for the object,
but I haven't checked if there are other problems even then, once I
noticed the spec alignment requirement.
To me what's logical as a rule is to not wrap around the right edge of
the fence (implicit or explicit) by programming a display surface base
address and an x offset. That would also mean that the stride of FB
surfaces (for planar YUV surfaces all surface stride's being the same)
match the stride of an implicit or explicit fence. Not sure if we
enforce all these.
> > object - with its own stride and so "left" and "right" edge - applies to
> > all the planes in the FB, so each tile row of all planes should be tile
> > row aligned.
> >
> > In fact BSpec requires this alignment since SKL. On SKL we may enforce
> > this due to the AUX plane x,y coords check, but on ICL and TGL we don't.
> > For now enforce this only on TGL; I can follow up with any necessary
> > change for ICL after more tests.
>
> Considering the severity of the error, I strongly suggest we fix all
> suspected machines and Cc:stable.
Ok, will add Cc now to this one, but would follow up with other machines
after more empirical proofs.
> > BSpec requires a stricter alignment for linear UV planes too (kind of a
> > tile row alignment), but it's unclear whether that's really needed
> > (couldn't be explained with the de-tiling fence as above) and enforcing
> > that could break existing user space; so avoid that too for now until
> > more tests.
> >
> > Cc: Chris Wilson
> > Cc: Ville Syrjälä
> > Signed-off-by: Imre Deak
> > ---
> > +static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb,
> > + int color_plane)
> > +{
> > + unsigned int tile_width, tile_height;
> > +
> > + intel_tile_dims(fb, color_plane, _width, _height);
> > +
> > + return fb->pitches[color_plane] * tile_height;
>
> Ok, that is tile_row_size.
> -Chris
___
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Re: [Intel-gfx] [PATCH 2/3] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned
Quoting Imre Deak (2019-12-30 19:20:36) > On Mon, Dec 30, 2019 at 10:53:21AM +, Chris Wilson wrote: > > Quoting Imre Deak (2019-12-27 23:51:46) > > > Currently the start address of a UV plane in a semiplanar YUV FB is tile > > > size (4kB) aligned. I noticed, that enforcing only this alignment leads > > > oddly to random memory corruptions on TGL while scanning out Y-tiled > > > FBs. This issue can be easily reproduced with a UV plane that is not > > > aligned to the plane's tile row size. > > > > > > Some experiments showed the correct alignment to be tile row size > > > indeed. This also makes sense, since the de-tiling fence created for the > > > > One would expect the implicit fence to follow the fence detiling HW > > logic, which does not require tile-row alignment, just 4096 alignment > > (since gen4). That suggests this logic is peculiar to the display engine. > > Not sure what's an implicit fence, I only considered the fence we add > (which is added at offset 0 for the whole object via the set_tiling > IOCTL). But I suppose you mean the display would use its own fence even > if we don't add one (since an explicit fence for display is not needed > for a while now). Not sure what's the exact reason for the spec's > tile-row alignment restriction for UV surface addresses, maybe it's > required both by an implicit or explicit fence. Note that I haven't seen > the memory corruption if I didn't add the explicit fence for the object, > but I haven't checked if there are other problems even then, once I > noticed the spec alignment requirement. > > To me what's logical as a rule is to not wrap around the right edge of > the fence (implicit or explicit) by programming a display surface base > address and an x offset. That would also mean that the stride of FB > surfaces (for planar YUV surfaces all surface stride's being the same) > match the stride of an implicit or explicit fence. Not sure if we > enforce all these. > > > > object - with its own stride and so "left" and "right" edge - applies to > > > all the planes in the FB, so each tile row of all planes should be tile > > > row aligned. > > > > > > In fact BSpec requires this alignment since SKL. On SKL we may enforce > > > this due to the AUX plane x,y coords check, but on ICL and TGL we don't. > > > For now enforce this only on TGL; I can follow up with any necessary > > > change for ICL after more tests. > > > > Considering the severity of the error, I strongly suggest we fix all > > suspected machines and Cc:stable. > > Ok, will add Cc now to this one, but would follow up with other machines > after more empirical proofs. Personally, I would do it in one patch. The downside of imposing a stricter alignment is increased fragmentation (and perhaps the occasional bit of rebinding), which should be of little concern. If you can figure out the meaning of the rule, please do add it to the changelog and comments, Acked-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/7] drm/i915/gt: Ensure that all new contexts clear STOP_RING (rev4)
== Series Details == Series: series starting with [1/7] drm/i915/gt: Ensure that all new contexts clear STOP_RING (rev4) URL : https://patchwork.freedesktop.org/series/71479/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7654_full -> Patchwork_15944_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_15944_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15944_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15944_full: ### IGT changes ### Possible regressions * igt@gem_wait@basic-await-all: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-tglb3/igt@gem_w...@basic-await-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/shard-tglb9/igt@gem_w...@basic-await-all.html * igt@kms_flip_tiling@flip-y-tiled: - shard-tglb: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/shard-tglb9/igt@kms_flip_til...@flip-y-tiled.html Known issues Here are the changes found in Patchwork_15944_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@vcs1-mixed-process: - shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#109276] / [fdo#112080]) +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-iclb4/igt@gem_ctx_persiste...@vcs1-mixed-process.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/shard-iclb3/igt@gem_ctx_persiste...@vcs1-mixed-process.html * igt@gem_ctx_shared@exec-single-timeline-bsd1: - shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#109276]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd1.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/shard-iclb8/igt@gem_ctx_sha...@exec-single-timeline-bsd1.html * igt@gem_eio@kms: - shard-snb: [PASS][8] -> [DMESG-WARN][9] ([i915#444]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-snb1/igt@gem_...@kms.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/shard-snb5/igt@gem_...@kms.html * igt@gem_exec_await@wide-all: - shard-tglb: [PASS][10] -> [INCOMPLETE][11] ([fdo#111736]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-tglb1/igt@gem_exec_aw...@wide-all.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/shard-tglb3/igt@gem_exec_aw...@wide-all.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#110854]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-iclb4/igt@gem_exec_balan...@smoke.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/shard-iclb8/igt@gem_exec_balan...@smoke.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#112080]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-iclb4/igt@gem_exec_paral...@vcs1-fds.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/shard-iclb8/igt@gem_exec_paral...@vcs1-fds.html * igt@gem_exec_schedule@preempt-queue-blt: - shard-tglb: [PASS][16] -> [INCOMPLETE][17] ([fdo#111677]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-tglb2/igt@gem_exec_sched...@preempt-queue-blt.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/shard-tglb8/igt@gem_exec_sched...@preempt-queue-blt.html * igt@gem_exec_schedule@preempt-queue-contexts-chain-blt: - shard-tglb: [PASS][18] -> [INCOMPLETE][19] ([fdo#111606] / [fdo#111677]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-tglb6/igt@gem_exec_sched...@preempt-queue-contexts-chain-blt.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/shard-tglb8/igt@gem_exec_sched...@preempt-queue-contexts-chain-blt.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][20] -> [SKIP][21] ([fdo#112146]) +6 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7654/shard-iclb6/igt@gem_exec_sched...@preemptive-hang-bsd.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15944/shard-iclb4/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_exec_schedule@smoketest-all: - shard-tglb: [PASS][22] -> [INCOMPLETE][23] ([i915#463]) [22]:
