Quoting Chris Wilson (2020-05-20 13:01:35)
> Quoting Tvrtko Ursulin (2020-05-20 12:54:19)
> >
> > On 20/05/2020 11:38, Chris Wilson wrote:
> > > @@ -1083,10 +1154,10 @@ print_header(struct engines *engines, double t,
> > > printf("\033[H\033[J");
> > >
> > > if
Hi Dave & Daniel,
On top of the drm-intel-next PR one fix for TypeC mode resets and
two compile time warning fixes.
CI results for your viewing:
https://intel-gfx-ci.01.org/tree/drm-intel-next-fixes/combined-alt.html
CI_DINF_189 = drm-intel-next pull
CI_DINF_190 = this pull (3 patches)
There
So lets support it.
v2: - Fixed "from" field which got corrupted for some weird reason
Reviewed-by: Manasi Navare
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Wed, May 20, 2020 at 11:30:25AM +0200, Borislav Petkov wrote:
On Tue, May 19, 2020 at 04:57:27PM -0700, Lucas De Marchi wrote:
The following files are outside of i915 maintenance scope:
arch/x86/kernel/early-quirks.c
Can we get an ack?
Acked-by: Borislav Petkov
Going forward, for
Use a spinner to create a fence, and then use that as to synchronise
another batch to cancel the spinner.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/i915/gem_exec_schedule.c | 121 +++--
1 file changed, 116 insertions(+), 5 deletions(-)
diff --git
On Thu, May 14, 2020 at 02:38:38PM +0300, Oded Gabbay wrote:
> On Tue, May 12, 2020 at 9:12 AM Daniel Vetter wrote:
> >
> > On Tue, May 12, 2020 at 4:14 AM Dave Airlie wrote:
> > >
> > > On Mon, 11 May 2020 at 19:37, Oded Gabbay wrote:
> > > >
> > > > On Mon, May 11, 2020 at 12:11 PM Daniel
On Mon, May 11, 2020 at 06:12:32PM +, Ruhl, Michael J wrote:
> >-Original Message-
> >From: dri-devel On Behalf Of
> >Daniel Vetter
> >Sent: Monday, May 11, 2020 5:12 AM
> >To: LKML
> >Cc: David Airlie ; Daniel Vetter ;
> >Intel Graphics Development ; DRI
> >Development ; Thomas
On Wed, 2020-05-20 at 11:45 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/ehl: Wa_22010271021 (rev2)
> URL : https://patchwork.freedesktop.org/series/77428/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_8506_full -> Patchwork_17716_full
>
On Wed, May 20, 2020 at 9:05 PM Daniel Vetter wrote:
>
> On Thu, May 14, 2020 at 02:38:38PM +0300, Oded Gabbay wrote:
> > On Tue, May 12, 2020 at 9:12 AM Daniel Vetter
> > wrote:
> > >
> > > On Tue, May 12, 2020 at 4:14 AM Dave Airlie wrote:
> > > >
> > > > On Mon, 11 May 2020 at 19:37, Oded
== Series Details ==
Series: drm/i915/ehl: Wa_22010271021 (rev2)
URL : https://patchwork.freedesktop.org/series/77428/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8506_full -> Patchwork_17716_full
Summary
---
We want to get rid of intel_context_pin(), convert
intel_context_create_request() first. :)
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/intel_context.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git
This reverts commit 0f1dd02295f35dcdcbaafcbcbbec0753884ab974.
This conflicts with the ww mutex handling, which needs to drop
the references after gpu submission anyway, because otherwise we
may risk unlocking a BO after first freeing it.
Signed-off-by: Maarten Lankhorst
---
We want to lock all gem objects, including the engine context objects,
rework the throttling to ensure that we can do this. Now we only throttle
once, but can take eb_pin_engine while acquiring objects. This means we
will have to drop the lock to wait. If we don't have to throttle we can
still
We have the ordering of timeline->mutex vs resv_lock wrong,
convert the i915_pin_vma and intel_context_pin as well to
future-proof this.
We may need to do future changes to do this more transaction-like,
and only get down to a single i915_gem_ww_ctx, but for now this
should work.
Signed-off-by:
Those arguments are already set as eb.file and eb.args, so kill off
the extra arguments. This will allow us to move eb_pin_engine() to
after we reserved all BO's.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 17 +++--
1 file changed, 7
Instead of using intel_context_create_request(), use intel_context_pin()
and i915_create_request directly.
Now all those calls are gone outside of selftests. :)
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 43 ++---
1 file changed, 29
We want to introduce backoff logic, but we need to lock the
pool object as well for command parsing. Because of this, we
will need backoff logic for the engine pool obj, move the batch
validation up slightly to eb_lookup_vmas, and the actual command
parsing in a separate function which can get
Checking with hweight8 if plane configuration had
changed seems to be wrong as different plane configs
can result in a same hamming weight.
So lets check the bitmask itself.
v2: Fixed "from" field which got corrupted for some weird reason
Reviewed-by: Manasi Navare
Signed-off-by: Stanislav
== Series Details ==
Series: Consider DBuf bandwidth when calculating CDCLK (rev18)
URL : https://patchwork.freedesktop.org/series/74739/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
27d0a2a78122 drm/i915: Decouple cdclk calculation from modeset checks
b0928a963b24 drm/i915:
Quoting Tvrtko Ursulin (2020-05-20 12:54:19)
>
> On 20/05/2020 11:38, Chris Wilson wrote:
> > @@ -1083,10 +1154,10 @@ print_header(struct engines *engines, double t,
> > printf("\033[H\033[J");
> >
> > if (lines++ < con_h)
> > -
This function does not use intel_context_create_request, so it has
to use the same locking order as normal code. This is required to
shut up lockdep in selftests.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 15 ---
1 file changed, 12 insertions(+),
The lock here should be interruptible, so we can backoff if needed.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
As a preparation step for full object locking and wait/wound handling
during pin and object mapping, ensure that we always pass the ww context
in i915_gem_execbuffer.c to i915_vma_pin, use lockdep to ensure this
happens.
This also requires changing the order of eb_parse slightly, to ensure
we
This is required if we want to pass a ww context in intel_context_pin
and gen6_ppgtt_pin().
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 55 ++-
.../drm/i915/gem/selftests/i915_gem_context.c | 22 +++-
2 files changed, 48
Execbuffer submission will perform its own WW locking, and we
cannot rely on the implicit lock there.
This also makes it clear that the GVT code will get a lockdep splat when
multiple batchbuffer shadows need to be performed in the same instance,
fix that up.
Signed-off-by: Maarten Lankhorst
i915_gem_ww_ctx is used to lock all gem bo's for pinning and memory
eviction. We don't use it yet, but lets start adding the definition
first.
To use it, we have to pass a non-NULL ww to gem_object_lock, and don't
unlock directly. It is done in i915_gem_ww_ctx_fini.
Changes since v1:
- Change
Instead of doing everything inside of pin_mutex, we move all pinning
outside. Because i915_active has its own reference counting and
pinning is also having the same issues vs mutexes, we make sure
everything is pinned first, so the pinning in i915_active only needs
to bump refcounts. This allows
Now that we changed execbuf submission slightly to allow us to do all
pinning in one place, we can now simply add ww versions on top of
struct_mutex. All we have to do is a separate path for -EDEADLK
handling, which needs to unpin all gem bo's before dropping the lock,
then starting over.
This
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 9 -
drivers/gpu/drm/i915/i915_vma.h | 1 +
3 files changed, 10 insertions(+), 2 deletions(-)
diff --git
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 65 --
drivers/gpu/drm/i915/gem/i915_gem_object.h | 1 +
2 files changed, 49 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
This reverts commit 7dc8f1143778 ("drm/i915/gem: Drop relocation
slowpath"). We need the slowpath relocation for taking ww-mutex
inside the page fault handler, and we will take this mutex when
pinning all objects.
[mlankhorst: Adjusted for reloc_gpu_flush() changes]
Cc: Chris Wilson
Cc: Matthew
Make sure vma_lock is not used as inner lock when kernel context is used,
and add ww handling where appropriate.
Ensure that execbuf selftests keep passing by using ww handling.
Signed-off-by: Maarten Lankhorst
---
.../i915/gem/selftests/i915_gem_coherency.c | 26 ++--
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 51 +++-
1 file changed, 33 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 9d306dc9849d..a8f1d438affd
This is the last part outside of selftests that still don't use the
correct lock ordering of timeline->mutex vs resv_lock.
With gem fixed, there are a few places that still get locking wrong:
- gvt/scheduler.c
- i915_perf.c
- Most if not all selftests.
Changes since v1:
- Add
We want to start using ww locking in intel_context_pin, for this
we need to lock multiple objects, and the single i915_gem_object_lock
is not enough.
Convert to using ww-waiting, and make sure we always pin intel_context_state,
even if we don't have a renderstate object.
Signed-off-by: Maarten
Some i915 selftests still use i915_vma_lock() as inner lock, and
intel_context_create_request() intel_timeline->mutex as outer lock.
Fortunately for selftests this is not an issue, they should be fixed
but we can move ahead and cleanify lockdep now.
Signed-off-by: Maarten Lankhorst
---
== Series Details ==
Series: drm/i915/hdcp: Add additional R0' wait
URL : https://patchwork.freedesktop.org/series/77439/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8506_full -> Patchwork_17719_full
Summary
---
== Series Details ==
Series: drm/i915/hdcp: Add additional R0' wait (rev2)
URL : https://patchwork.freedesktop.org/series/77439/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8511 -> Patchwork_17731
Summary
---
== Series Details ==
Series: Consider DBuf bandwidth when calculating CDCLK (rev18)
URL : https://patchwork.freedesktop.org/series/74739/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
-
On Tue, 2020-05-19 at 13:12 -0700, Swathi Dhanavanthri wrote:
> This is a permanent w/a for JSL/EHL.This is to be applied to the
> PCH types on JSL/EHL ie JSP/MCC
> Bspec: 52888
>
> v2: Fixed the wrong usage of logical OR(ville)
>
> Signed-off-by: Swathi Dhanavanthri
> ---
>
On 20/05/2020 11:38, Chris Wilson wrote:
With integrated graphics the TDP is shared between the gpu and the cpu,
knowing the total energy consumed by the package is relevant to
understanding throttling.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 195
== Series Details ==
Series: drm/i915/ehl: Extend w/a 14010685332 to JSP/MCC (rev2)
URL : https://patchwork.freedesktop.org/series/77382/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8506_full -> Patchwork_17717_full
From: Sean Paul
We're seeing some R0' mismatches in the field, particularly with
repeaters. I'm guessing the (already lenient) 300ms wait time isn't
enough for some setups. So add an additional wait when R0' is
mismatched.
Signed-off-by: Sean Paul
Changes in v2:
- Actually add the delay in
== Series Details ==
Series: drm: Replace deprecated function in drm_crtc_helper
URL : https://patchwork.freedesktop.org/series/77467/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8511 -> Patchwork_17729
Summary
---
== Series Details ==
Series: drm/i915/gt: Trace the CS interrupt (rev4)
URL : https://patchwork.freedesktop.org/series/77441/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8511 -> Patchwork_17727
Summary
---
== Series Details ==
Series: series starting with [01/23] Revert "drm/i915/gem: Drop relocation
slowpath".
URL : https://patchwork.freedesktop.org/series/77472/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8511 -> Patchwork_17730
According to BSpec max BW per slice is calculated using formula
Max BW = CDCLK * 64. Currently when calculating min CDCLK we
account only per plane requirements, however in order to avoid
FIFO underruns we need to estimate accumulated BW consumed by
all planes(ddb entries basically) residing on
== Series Details ==
Series: series starting with [1/3] drm/i915/params: don't expose
inject_probe_failure in debugfs (rev2)
URL : https://patchwork.freedesktop.org/series/77366/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8511 -> Patchwork_17728
Pre-allocate command buffer in atomic_commit using intel_dsb_prepare
function which also includes pinning and map in cpu domain.
No functional change is dsb write/commit functions.
Now dsb get/put function is removed and ref-count mechanism is
not needed. Below dsb api added to do respective job
== Series Details ==
Series: series starting with [01/23] Revert "drm/i915/gem: Drop relocation
slowpath".
URL : https://patchwork.freedesktop.org/series/77472/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e8a9ca7ebbde Revert "drm/i915/gem: Drop relocation slowpath".
-:80:
== Series Details ==
Series: series starting with [01/23] Revert "drm/i915/gem: Drop relocation
slowpath".
URL : https://patchwork.freedesktop.org/series/77472/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be
== Series Details ==
Series: Consider DBuf bandwidth when calculating CDCLK (rev18)
URL : https://patchwork.freedesktop.org/series/74739/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8511 -> Patchwork_17733
Summary
== Series Details ==
Series: series starting with [1/3] drm/i915/params: don't expose
inject_probe_failure in debugfs (rev2)
URL : https://patchwork.freedesktop.org/series/77366/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each
== Series Details ==
Series: series starting with [1/3] drm/i915/params: don't expose
inject_probe_failure in debugfs (rev2)
URL : https://patchwork.freedesktop.org/series/77366/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6190d8ce3829 drm/i915/params: don't expose
On Mon, May 18, 2020 at 12:41 PM Ramalingam C wrote:
>
> On 2020-05-18 at 10:32:09 -0400, Sean Paul wrote:
> > On Fri, May 15, 2020 at 10:48 AM Ramalingam C
> > wrote:
> > >
> > > On 2020-04-29 at 15:54:46 -0400, Sean Paul wrote:
> > > > From: Sean Paul
> > > >
> > > > Changes in v6:
> > > >
== Series Details ==
Series: drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev10)
URL : https://patchwork.freedesktop.org/series/73036/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8511 -> Patchwork_17732
Check that if we submit a request that is held up by an external fence,
that we conserve power during the wait as the GPU is idle.
Signed-off-by: Chris Wilson
Cc: Venkata Sandeep Dhanalakota
---
tests/i915/i915_pm_rc6_residency.c | 82 ++
1 file changed, 82
From: Sean Paul
If userspace sets the CP property to DESIRED while it's already ENABLED,
the driver will try to re-enable HDCP. On some displays, this will
result in R0' mismatches. I'm guessing this is because the display is
still sending back Ri instead of re-authenticating.
At any rate, we
== Series Details ==
Series: Consider DBuf bandwidth when calculating CDCLK (rev15)
URL : https://patchwork.freedesktop.org/series/74739/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8506_full -> Patchwork_17718_full
== Series Details ==
Series: drm/i915/gt: Trace the CS interrupt (rev7)
URL : https://patchwork.freedesktop.org/series/77441/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17739
Summary
---
== Series Details ==
Series: series starting with [01/22] drm/i915/gem: Suppress some random warnings
URL : https://patchwork.freedesktop.org/series/77459/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8509_full -> Patchwork_17724_full
== Series Details ==
Series: drm/i915/gt: Cancel the flush worker more thoroughly
URL : https://patchwork.freedesktop.org/series/77490/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a3dd258ba778 drm/i915/gt: Cancel the flush worker more thoroughly
-:13:
== Series Details ==
Series: drm/i915: Add psr_safest_params
URL : https://patchwork.freedesktop.org/series/77491/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7f3095d8f257 drm/i915: Add psr_safest_params
-:98: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open
On Wed, May 20, 2020 at 9:08 AM Sean Paul wrote:
>
> From: Sean Paul
>
> We're seeing some R0' mismatches in the field, particularly with
> repeaters. I'm guessing the (already lenient) 300ms wait time isn't
> enough for some setups. So add an additional wait when R0' is
> mismatched.
>
I think
Since the worker may rearm, we currently are only guaranteed to flush
the work if we cancel the timer. If the work was running at the time we
try and cancel it, we will wait for it to complete, but it may leave
items in the pool and requeue the work. If we rearrange the immediate
discard of the
== Series Details ==
Series: drm/i915/gt: Trace the CS interrupt (rev6)
URL : https://patchwork.freedesktop.org/series/77441/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17737
Summary
---
We have traces for the semaphore and the error, but not the far more
frequent CS interrupts. This is likely to be too much, but for the
purpose of live_unlite_preempt it may answer a question or two.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 6 +-
== Series Details ==
Series: drm/i915/gt: Cancel the flush worker more thoroughly
URL : https://patchwork.freedesktop.org/series/77490/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17736
Summary
---
This parameter is meant to be used when PSR issues are found as some
issues in the past was due wrong values set in VBT so this would be
a quick and easy way to ask users or for us to check if the issue is
due VBT values.
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
== Series Details ==
Series: drm/i915: Add psr_safest_params
URL : https://patchwork.freedesktop.org/series/77491/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17738
Summary
---
**SUCCESS**
No
== Series Details ==
Series: drm/i915/hdcp: Avoid duplicate HDCP enables
URL : https://patchwork.freedesktop.org/series/77487/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17734
Summary
---
== Series Details ==
Series: drm/i915/gt: Trace the CS interrupt (rev5)
URL : https://patchwork.freedesktop.org/series/77441/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17735
Summary
---
== Series Details ==
Series: drm/i915: Disable semaphore inter-engine sync without timeslicing (rev2)
URL : https://patchwork.freedesktop.org/series/77462/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8509_full -> Patchwork_17726_full
Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
The values for VBT are currently not in BSpec. If we assume the latest
is ICL (like we did for TGL), then the mapping is wrong per VBT we can
currently parse.
>From spec we have registers GPIO_CTL[1-4], so we should not do
From: Matt Roper
DG1's vswing tables are the same for eDP and HDMI but have slight
differences from ICL/TGL for DP.
Bspec: 49291
Cc: Clinton Taylor
Cc: José Roberto de Souza
Cc: Radhakrishna Sripada
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
From: Matt Roper
DG1 does some additional pcode/uncore handshaking at
boot time; this handshaking must complete before various other pcode
commands are effective and before general work is submitted to the GPU.
We need to poll a new pcode mailbox during startup until it reports that
this
DG1 has one more combo phy port, no TC and all irq handling goes through
SDE, like for MCC.
Cc: Anshuman Gupta
Cc: José Roberto de Souza
Cc: Imre Deak
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 57 +
drivers/gpu/drm/i915/i915_reg.h |
From: Matt Roper
Certain combo PHYs act as a compensation master to other PHYs and need
to be initialized with a special irefgen bit in the PORT_COMP_DW8
register. Previously PHY A was the only compensation master (for PHYs
B & C), but RKL adds a fourth PHY which is slaved to PHY C instead.
From: Fernando Pacheco
The error detection and correction capability
for GRF and instruction cache (IC) will utilize
the new interrupt and error handling infrastructure
for dgfx products. The GFX device can generate
a number of classes of error under the new
infrastructure: correctable,
DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
single macro that chooses the correct register according to the phy
being accessed, use the correct bitfields for each pll/phy and implement
separate
From: Stuart Summers
DG1 shares some workarounds with TGL and RKL and also has some
additional workarounds of its own.
Media power gating should not be applied so we just set it to
nop_init_clock_gating().
BSpec: 53508
Cc: Matt Atwood
Cc: Matt Roper
Cc: Radhakrishna Sripada
Cc: José
From: Aditya Swarup
Enable PORTS A and B for DG1 initially, the other ports still need more
plumbing code in order to be enabled.
Cc: Clinton Taylor
Cc: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
From: Anusha Srivatsa
Bspec asks us to remove the special programming of the
SHPD_FILTER_CNT register which we have been doing since CNP+.
Bspec: 49305
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 3 ++-
1 file changed,
From: Matt Roper
The only bit we use in PHY_MISC is DE_IO_COMP_PWR_DOWN, and the bspec
details for that bit tell us that it need only be set for PHY-A and
PHY-B. It also turns out that there isn't even an instance of the
PHY_MISC register for PHY-D on this platform. Let's extend the EHL/RKL
DG1 has master unit interrupt register which is used to indicate the
correct source of interrupt.
Cc: Radhakrishna Sripada
Cc: Daniele Spurio Ceraolo
Cc: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +++
drivers/gpu/drm/i915/i915_irq.c | 56
From: Matt Roper
As with RKL, DG1's VBT outputs are indexed according to PHY rather than
DDI.
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_bios.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git
From: Matt Roper
RKL and TGL share some general gen12 workarounds, but each platform also
has its own platform-specific workarounds.
Cc: Matt Atwood
Signed-off-by: Matt Roper
Link:
https://patchwork.freedesktop.org/patch/msgid/20200504225227.464666-23-matthew.d.ro...@intel.com
---
From: Matt Roper
RKL uses DDI's A, B, TC1, and TC2 which need to map to combo PHY's A-D.
Bspec: 49181
Cc: Imre Deak
Cc: Aditya Swarup
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Link:
https://patchwork.freedesktop.org/patch/msgid/20200504225227.464666-14-matthew.d.ro...@intel.com
---
From: Uma Shankar
Most of TGL power wells are re-used for DG1. However, AUDIO Power
Domain is moved from PG3 to PG0. Handle the change and initialize
power wells with the new power well structure.
Some of the Audio Streaming logic still remains in PW3 so still
it needs to be enabled.
DDIA,
From: Aditya Swarup
Add DG1 DPLL Enable register macro and use the macro to enable the
correct DPLL based on PLL id.
Bspec: 49443, 49206
Cc: Clinton Taylor
Cc: Matt Roper
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30
DG1 has a new MOCS table. We still use the old definition of the table,
but as for any dgfx card it doesn't contain the control_value values
(these values don't matter as we won't program them).
Bspec: 45101
Cc: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
From: Clinton A Taylor
HPD pins are inverted for DG1 platform.
Bspec: 49956
Cc: José Roberto de Souza
Cc: Matt Roper
Signed-off-by: Clinton A Taylor
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 4
drivers/gpu/drm/i915/i915_reg.h | 4
2 files changed, 8
From: Matt Roper
DG1 always uses a 38.4 MHz rawclk rather and we don't need to read
fuse straps like on CNP+. frequencies on CNP+. Note that register bits
associated with this frequency confusingly use 37 for the divider field
rather than 38 as you might expect.
For simplicity, let's just
Return the old value read so some places of the code can still do the
rmw but add warnings/errors about the value it read.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_de.h | 4 ++--
drivers/gpu/drm/i915/intel_uncore.h | 10 +++---
2 files changed, 9
From: Venkata Sandeep Dhanalakota
On dgfx register range has been extended to go up to 4MB.
Cc: Daniele Ceraolo Spurio
Cc: Michael J. Ruhl
Signed-off-by: Venkata Sandeep Dhanalakota
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_uncore.c | 4
1 file changed, 4
From: Matt Roper
If HTI (also sometimes called HDPORT) is enabled at startup, it may be
using some of the PHYs and DPLLs making them unavailable for general
usage. Let's read out the HDPORT_STATE register and avoid making use of
resources that HTI is already using.
Bspec: 49189
Bspec: 53707
From: Abdiel Janulgue
Bspec: 44463
Cc: Matthew Auld
Cc: James Ausmus
Cc: Joonas Lahtinen
Cc: Matt Roper
Signed-off-by: Abdiel Janulgue
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
include/drm/i915_pciids.h | 4
2 files changed, 6 insertions(+), 1
DG1 is a gen12 dgfx platform. This is the first batch of patches to
support it. It also depends on some in-flight patches adding RKL. In
order for this series to be compiled, I'm including them here.
While converting some of these patches to the current
intel_uncore/intel_de APIs I thought it
From: Abdiel Janulgue
Bspec: 33617, 33617
Cc: José Roberto de Souza
Cc: Daniele Ceraolo Spurio
Cc: Stuart Summers
Cc: Vanshidhar Konda
Cc: Lucas De Marchi
Cc: Aravind Iddamsetty
Cc: Matt Roper
Signed-off-by: Abdiel Janulgue
Signed-off-by: Lucas De Marchi
---
From: Matt Roper
The pin mapping for the final two outputs varies according to which PCH
is present on the platform: with TGP the pins are remapped into the TC
range, whereas with CMP they stay in the traditional combo output range.
Bspec: 49181
Cc: Aditya Swarup
Signed-off-by: Matt Roper
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