> I started by splitting Alexei's SKL PCI ID fix into
> logical chunks, and then ocd kicked in a bit...
Thank you for picking it up. Please do not forget
https://lists.freedesktop.org/archives/intel-gfx/2020-April/237944.html
Alexei
>
> Cc: Alexei Podtelezhnikov
>
> Alexei Podtelezhnikov
Since we want to read the values from the HWSP as written to by the GPU,
warn the compiler that the values are volatile.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 22 ++---
1 file changed, 11 insertions(+), 11 deletions(-)
Add a SRM read back of the aux invalidation register after poking
hsdes: 1809175790, as failing to do so leads to writes going astray.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2169
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 31
This is an attempt to chase down some preempt-to-busy races with
breadcrumb signaling on the virtual engines. By using more semaphore
spinners than available engines, we encourage very short timeslices, and
we make each batch of random duration to try and coincide the end of a
batch with the
== Series Details ==
Series: series starting with [v6,01/11] HAX to make DSC work on the icelake
test system (rev2)
URL : https://patchwork.freedesktop.org/series/79534/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8758 -> Patchwork_18196
== Series Details ==
Series: Remaining RKL patches (rev7)
URL : https://patchwork.freedesktop.org/series/77971/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: PCI ID cleanup
URL : https://patchwork.freedesktop.org/series/79561/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8757_full -> Patchwork_18192_full
Summary
---
**FAILURE**
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: HAX Try the bspec value for
CLKTOP2_CORECLKCTL
URL : https://patchwork.freedesktop.org/series/79569/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7e44cd55cc41 drm/i915/dp: HAX Try the bspec value for
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: HAX Try the bspec value for
CLKTOP2_CORECLKCTL
URL : https://patchwork.freedesktop.org/series/79569/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: HAX Try the bspec value for
CLKTOP2_CORECLKCTL
URL : https://patchwork.freedesktop.org/series/79569/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8759 -> Patchwork_18198
After doing normal PHY-B initialization on Rocket Lake, we need to
manually copy some additional PHY-A register values into PHY-B
registers.
Note that the bspec's combo phy page doesn't specify that this
workaround is restricted to specific platform steppings (and doesn't
even do a very good job
RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register.
v2:
- Fix inverted mask application when updating ICL_DPCLKA_CFGCR0
- Checkpatch style fixes
Bspec: 50287
Cc: Aditya Swarup
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
The first couple patches here already have r-b's from Jose, but since
it's been a while since they were last sent to the list we should get
another CI pass before merging them.
Changes since v7:
- Undo the renumbering of PLL IDs in the DPLL4 patch; the shared DPLL
code has deep-rooted
If HTI (also sometimes called HDPORT) is enabled at startup, it may be
using some of the PHYs and DPLLs making them unavailable for general
usage. Let's read out the HDPORT_STATE register and avoid making use of
resources that HTI is already using.
v2:
- Fix minor checkpatch warnings
v3:
-
Rocket Lake has a third DPLL (called 'DPLL4') that must be used to
enable a third display. Unlike EHL's variant of DPLL4, the RKL variant
behaves the same as DPLL0/1. And despite its name, the DPLL4 registers
are offset as if it were DPLL2.
v2:
- Add new .update_ref_clks() hook.
v3:
-
RKL and TGL share some general gen12 workarounds, but each platform also
has its own platform-specific workarounds.
v2:
- Add Wa_1604555607 for RKL. This makes RKL's ctx WA list identical to
TGL's, so we'll have both functions call the tgl_ function for now;
this workaround isn't listed
== Series Details ==
Series: Remaining RKL patches (rev7)
URL : https://patchwork.freedesktop.org/series/77971/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8758 -> Patchwork_18197
Summary
---
**SUCCESS**
No
== Series Details ==
Series: series starting with [1/5] drm/i915: Be wary of data races when reading
the active execlists (rev2)
URL : https://patchwork.freedesktop.org/series/79551/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8757_full -> Patchwork_18193_full
== Series Details ==
Series: series starting with [1/2] drm/i915: Move WaDisableDopClockGating:skl
to skl_init_clock_gating()
URL : https://patchwork.freedesktop.org/series/79563/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8757_full -> Patchwork_18194_full
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index
Keep the link rate const at 2.7 Gpbs, lane count =4 and do not
fallback on link training. See if kms_atomic_transition test passes
in constant configuration
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 +--
On Thu, 2020-07-16 at 15:05 -0700, Matt Roper wrote:
> If HTI (also sometimes called HDPORT) is enabled at startup, it may be
> using some of the PHYs and DPLLs making them unavailable for general
> usage. Let's read out the HDPORT_STATE register and avoid making use of
> resources that HTI is
On Thu, 2020-07-16 at 22:04 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> It's silly to have if(SKL) checks in gen9_init_clock_gating() when
> we can just move those bits into skl_init_clock_gating().
>
> I'm not entirely convinced we even need this w/a, or if we do
> then maybe we want
On Thu, 2020-07-16 at 15:05 -0700, Matt Roper wrote:
> After doing normal PHY-B initialization on Rocket Lake, we need to
> manually copy some additional PHY-A register values into PHY-B
> registers.
>
> Note that the bspec's combo phy page doesn't specify that this
> workaround is restricted to
Hi all,
On Wed, 15 Jul 2020 at 12:57, Daniel Vetter wrote:
> On Wed, Jul 15, 2020 at 1:47 PM Daniel Stone wrote:
> > On Wed, 15 Jul 2020 at 12:05, Bas Nieuwenhuizen
> > wrote:
> > > Yes, this is used as part of the Android stack on Chrome OS (need to
> > > see if ChromeOS specific, but
> > >
On Thu, Jul 16, 2020 at 12:28:47PM -0700, Umesh Nerlige Ramappa wrote:
On Thu, Jul 16, 2020 at 09:44:46PM +0300, Lionel Landwerlin wrote:
On 16/07/2020 21:06, Umesh Nerlige Ramappa wrote:
On Thu, Jul 16, 2020 at 06:32:10PM +0300, Lionel Landwerlin wrote:
On 14/07/2020 10:22, Umesh Nerlige
== Series Details ==
Series: series starting with [v6,01/11] HAX to make DSC work on the icelake
test system (rev2)
URL : https://patchwork.freedesktop.org/series/79534/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8758_full -> Patchwork_18196_full
== Series Details ==
Series: Remaining RKL patches (rev7)
URL : https://patchwork.freedesktop.org/series/77971/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8758_full -> Patchwork_18197_full
Summary
---
**FAILURE**
From: Piotr Maciejewski
It is useful to have markers in the OA reports to identify triggered
reports. Whitelist some OA counters that can be used as markers.
A triggered report can be found faster if we can sample the HW tail and
head registers when the report was triggered. Whitelist OA buffer
From: Piotr Maciejewski
i915 used to support time based sampling mode which is good for overall
system monitoring, but is not enough for query mode used to measure a
single draw call or dispatch. Gen9-Gen11 are using current i915 perf
implementation for query, but Gen12+ requires a new approach
From: Piotr Maciejewski
OA reports can be triggered into the OA buffer by writing into the
OAREPORTTRIG registers. Whitelist the registers to allow user to trigger
reports.
Signed-off-by: Piotr Maciejewski
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_workarounds.c |
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