== Series Details ==
Series: drm/i915: Remove obj->mm.lock! (rev14)
URL : https://patchwork.freedesktop.org/series/82337/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter
or member 'ww'
On Wed, Jan 27, 2021 at 08:19:09PM +0200, Imre Deak wrote:
> At least on some TGL platforms PUNIT wants to access some display HW
> registers, but it doesn't handle display power managment (disabling DC
> states as required) and so this register access will lead to a hang. To
> prevent this
Display13 brings enhanced underrun recovery: the hardware can somewhat
mitigate underruns by using an interpolated replacement pixel (soft
underrun) or the previous pixel (hard underrun). Furthermore, underruns
can now be caused downstream by the port, even if the pipe itself is
operating
From: Vandita Kulkarni
We need slice height to calculate few RC parameters
hence assign slice height first.
Cc: Manasi Navare
Signed-off-by: Vandita Kulkarni
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
Let's start preparing for upcoming platforms that will use a Display13
design.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 11 +++
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
3 files changed, 14
From: Nischal Varide
If the panel is 12bpc then Dithering is not enabled in the Legacy
dithering block , instead its Enabled after the C1 CC1 pipe post
color space conversion.For a 6bpc pannel Dithering is enabled in
Legacy block.
Cc: Uma Shankar
Signed-off-by: Nischal Varide
Signed-off-by:
From: Uma Shankar
Enable LPSP for Display13 and get the proper power well
enable check in place. For Display13 it is PW2 which
need to check for LPSP.
Cc: Anshuman Gupta
Cc: Animesh Manna
Cc: Matt Roper
Suggested-by: Matt Roper
Signed-off-by: Uma Shankar
Signed-off-by: Anshuman Gupta
Aside from the hardware-managed PG0, Display13 has power wells 1-2 and
A-D. These power wells should be enabled/disabled according to the
following dependency tree (enable top to bottom, disable bottom to top):
PG0
|
--PG1--
/ \
From: Vandita Kulkarni
Move the platform specific max bpc calculation into
intel_dp_dsc_compute_bpp function
Cc: Manasi Navare
Signed-off-by: Vandita Kulkarni
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++--
1 file changed, 10 insertions(+),
From: Vandita Kulkarni
Support compression BPPs from bpc to uncompressed BPP -1.
So far we have 8,10,12 as valid compressed BPPS now the
support is extended.
Cc: Manasi Navare
Signed-off-by: Vandita Kulkarni
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 32
If VT-d is active, the memory bandwidth usage of the display is 5%
higher. Take this into account when determining whether we can support
a display configuration.
Bspec: 64631
Cc: Matt Atwood
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 3 +++
1 file changed, 3
From: Juha-Pekka Heikkilä
Display13 supports plane strides up to 128KB.
Cc: Vandita Kulkarni
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 6 -
drivers/gpu/drm/i915/display/intel_sprite.c | 24 ++--
Display13 continues to use the same "skylake-style" watermark
programming as other recent platforms. The only change to the watermark
calculations compared to Display12 is that Display13 now allows a
maximum of 255 lines vs the old limit of 31.
Due to the larger possible lines value, the
Cc: Aditya Swarup
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4
drivers/gpu/drm/i915/i915_reg.h| 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
The DDI naming template for Display12 went A-C, TC1-TC6. With
Display13, that naming scheme for DDI's has now changed to A-E, TC1-TC4.
The Display13 design keeps the register offsets and bitfields relating
to the TC outputs in the same location they were on Display12. The new
"D" and "E"
On Thu, 2021-01-21 at 15:15 +0200, Imre Deak wrote:
> On Tue, Jan 19, 2021 at 08:47:25AM +0200, Almahallawy, Khaled wrote:
> > On Mon, 2021-01-18 at 20:31 +0200, Imre Deak wrote:
> > > Atm, the driver programs explicitly the default transparent link
> > > training mode (0x55) to
Previously when reading Send_Pairing_Info, RxInfo by itself was read
once to retrieve the DEVICE_COUNT and then a second time when reading
the RepeaterAuth_Send_ReceiverID_List which contains RxInfo.
On a couple HDCP 2.2 docks, this second read attempt on RxInfo fails
due to no Ack response. This
Update cp_irq_count_cached when we handle reading the messages rather
than writing a message to make sure the value is up to date and not
stale from a previously handled CP_IRQ. AKE flow doesn't always respond
to a read with a write msg.
E.g. currently AKE_Send_Pairing_Info will "timeout"
On 28/01/2021 16:26, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2021-01-28 15:56:19)
On 25/01/2021 14:01, Chris Wilson wrote:
diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h
b/drivers/gpu/drm/i915/i915_priolist_types.h
index bc2fa84f98a8..1200c3df6a4a 100644
---
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Nuke not needed members of
dram_info
URL : https://patchwork.freedesktop.org/series/86404/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9695 -> Patchwork_19531
== Series Details ==
Series: series starting with [1/5] drm/i915: Skip vswing programming for TBT
(rev2)
URL : https://patchwork.freedesktop.org/series/86402/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9695 -> Patchwork_19532
== Series Details ==
Series: Preliminary Display13 support
URL : https://patchwork.freedesktop.org/series/86409/
State : failure
== Summary ==
Applying: drm/i915/display13: add Display13 characteristics
Applying: drm/i915/display13: Handle proper AUX interrupt bits
Applying:
Quoting Tvrtko Ursulin (2021-01-28 16:42:44)
>
> On 28/01/2021 16:26, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2021-01-28 15:56:19)
> >> On 25/01/2021 14:01, Chris Wilson wrote:
> >>>struct i915_priolist {
> >>>struct list_head requests;
> >>
> >> What would be on this list?
Quoting Tvrtko Ursulin (2021-01-28 16:42:44)
>
> On 28/01/2021 16:26, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2021-01-28 15:56:19)
> >> On 25/01/2021 14:01, Chris Wilson wrote:
> >>> diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h
> >>>
On Mon, Jan 25, 2021 at 02:01:15PM +, Chris Wilson wrote:
> Replace the priolist rbtree with a skiplist. The crucial difference is
> that walking and removing the first element of a skiplist is O(1), but
> O(lgN) for an rbtree, as we need to rebalance on remove. This is a
> hindrance for
On Tue, Jan 26, 2021 at 01:28:09AM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/dp/mst: Export
> drm_dp_get_vc_payload_bw()
> URL : https://patchwork.freedesktop.org/series/86267/
> State : success
Patchset pushed to -din with the docbook fix,
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/hdcp: update cp_irq_count_cached
in intel_dp_hdcp2_read_msg()
URL : https://patchwork.freedesktop.org/series/86424/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9696 -> Patchwork_19534
== Series Details ==
Series: Final set of patches for ADLS enabling (rev2)
URL : https://patchwork.freedesktop.org/series/86322/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9690_full -> Patchwork_19525_full
Summary
On 27/01/2021 09:06, Chris Wilson wrote:
In gen8_emit_flush_xcs, we have to look at all the engines the request
may execute on, and emit an aux-invalidate for each. Currently, we
handle the virtual engine by looking at its engine mask, but that is
copied and refined as the
== Series Details ==
Series: disable the QSES check for HDCP2.2 over MST
URL : https://patchwork.freedesktop.org/series/86375/
State : failure
== Summary ==
Applying: drm/i915/hdcp: disable the QSES check for HDCP2.2 over MST
Using index info to reconstruct a base tree...
M
Quoting Tvrtko Ursulin (2021-01-27 15:58:12)
> Okay makes sense. The change in key drives the requirement so just
> please mention in the commit message and I'll tackle the skip list
> mechanics in the meantime.
In the following patches, we introduce a new sort key to the scheduler,
a virtual
On 25/01/2021 14:01, Chris Wilson wrote:
The first "scheduler" was a topographical sorting of requests into
priority order. The execution order was deterministic, the earliest
submitted, highest priority request would be executed first. Priority
inheritance ensured that inversions were kept at
On 1/11/2021 10:07 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Limit pre-skl plane stride to below 4k or 8k pixels (depending on
the platform). We do this in order guarantee that TILEOFF/OFFSET.x
does not get too big.
Currently this is not a problem as we align SURF to 4k, and so
On 2021/1/27 上午5:46, Brian Welty wrote:
> We'd like to revisit the proposal of a GPU cgroup controller for managing
> GPU devices but with just a basic set of controls. This series is based on
> the prior patch series from Kenny Ho [1]. We take Kenny's base patches
> which implement the basic
On 2021.01.29 00:49:32 +, Chris Wilson wrote:
> Rather than break existing context objects by incorrectly forcing them
> to rogue cache coherency and trying to assert a new mapping, read the
> reg whitelist from the default context image.
>
So this work actually lived within internal for some
On 2021/1/27 上午5:46, Brian Welty wrote:
> We'd like to revisit the proposal of a GPU cgroup controller for managing
> GPU devices but with just a basic set of controls. This series is based on
> the prior patch series from Kenny Ho [1]. We take Kenny's base patches
> which implement the basic
== Series Details ==
Series: series starting with [v5,1/8] drm/i915: make local-memory probing a GT
operation (rev2)
URL : https://patchwork.freedesktop.org/series/86355/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9693_full -> Patchwork_19527_full
Use the right intel_gt stored as a backpointer in intel_vgpu.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gvt/execlist.c | 8 +++-
drivers/gpu/drm/i915/gvt/scheduler.c | 3 +--
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/execlist.c
Rather than break existing context objects by incorrectly forcing them
to rogue cache coherency and trying to assert a new mapping, read the
reg whitelist from the default context image.
And use gvt->gt, never _priv->gt.
Fixes: 493f30cd086e ("drm/i915/gvt: parse init context to update cmd
== Series Details ==
Series: series starting with [1/2] drm/i915/gvt: Parse default state to update
reg whitelist
URL : https://patchwork.freedesktop.org/series/86425/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9696 -> Patchwork_19535
== Series Details ==
Series: drm: Move struct drm_device.pdev to legacy (rev6)
URL : https://patchwork.freedesktop.org/series/84205/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9693_full -> Patchwork_19528_full
Summary
Take a simple lock so we hold ww around (un)pin_pages as needed.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
Only needs to convert a single call to the unlocked version.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/selftest_context.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c
We map the initial context during first pin.
This allows us to remove pin_map from state allocation, which saves
us a few retry loops. We won't need this until first pin anyway.
intel_ring_submission_setup() is also reworked slightly to do all
pinning in a single ww loop.
Changes since v1:
-
Also quite simple, a single call needs to use the unlocked version.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Try to pin to ggtt first, and use a full ww loop to handle
eviction correctly.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 37 +++
1 file changed, 24 insertions(+), 13 deletions(-)
diff --git
We're starting to require the reservation lock for pinning,
so wait until we have that.
Update the selftests to handle this correctly, and ensure pin is
called in live_hwsp_rollover_user() and mock_hwsp_freelist().
Changes since v1:
- Fix NULL + XX arithmatic, use casts. (kbuild)
Changes since
This allows us to remove pin_map from state allocation, which saves
us a few retry loops. We won't need this until first pin, anyway.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
.../drm/i915/gt/intel_execlists_submission.c | 26 ---
1 file changed, 23
Use unlocked versions when the ww lock is not held.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/selftest_ring_submission.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
igt_emit_store_dw needs to use the unlocked version, as it's not
holding a lock. This fixes igt_gpu_fill_dw() which is used by
some other selftests.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c | 2 +-
1 file changed, 1
Straightforward conversion, just convert a bunch of calls to
unlocked versions.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 28 ++-
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git
With userptr fixed, there is no need for all separate lockdep classes
now, and we can remove all lockdep tricks used. A trylock in the
shrinker is all we need now to flatten the locking hierarchy.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
Straightforward conversion by using unlocked versions.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/selftests/i915_request.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
We previously complained when ww == NULL.
This function is now only used in selftests to pin an object,
and ww locking is now fixed.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
.../i915/gem/selftests/i915_gem_coherency.c | 14 +
Straightforward conversion, just convert a bunch of calls to
unlocked versions.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Userptr should not need the kernel for a userspace memcpy, userspace
needs to call memcpy directly.
Specifically, disable i915_gem_pwrite_ioctl() and i915_gem_pread_ioctl().
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
-- Still needs an ack from relevant userspace that it
Instead of multiple lockings, lock the object once,
and perform the ww dance around attach_phys and pin_pages.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/display/intel_display.c | 69 ---
drivers/gpu/drm/i915/display/intel_display.h
We may create page table objects on the fly, but we may need to
wait with the ww lock held. Instead of waiting on a freed obj
lock, ensure we have the same lock for each object to keep
-EDEADLK working. This ensures that i915_vma_pin_ww can lock
the page tables when required.
Signed-off-by:
In the ucode functions, the calls are done before userspace runs,
when debugging using debugfs, or when creating semi-permanent mappings;
we can safely use the unlocked versions that does the ww dance for us.
Because there is no pin_pages_unlocked yet, add it as convenience function.
This
We need to lock the object to move it to the correct domain,
add the missing lock.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git
Ensure we hold the lock around put_pages, and use the unlocked wrappers
for pinning pages and mappings.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff
Straightforward conversion, just convert a bunch of calls to
unlocked versions.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git
It doesn't make sense to export a memory address, we will prevent
allowing access this way to different address spaces when we
rework userptr handling, so best to explicitly disable it.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
Cc: Jason Ekstrand
-- Still needs an ack
Convert a few calls to use the unlocked versions.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
There are a couple of ioctl's related to tiling and cache placement,
that make no sense for userptr, reject those:
- i915_gem_set_tiling_ioctl()
Tiling should always be linear for userptr. Changing placement will
fail with -ENXIO.
- i915_gem_set_caching_ioctl()
Userptr memory should
Because of the long lifetime of the mapping, we cannot wrap this in a
simple limited ww lock. Just use the unlocked version of pin_map,
because we'll likely release the mapping a lot later, in a different
thread.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
We need to take the obj lock to pin pages, so wait until the callers
have done so, before making the object unshrinkable.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +
.../gpu/drm/i915/gem/i915_gem_object_blt.c| 6
By default, we assume that it's called inside igt_create_request
to keep existing selftests working, but allow for manual pinning
when passing a ww context.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/selftests/igt_spinner.c | 136 ---
Straightforward conversion, just convert a bunch of calls to
unlocked versions.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
vmap is using pin_pages, but needs to use ww locking,
add pin_pages_unlocked to correctly lock the mapping.
Also add ww locking to begin/end cpu access.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 60 --
1
Use pin_pages_unlocked() where we don't have a lock.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
Instead of creating a separate object type, we make changes to
the shmem type, to clear struct page backing. This will allow us to
ensure we never run into a race when we exchange obj->ops with other
function pointers.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
Currently we have a lot of places where we hold the gem object lock,
but haven't yet been converted to the ww dance. Complain loudly about
those places.
i915_vma_pin shouldn't have the obj lock held, so we can do a ww dance,
while i915_vma_pin_ww should.
Signed-off-by: Maarten Lankhorst
We need to lock a few more objects, some temporarily,
add ww lock where needed.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/i915_perf.c | 56
1 file changed, 43 insertions(+), 13 deletions(-)
diff --git
Convert a single pin_pages call to use the unlocked version.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Now that unsynchronized mappings are removed, the only time userptr
works is when the MMU notifier is enabled. Put all of the userptr
code behind a mmu notifier ifdef.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +
We are removing obj->mm.lock, and need to take the reservation lock
before we can pin pages. Move the pinning pages into the helper, and
merge gtt pwrite/pread preparation and cleanup paths.
The fence lock is also removed; it will conflict with fence annotations,
because of memory allocations
Instead of force unbinding and rebinding every time, we try to check
if our notifier seqcount is still correct when pages are bound. This
way we only rebind userptr when we need to, and prevent stalls.
Changes since v1:
- Missing mutex_unlock, reported by kbuild.
Reported-by: kernel test robot
We can no longer call intel_timeline_pin with a null argument,
so add a ww loop that locks the backing object.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 30 +
1 file changed, 25 insertions(+), 5
From: Thomas Hellström
Stolen objects need to lock, and we may call put_pages when
refcount drops to 0, ensure all calls are handled correctly.
Changes since v1:
- Rebase on top of upstream changes.
Idea-from: Thomas Hellström
Signed-off-by: Maarten Lankhorst
Signed-off-by: Thomas Hellström
This should be done as part of the ww loop, in order to remove a
i915_vma_pin that needs ww held.
Now only i915_ggtt_pin() callers remaining.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/intel_gtt.c| 14 +-
Use some unlocked versions where we're not holding the ww lock.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
We need to lock the global gtt dma_resv, use i915_vm_lock_objects
to handle this correctly. Add ww handling for this where required.
Add the object lock around unpin/put pages, and use the unlocked
versions of pin_pages and pin_map where required.
Signed-off-by: Maarten Lankhorst
Reviewed-by:
On 25/01/2021 14:01, Chris Wilson wrote:
Replace the priolist rbtree with a skiplist. The crucial difference is
that walking and removing the first element of a skiplist is O(1), but
O(lgN) for an rbtree, as we need to rebalance on remove. This is a
hindrance for submission latency as it
On Thu, Jan 28, 2021 at 10:26 AM Maarten Lankhorst
wrote:
>
> There are a couple of ioctl's related to tiling and cache placement,
> that make no sense for userptr, reject those:
> - i915_gem_set_tiling_ioctl()
> Tiling should always be linear for userptr. Changing placement will
> fail
On Wed, 2021-01-27 at 20:21 -0800, Lucas De Marchi wrote:
> On Wed, Jan 27, 2021 at 08:54:01AM -0800, Jose Souza wrote:
> > DRAM information is required to properly program display.
> > Before "drm/i915/gen11+: Only load DRAM information from pcode" we
> > were failing driver load if unable to
We've never used this bit in mesa.
Acked-by: Jason Ekstrand
On Thu, Jan 28, 2021 at 10:26 AM Maarten Lankhorst
wrote:
>
> We should not allow this any more, as it will break with the new userptr
> implementation, it could still be made to work, but there's no point in
> doing so.
>
>
== Series Details ==
Series: drm/i915: Remove obj->mm.lock! (rev14)
URL : https://patchwork.freedesktop.org/series/82337/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: series starting with [1/5] drm/i915: Skip vswing programming for TBT
URL : https://patchwork.freedesktop.org/series/86402/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9694 -> Patchwork_19529
This series still willfully breaks ABI resulting in iris aborting among
others, introduces an unrecoverable dos, despite knowing how to avoid
both.It is unconscionable that this design was not revised to avoid
such breakage, after being rejected.
-Chris
== Series Details ==
Series: drm/i915: Remove obj->mm.lock! (rev14)
URL : https://patchwork.freedesktop.org/series/82337/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9695 -> Patchwork_19530
Summary
---
**FAILURE**
From: Ville Syrjälä
Reduce the copypasta by pulling the combo PHY lane
power up stuff into a helper. We'll have a third user soon.
Cc: sta...@vger.kernel.org
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 35 +---
1 file changed, 19
From: Ville Syrjälä
Currently we only explicitly power up the combo PHY lanes
for DP. The spec says we should do it for HDMI as well.
Cc: sta...@vger.kernel.org
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Ville Syrjälä
In thunderbolt mode the PHY is owned by the thunderbolt controller.
We are not supposed to touch it. So skip the vswing programming
as well (we already skipped the other steps not applicable to TBT).
Touching this stuff could supposedly interfere with the PHY
programming
From: Ville Syrjälä
The documented programming sequence indicates the correct point
for the vswing programming is just before we enable the DDI.
Make it so.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 30
1 file changed, 15
Valid, ranks and bandwidth_kbps are set into dram_info but are not
used anywhere else so nuking it.
Reviewed-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 4 +--
drivers/gpu/drm/i915/i915_drv.h | 3 --
drivers/gpu/drm/i915/intel_dram.c |
As it now it is always required for GEN12+ the is_16gb_dimm name
do not make sense for GEN12+.
v2:
- Updated comment on top of "dram_info->wm_lv_0_adjust_needed =
!IS_GEN9_LP(i915);"
Reviewed-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 2
Up to now we were reading some DRAM information from MCHBAR register
and from pcode what is already not good but some GEN12(TGL-H and ADL-S)
platforms have MCHBAR DRAM information in different offsets.
This was notified to HW team that decided that the best alternative is
always apply the
From: Ville Syrjälä
We shouldn't really trust tc_mode on non-TC PHYs since we never
initialize it explicitly. So let's check for the PHY type first.
Fortunately TC_PORT_TBT_ALT happens to be zero so I don't think
there's an actual bug here, just a possibility for a future one
if someone
Instead of sharing pages with breadcrumbs, give each timeline a
single page. This allows unrelated timelines not to share locks
any more during command submission.
As an additional benefit, seqno wraparound no longer requires
i915_vma_pin, which means we no longer need to worry about a
potential
1 - 100 of 147 matches
Mail list logo
