On Sat, 30 Jan 2021, Joe Perches wrote:
> On Mon, 2020-08-24 at 21:56 -0700, Joe Perches wrote:
>> Use semicolons and braces.
>
> Ping?
Seems to have fallen between the cracks.
The first two hunks have been fixed, the last two are still there. Care
to respin and rebase against drm-tip (or
On 01/02/2021 08:53, Chris Wilson wrote:
Hide inactive clients by pressing 'i' (toggle in interactive mode).
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
Quoting Jani Nikula (2021-01-28 13:23:48)
>
> A number of our CI systems are hitting redzone overwritten errors after
> s2idle, with the errors introduced between v5.11-rc4 and v5.11-rc5. See
> snippet below, full logs for one affected machine at [1].
>
> Known issue?
Fwiw, I think this should
On 01/02/2021 08:21, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2021-02-01 08:14:45)
On 31/01/2021 03:11, Chris Wilson wrote:
Keep new clients hidden until they utilise the GPU.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 5 -
1 file changed, 4
Hide inactive clients by pressing 'i' (toggle in interactive mode).
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 60ff62d28..edf0dedac 100644
---
Whether a scheduler chooses to implement timeslicing is up to it, and
not an underlying property of the HW engine. The scheduler does depend
on the HW supporting preemption.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine.h | 6 ++
Since finding the currently active request starts by walking the
scheduler lists under the scheduler lock, move the routine to the
scheduler.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine.h| 3 -
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 71 ++--
As a topological sort, we expect it to run in linear graph time,
O(V+E). In removing the recursion, it is no longer a DFS but rather a
BFS, and performs as O(VE). Let's demonstrate how bad this is with a few
examples, and build a few test cases to verify a potential fix.
Signed-off-by: Chris
The current implementation of walking the children of a deferred
requests lacks the backtracking required to reduce the dfs to linear.
Having pulled it from execlists into the common layer, we can reuse the
dfs code for priority inheritance.
Signed-off-by: Chris Wilson
---
Extract the scheduling queue from "execlists" into the per-engine
scheduling structs, for reuse by other backends.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_wait.c | 1 +
live_timeslice_rewind assumes a particular traversal and reordering
after the first timeslice yield. However, the outcome can be either
(A1, A2, B1) or (A1, B2, A2) depending on the path taken through the
dependency graph. So if we do not get the outcome we need at first, give
it a priority kick
Verify that context isolation is also preserved when accessing
context-local registers with relative-mmio commands.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 88 --
1 file changed, 67 insertions(+), 21 deletions(-)
diff --git
The name very often may be freed independently of the fence, with the
only protection being RCU. To be safe as we read the names, hold RCU.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_sw_fence.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
Make the ability to suspend and resume a request and its dependents
generic.
Signed-off-by: Chris Wilson
---
.../drm/i915/gt/intel_execlists_submission.c | 167 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 8 +-
drivers/gpu/drm/i915/i915_scheduler.c | 153
Start extracting the scheduling flags from the engine. We begin with its
own existence.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine.h| 6 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 21 +++
.../drm/i915/gt/intel_execlists_submission.c
Wrap the query on whether the backend engine supports us emitting
semaphores to coordinate multiple requests.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 2 +-
drivers/gpu/drm/i915/i915_request.h | 5 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git
A quick test to verify that the backend accepts each type of timeline
and can use them to track and control request emission.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 105
1 file changed, 105 insertions(+)
diff --git
As soon as we mark a request as completed, it may be retired. So when
cancelling a request and marking it complete, make sure we first keep a
reference to the request.
Signed-off-by: Chris Wilson
---
.../drm/i915/gt/intel_execlists_submission.c | 19 +++
We check for idle during debug prints and other debugging actions.
Simplify the flow by not touching execlists state.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git
Extract the scheduler lists into a related structure, stop sprawling
over struct intel_engine_cs. Also transfer the responsibility of tracing
the scheduler events from ENGINE_TRACE() to SCHED_TRACE().
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 8 +-
Since we setup the submission method for the engines once, it is easy to
assign an enum and use that instead of probing into the backends.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine.h | 8 +++-
drivers/gpu/drm/i915/gt/intel_engine_cs.c|
When we introduced the saturated workload detection to tell us to back
off from semaphore usage [semaphores have a noticeable impact on
contended bus cycles with the CPU for some heavy workloads], we first
introduced it as a per-context tracker. This allows individual contexts
to try and optimise
Lift the ability to defer a request until later from execlists into the
common layer.
Signed-off-by: Chris Wilson
---
.../drm/i915/gt/intel_execlists_submission.c | 57 +++--
drivers/gpu/drm/i915/i915_scheduler.c | 63 +--
As we are about to shuffle the lists around to consolidate new control
objects, reduce the code movement by wrapping access to the scheduler
lists ahead of time.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 17 +++---
Claim the submit_request vfunc as the entry point into the scheduler
backend for ready requests.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 8
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 11 ++-
Exercise rescheduling priority inheritance around a sequence of requests
that wrap around all the engines.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/selftests/i915_scheduler.c | 225 ++
1 file changed, 225 insertions(+)
diff --git
Move the scheduling tasklists out of the execlists backend into the
per-engine scheduling bookkeeping.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine.h| 33 +++-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 33 ++--
Re-enable secure dispatch for gen6/gen7, primarily to workaround the
command parser and overly zealous command validation on Haswell. For
example this prevents making accurate measurements using a journal for
store results from the GPU without CPU intervention.
Signed-off-by: Chris Wilson
---
This was removed in commit 478ffad6d690 ("drm/i915: drop
engine_pin/unpin_breadcrumbs_irq") as the last user had been removed,
but now there is a promise of a new user in the next patch.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 24
In the process of preparing to reuse the request submission logic for
other backends, lift it out of the execlists backend.
While this operates on the common structs, we do have a bit of backend
knowledge, which is harmless for !lrc but still unsightly.
Signed-off-by: Chris Wilson
---
In anticipation of wanting to be able to call pi from underneath an
engine's active.lock, rework the priority inheritance to primarily work
along an engine's priority queue, delegating any other engine that the
chain may traverse to a worker. This reduces the global spinlock from
governing the
Primarily to smooth over differences with the guc backend that struggles
with smaller quanta, bump the default timeslicing to 5ms from 1ms.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Kconfig.profile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
It appears that Elkhart Lake uses the same clock for CTX_TIMESTAMP as
CS_TIMESTAMP, leaving Icelake as the odd one out.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3024
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 2 +-
1 file changed, 1
Kick the scheduler to allow it to see the timeslice duration change,
don't peek into execlists.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/sysfs_engines.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c
To support legacy ring buffer scheduling, we want a virtual ringbuffer
for each client. These rings are purely for holding the requests as they
are being constructed on the CPU and never accessed by the GPU, so they
should not be bound into the GGTT, and we can use plain old WB mapped
pages.
As
Move the scheduler pretty printer from out of the execlists register
state to and push it to the schduler.
v2: It's not common to all, so shove it out of intel_engine_cs and
split it between scheduler front/back ends
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c
In the process of preparing to reuse the request submission logic for
other backends, lift it out of the execlists backend. It already
operates on the common structs, so just a matter of moving and renaming.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
Verify that one context running on engine A cannot manipulate another
client's context concurrently running on engine B using unprivileged
access.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 275 +
1 file changed, 238 insertions(+), 37
On 31/01/2021 03:11, Chris Wilson wrote:
Keep new clients hidden until they utilise the GPU.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
Quoting Tvrtko Ursulin (2021-02-01 08:14:45)
>
> On 31/01/2021 03:11, Chris Wilson wrote:
> > Keep new clients hidden until they utilise the GPU.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> > ---
> > tools/intel_gpu_top.c | 5 -
> > 1 file changed, 4 insertions(+), 1
Allow multiple requests to be queued unto a virtual engine, whereas
before we only allowed a single request to be queued at a time. The
advantage of keeping just one request in the queue was to ensure that we
always decided late which engine to use. However, with the introduction
of the virtual
As we know when we expect the heartbeat to be checked for completion,
pass this information along as its deadline. We still do not complain if
the deadline is missed, at least until we have tried a few times, but it
will allow for quicker hang detection on systems where deadlines are
adhered to.
Whether the scheduler depends on interrupt delivery for forward progress
is a property of the scheduler backend not of the underlying engine, so
move the flag from inside the engine to i915_sched_engine.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine.h| 6
Now that we no longer switch back and forth between guc and execlists,
we no longer need to restore the backend's vfunc and can leave them set
after initialisation. The only catch is that we lose the submission on
wedging and still need to reset the submit_request vfunc on unwedging.
The core of the scheduling algorithm is that we compute the topological
order of the fence DAG. Knowing that we have a DAG, we should be able to
use a DFS to compute the topological sort in linear time. However,
during the conversion of the recursive algorithm into an iterative one,
the
For a modeset/pageflip, there is a very precise deadline by which the
frame must be completed in order to hit the vblank and be shown. While
we don't pass along that exact information, we can at least inform the
scheduler that this request-chain needs to be completed asap.
Signed-off-by: Chris
If we allow for per-client timelines, even with legacy ring submission,
we open the door to a world full of possiblities [scheduling and
semaphores].
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 72 ++-
drivers/gpu/drm/i915/gt/gen2_engine_cs.h
Busy-waiting is used for preempt-to-busy by schedulers, if they so
choose. Since it is not a property of the engine, but that of the
submission backend, move the flag from out of the engine to
i915_sched_engine.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 4
A key prolem with legacy ring buffer submission is that it is an inheret
FIFO queue across all clients; if one blocks, they all block. A
scheduler allows us to avoid that limitation, and ensures that all
clients can submit in parallel, removing the resource contention of the
global ringbuffer.
When we are not using semaphores with a context/engine, we can simply
reuse the same seqno location across wraps, but we still require each
timeline to have its own address. For LRC submission, each context is
prefixed by a per-process HWSP, which provides us with a unique location
for each
The first "scheduler" was a topographical sorting of requests into
priority order. The execution order was deterministic, the earliest
submitted, highest priority request would be executed first. Priority
inheritance ensured that inversions were kept at bay, and allowed us to
dynamically boost
If any engine asks for the tasklet to be kicked from the CS interrupt,
do so. Currently, this is used by the execlists scheduler backends to
feed in the next request to the HW, and similarly could be used by a
ring scheduler, as will be seen in the next patch.
Signed-off-by: Chris Wilson
In preparation for removing the has_initial_breadcrumb field, add a
helper function for the existing callers.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c| 2 +-
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 4 ++--
Replace the priolist rbtree with a skiplist. The crucial difference is
that walking and removing the first element of a skiplist is O(1), but
O(lgN) for an rbtree, as we need to rebalance on remove. This is a
hindrance for submission latency as it occurs between picking a request
for the priolist
Explicitly differentiate between the absolute and relative timelines,
and the global HWSP and ppHWSP relative offsets. When using a timeline
that is relative to a known status page, we can replace the absolute
addressing in the commands with indexed variants.
Signed-off-by: Chris Wilson
Switch over from FIFO global submission to the priority-sorted
topographical scheduler. At the cost of more busy work on the CPU to
keep the GPU supplied with the next packet of requests, this allows us
to reorder requests around submission stalls and so allow low latency
under load while
Currently we know that the timeline status page is at most a page in
size, and so we can preserve the lower 12bits of the offset when
relocating the status page in the GGTT. If we want to use a larger
object, such as the context state, we may not necessarily use a position
within the first page
Build a bare bones scheduler to sit on top the global legacy ringbuffer
submission. This virtual execlists scheme should be applicable to all
older platforms.
A key problem we have with the legacy ring buffer submission is that it
only allows for FIFO queuing. All clients share the global request
While the HW may support preemption, whether or not the scheduler
enforces preemption by forcibly resetting the current context is
ultimately up to the scheduler.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine.h | 7 ++-
Before we take the irqsafe spinlock to dequeue requests and submit them
to HW, first do the check whether we need to take any action (i.e.
whether the HW is ready for some work, or if we need to preempt the
currently executing context) without taking the lock. We will then
likely skip taking the
Looking to the future, we want to set the scheduling attributes
explicitly and so replace the generic engine->schedule() with the more
direct i915_request_set_priority()
What it loses in removing the 'schedule' name from the function, it
gains in having an explicit entry point with a stated goal.
Relative timelines are relative to either the global or per-process
HWSP, and so we can replace the absolute addressing with store-index
variants for position invariance.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 98
Let userspace know if they can trust timeslicing by including it as part
of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING
v2: Only declare timeslicing if we can safely preempt userspace.
Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
Signed-off-by: Chris
Wrap cmpxchg64 with a try_cmpxchg()-esque helper. Hiding the old-value
dance in the helper allows for cleaner code.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_utils.h | 32 +++
1 file changed, 32 insertions(+)
diff --git
Quoting Tvrtko Ursulin (2021-02-01 08:36:04)
>
> On 01/02/2021 08:21, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2021-02-01 08:14:45)
> >>
> >> On 31/01/2021 03:11, Chris Wilson wrote:
> >>> Keep new clients hidden until they utilise the GPU.
> >>>
> >>> Signed-off-by: Chris Wilson
> >>>
Instead of copying the whole table to each category (mocs, l3cc), use a
single table with a pointer to it if the category is enabled.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_mocs.c | 32 +
1 file changed, 22 insertions(+), 10 deletions(-)
diff
On 01/02/2021 09:57, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2021-02-01 09:53:20)
On 01/02/2021 09:31, Chris Wilson wrote:
Hide inactive clients by pressing 'i' (toggle in interactive mode).
v2: Fix location of filter_idle.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by:
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Monday, February 1, 2021 4:25 PM
> To: Gupta, Anshuman ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/debugfs: HDCP capability enc NULL
> check
>
>
> On 1/29/2021 1:30 PM, Anshuman Gupta wrote:
From: Tvrtko Ursulin
Slight improvement with regards to wrapping header components to fit
console width. If a single element is wider than max it can still
overflow but it should now work better for practical console widths.
Signed-off-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 84
Reporting a port as connected if nothing is attached to them leads to
any i2c transactions on this port trying to use an uninitialized i2c
adapter, fix this.
Let's account for this case even if branch devices have no good reason
to report a port as unplugged with their peer device type set to
Quoting Tvrtko Ursulin (2021-02-01 11:57:56)
> From: Tvrtko Ursulin
>
> Slight improvement with regards to wrapping header components to fit
> console width. If a single element is wider than max it can still
> overflow but it should now work better for practical console widths.
<
On 01/02/2021 09:31, Chris Wilson wrote:
Hide inactive clients by pressing 'i' (toggle in interactive mode).
v2: Fix location of filter_idle.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 9 +
1 file changed, 9
Quoting Tvrtko Ursulin (2021-02-01 10:45:24)
> From: Tvrtko Ursulin
>
> Client stats refactoring broke the header layout with an extra newline.
Argh; keep the newline, or at least check the terminal width and make
the newline conditional.
-Chris
___
On Sat, Jan 30, 2021 at 9:45 AM Chris Wilson wrote:
>
> Quoting Vinicius Tinti (2021-01-30 12:34:11)
> > On Fri, Jan 29, 2021 at 08:55:54PM +, Chris Wilson wrote:
> > > Quoting Vinicius Tinti (2021-01-29 18:15:19)
> > > > By enabling -Wunreachable-code-aggressive on Clang the following code
>
Chris Wilson writes:
> Verify that context isolation is also preserved when accessing
> context-local registers with relative-mmio commands.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 88 --
> 1 file
On 1/29/21 2:11 PM, Maarten Lankhorst wrote:
In reloc_iomap we swallow the -EDEADLK error, but this needs to
be returned for -EDEADLK handling. Add the missing check to
make bsw pass again.
Testcase: gem_exec_fence.basic-await
Signed-off-by: Maarten Lankhorst
---
Quoting Maarten Lankhorst (2021-02-01 12:50:37)
> Make creation separate from pinning, in order to take the lock only
> once, and pin the mapping with the lock held.
>
> Changes since v1:
> - Rebase on top of upstream changes.
> Changes since v2:
> - Fully clear wa_ctx on error.
>
>
== Series Details ==
Series: series starting with [01/57] drm/i915/gt: Restrict the GT clock
override to just Icelake
URL : https://patchwork.freedesktop.org/series/86521/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit
On 2/1/21 1:50 PM, Maarten Lankhorst wrote:
Make creation separate from pinning, in order to take the lock only
once, and pin the mapping with the lock held.
Changes since v1:
- Rebase on top of upstream changes.
Changes since v2:
- Fully clear wa_ctx on error.
Signed-off-by: Maarten
== Series Details ==
Series: series starting with [01/57] drm/i915/gt: Restrict the GT clock
override to just Icelake
URL : https://patchwork.freedesktop.org/series/86521/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
02ff187efe58 drm/i915/gt: Restrict the GT clock override
Chris Wilson writes:
> It appears that Elkhart Lake uses the same clock for CTX_TIMESTAMP as
> CS_TIMESTAMP, leaving Icelake as the odd one out.
I am repeating myself: weird.
...but true.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3024
> Signed-off-by: Chris Wilson
Make creation separate from pinning, in order to take the lock only
once, and pin the mapping with the lock held.
Changes since v1:
- Rebase on top of upstream changes.
Changes since v2:
- Fully clear wa_ctx on error.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
== Series Details ==
Series: series starting with [01/57] drm/i915/gt: Restrict the GT clock
override to just Icelake
URL : https://patchwork.freedesktop.org/series/86521/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9712 -> Patchwork_19551
== Series Details ==
Series: drm/i915: Remove obj->mm.lock! (rev15)
URL : https://patchwork.freedesktop.org/series/82337/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Remove obj->mm.lock! (rev15)
URL : https://patchwork.freedesktop.org/series/82337/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter
or member 'ww'
== Series Details ==
Series: drm/i915/selftests: Use a single copy of the mocs table
URL : https://patchwork.freedesktop.org/series/86525/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9712 -> Patchwork_19552
Summary
On Thu, 2021-01-28 at 08:05 +, Patchwork wrote:
Patch Details
Series: Final set of patches for ADLS enabling (rev2)
URL:https://patchwork.freedesktop.org/series/86322/
State: success
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19525/index.html
CI Bug Log - changes
Chris Wilson writes:
> Verify that one context running on engine A cannot manipulate another
> client's context concurrently running on engine B using unprivileged
> access.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 275 +
> 1 file
== Series Details ==
Series: drm/i915: Remove obj->mm.lock! (rev15)
URL : https://patchwork.freedesktop.org/series/82337/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9712 -> Patchwork_19553
Summary
---
**FAILURE**
According to Bspec #20124, max link rate table for DP was updated
at BDB version 230. Max link rate can support upto UHBR.
After migrate to BDB v230, the definition for LBR, HBR2 and HBR3
were changed. For backward compatibility. If BDB version was
from 216 to 229. Driver have to follow original
We have not seen an occurrence of the false restart state recenty, and if
we did such an event from inside engine-reset, it would deadlock on
trying to suspend the tasklet to read the register state. Instead, we
inspect the context state before submission which will alert us to any
issues prior to
== Series Details ==
Series: drm/i915: Remove obj->mm.lock! (rev15)
URL : https://patchwork.freedesktop.org/series/82337/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7875c5f4807c drm/i915: Do not share hwsp across contexts any more, v7.
-:562: WARNING:CONSTANT_COMPARISON:
Hide inactive clients by pressing 'i' (toggle in interactive mode).
v2: Fix location of filter_idle.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/tools/intel_gpu_top.c
Quoting Tvrtko Ursulin (2021-02-01 09:53:20)
>
> On 01/02/2021 09:31, Chris Wilson wrote:
> > Hide inactive clients by pressing 'i' (toggle in interactive mode).
> >
> > v2: Fix location of filter_idle.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> > Reviewed-by: Tvrtko Ursulin
From: Tvrtko Ursulin
Document numeric busyness overlay and sort selection.
Signed-off-by: Tvrtko Ursulin
---
man/intel_gpu_top.rst | 2 ++
1 file changed, 2 insertions(+)
diff --git a/man/intel_gpu_top.rst b/man/intel_gpu_top.rst
index 35ab10da9bb4..b18fd9675bb7 100644
---
From: Tvrtko Ursulin
Allow hiding inactive clients (used no GPU time ever) in interactive mode
by pressing 'i'.
Signed-off-by: Tvrtko Ursulin
---
man/intel_gpu_top.rst | 1 +
tools/intel_gpu_top.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/man/intel_gpu_top.rst
From: Tvrtko Ursulin
Client stats refactoring broke the header layout with an extra newline.
Signed-off-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index
Quoting Tvrtko Ursulin (2021-02-01 10:45:22)
> From: Tvrtko Ursulin
>
> Document numeric busyness overlay and sort selection.
I looked for a 'h' or '?' screen.
Reviewed-by: Chris Wilson
-Chris
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Intel-gfx mailing list
On 1/29/2021 1:30 PM, Anshuman Gupta wrote:
DP-MST connector encoder initializes at modeset
Adding a connector->encoder NULL check in order to
avoid any NULL pointer dereference.
intel_hdcp_enable() already handle this but debugfs
can also invoke the intel_{hdcp,hdcp2_capable}.
Handling it
On Fri, 29 Jan 2021, Ville Syrjälä wrote:
> On Wed, Jan 27, 2021 at 10:45:34AM +0200, Jani Nikula wrote:
>> Make the child device details easier to read by turning this:
>>
>> [drm:parse_ddi_port [i915]] Port B VBT info: CRT:0 DVI:1 HDMI:1 DP:0 eDP:0
>> LSPCON:0 USB-Type-C:0 TBT:0 DSC:0
>>
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