== Series Details ==
Series: drm/i915/dg2: Tile 4 plane format support (rev2)
URL : https://patchwork.freedesktop.org/series/95715/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10797 -> Patchwork_21465
Summary
---
On 10/27/21 22:34, John Harrison wrote:
On 10/26/2021 23:36, Thomas Hellström wrote:
Hi, John,
On 10/26/21 21:55, John Harrison wrote:
On 10/21/2021 23:23, Thomas Hellström wrote:
On 10/21/21 22:37, Matthew Brost wrote:
On Thu, Oct 21, 2021 at 08:15:49AM +0200, Thomas Hellström wrote:
== Series Details ==
Series: series starting with [1/3] fbdev: rework FB_DDC dependencies
URL : https://patchwork.freedesktop.org/series/96343/
State : failure
== Summary ==
Applying: fbdev: rework FB_DDC dependencies
Applying: fbdev: rework backlight dependencies
error: sha1 information is
Should not be needed. Even with non-coherent display, we should be using
device local-memory there, and not system memory.
v2: also add a warning in i915_gem_clflush_object
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström #v1
---
On 2021-10-27 04:00, Pekka Paalanen wrote:
> On Tue, 26 Oct 2021 11:36:33 -0400
> Harry Wentland wrote:
>
>> On 2021-10-14 15:44, Shankar, Uma wrote:
>>>
>
...
>> FWIW, AMD HW (depending on generation) can do these operations
>> (in this order):
>>
>> 1) 1D LUT (fixed or PWL programmable)
On Wed, Oct 27, 2021 at 05:23:59PM +0100, Matthew Auld wrote:
On Wed, 27 Oct 2021 at 15:54, Lucas De Marchi wrote:
On Wed, Oct 27, 2021 at 08:57:48AM +0100, Matthew Auld wrote:
>On Thu, 21 Oct 2021 at 13:54, Matthew Auld wrote:
>>
>> wbinvd_on_all_cpus() is only defined on x86 it seems, plus
On 27/10/2021 11:52, Thomas Hellström wrote:
As we start to introduce asynchronous failsafe object migration,
where we update the object state and then submit asynchronous
commands we need to record what memory resources are actually used
by various part of the command stream. Initially for
On Wed, Oct 27, 2021 at 04:59:00PM +0300, Jani Nikula wrote:
> The PPS, RC_RANGE_PARAM, and RC_BUF_THRESH logging are clearly for
> debugging, and should not be info level messages.
>
> Signed-off-by: Jani Nikula
I think in the patch commit title there is a typo 'dcs' i think you meant
On 2021-10-27 at 18:46:53 +0300, Stanislav Lisovskiy wrote:
> TileF(Tile4 in bspec) format is 4K tile organized into
> 64B subtiles with same basic shape as for legacy TileY
> which will be supported by Display13.
>
> v2: - Fixed wrong case condition(Jani Nikula)
> - Increased
== Series Details ==
Series: drm/i915/psr2: Do full fetches when doing async flips
URL : https://patchwork.freedesktop.org/series/96357/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10799 -> Patchwork_21468
Summary
On Mon, Oct 18, 2021 at 02:50:25PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The amount of plane registers we have to write has been steadily
> increasing, putting more pressure on the vblank evasion mechanism
> and forcing us to increase its time budget. Let's try to take some
> of
== Series Details ==
Series: drm/i915/dcs: demote noisy drm_info() to drm_kms_dbg()
URL : https://patchwork.freedesktop.org/series/96344/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10797 -> Patchwork_21463
Summary
== Series Details ==
Series: drm/i915/dsc: Fix the usage of uncompressed bpp
URL : https://patchwork.freedesktop.org/series/96337/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10796_full -> Patchwork_21459_full
Summary
== Series Details ==
Series: series starting with [v2,1/4] drm/i915/clflush: fixup handling of
cache_dirty
URL : https://patchwork.freedesktop.org/series/96348/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10797 -> Patchwork_21466
Async flips are not supported by selective fetch and we had a check
for that but that check was only executed when doing modesets.
So moving this check to the page flip path, so it can be properly
handled.
This fix a failure in kms_async_flips@test-cursor.
Cc: Mika Kahola
Cc: Jouni Hogander
On Tue, Oct 26, 2021 at 02:58:00PM -0700, John Harrison wrote:
> On 10/20/2021 14:47, Matthew Brost wrote:
> > A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
> > execlists. Doing as little as possible to support this interface for
> > execlists - basically just passing
On Tue, Oct 26, 2021 at 05:48:21PM -0700, Umesh Nerlige Ramappa wrote:
> With GuC handling scheduling, i915 is not aware of the time that a
> context is scheduled in and out of the engine. Since i915 pmu relies on
> this info to provide engine busyness to the user, GuC shares this info
> with i915
On 10/26/2021 23:36, Thomas Hellström wrote:
Hi, John,
On 10/26/21 21:55, John Harrison wrote:
On 10/21/2021 23:23, Thomas Hellström wrote:
On 10/21/21 22:37, Matthew Brost wrote:
On Thu, Oct 21, 2021 at 08:15:49AM +0200, Thomas Hellström wrote:
Hi, Matthew,
On Mon, 2021-10-11 at 16:47
Details of the new features getting added as part of DG2 enabling and their
implicit impact on the uAPI.
v2: improvised the Flat-CCS documentation [Danvet & CQ]
Signed-off-by: Ramalingam C
cc: Daniel Vetter
cc: Matthew Auld
cc: Simon Ser
cc: Pekka Paalanen
Cc: Jordan Justen
Cc: Kenneth
== Series Details ==
Series: drm/i915/dg2: Enabling 64k page size and flat ccs (rev3)
URL : https://patchwork.freedesktop.org/series/95686/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
262eb27b8dcf drm/i915: Add has_64k_pages flag
e3f6866bf3b6 drm/i915/xehpsdv: set min
On Wed, Oct 27, 2021 at 06:46:53PM +0300, Stanislav Lisovskiy wrote:
> TileF(Tile4 in bspec) format is 4K tile organized into
> 64B subtiles with same basic shape as for legacy TileY
> which will be supported by Display13.
Is it supported on all D13 or only on DG2? Could you point to the bspec
== Series Details ==
Series: series starting with [v2,1/4] drm/i915/clflush: fixup handling of
cache_dirty
URL : https://patchwork.freedesktop.org/series/96348/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be
On 10/27/21 6:27 AM, Arnd Bergmann wrote:
From: Arnd Bergmann
Rather than having CONFIG_FB_BACKLIGHT select CONFIG_BACKLIGHT_CLASS_DEVICE,
make any driver that needs it have a dependency on the class device
being available, to prevent circular dependencies.
This is the same way that the
On Wed, Oct 27, 2021 at 01:04:49PM -0700, John Harrison wrote:
> On 10/27/2021 12:17, Matthew Brost wrote:
> > On Tue, Oct 26, 2021 at 02:58:00PM -0700, John Harrison wrote:
> > > On 10/20/2021 14:47, Matthew Brost wrote:
> > > > A weak implementation of parallel submission (multi-bb execbuf
== Series Details ==
Series: drm/i915/fb: Simplify modifier handling more (rev2)
URL : https://patchwork.freedesktop.org/series/96308/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10797_full -> Patchwork_21461_full
From: Matthew Auld
For local-memory objects we need to align the GTT addresses
to 64K, both for the ppgtt and ggtt.
We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into
From: Stuart Summers
Add a new platform flag, has_64k_pages, for platforms supporting
base page sizes of 64k.
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c
From: Matthew Auld
If the device needs 64K minimum GTT pages for device local-memory,
like on XEHPSDV, then we need to fail the allocation if we can't
meet it, instead of falling back to 4K pages, otherwise we can't
safely support the insertion of device local-memory pages for
this vm, since the
This series introduces the enabling patches for new memory compression
feature Flat CCS and 64k page support for i915 local memory, along with
documentation on the uAPI impact. Included the details of the feature and
the implications on the uAPI below. Which is also added into
From: Matthew Auld
LMEM should be allocated at 64K granularity, since 4K page support will
eventually be dropped for LMEM when using the PPGTT.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Reviewed-by: Lucas De
== Series Details ==
Series: i915/gem/dmabuf: add to fix build error
URL : https://patchwork.freedesktop.org/series/96360/
State : failure
== Summary ==
Applying: i915/gem/dmabuf: add to fix build error
error: sha1 information is lacking or useless
On Mon, Oct 18, 2021 at 02:50:26PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Chop skl_program_plane() into two halves. Fist half becomes
> the _noarm() variant, second part the _arm() variant.
>
> Fortunately I have already previously grouped the register
> writes into roughtly the
On Wed, Oct 27, 2021 at 03:23:16PM +0530, Vandita Kulkarni wrote:
> DP 1.4 spec limits max compression bpp to
> uncompressed bpp -1, which is supported from
> XELPD onwards.
> Instead of uncompressed bpp, max dsc input bpp
> was being used to limit the max compression bpp.
So the input Pipe BPP
This was for airlied to pull into drm-next
On Wed, 2021-10-27 at 09:18 +0200, Maxime Ripard wrote:
> Hi Lyude,
>
> On Mon, Oct 25, 2021 at 09:30:14PM -0400, Lyude Paul wrote:
> > topic/amdgpu-dp2.0-mst-2021-10-25:
> > UAPI Changes:
> > Nope!
> >
> > Cross-subsystem Changes:
> >
Hi,
On 10/27/21 15:38, Ville Syrjälä wrote:
> On Sun, Oct 24, 2021 at 05:50:10PM +0200, Hans de Goede wrote:
>> Add a NO_VLV_DISP_PW_DPIO_CMN_BC_INIT quirk to fix i915 not working on
>> the Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC).
>>
>> The Xiaomi Mi Pad 2 uses quite an unusual hardware-design
On 10/27/2021 12:17, Matthew Brost wrote:
On Tue, Oct 26, 2021 at 02:58:00PM -0700, John Harrison wrote:
On 10/20/2021 14:47, Matthew Brost wrote:
A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
execlists. Doing as little as possible to support this interface for
== Series Details ==
Series: drm/i915/adlp: Extend PSR2 support in transcoder B (rev2)
URL : https://patchwork.freedesktop.org/series/96321/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10798 -> Patchwork_21467
Summary
htinen
Cc: Rodrigo Vivi
Cc: intel-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c |1 +
1 file changed, 1 insertion(+)
--- linux-next-20211027.orig/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ linux-next-20211027/drivers/gpu/dr
From: Matt Roper
DG2 unifies render compression and media compression into a single
format for the first time. The programming and buffer layout is
supposed to match compression on older gen12 platforms, but the
actual compression algorithm is different from any previous platform; as
such, we
Documents the Flat-CCS feature and kernel handling required along with
modifiers used.
Signed-off-by: Ramalingam C
cc: Simon Ser
cc: Pekka Paalanen
Cc: Jordan Justen
Cc: Kenneth Graunke
Cc: mesa-...@lists.freedesktop.org
Cc: Tony Ye
Cc: Slawomir Milczarek
---
From: Anshuman Gupta
Handles the plane programing for flat ccs and clear color modifiers for
DG2
Signed-off-by: Anshuman Gupta
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Ramalingam C
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 3 +-
From: Stanislav Lisovskiy
TileF(Tile4 in bspec) format is 4K tile organized into
64B subtiles with same basic shape as for legacy TileY
which will be supported by Display13.
v2: - Fixed wrong case condition(Jani Nikula)
- Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
v3: -
From: Matthew Auld
On discrete platforms like DG2, we need to support a minimum page size
of 64K when dealing with device local-memory. This is quite tricky for
various reasons, so try to document the new implicit uapi for this.
v2: Fixed suggestions on formatting [Daniel]
Signed-off-by:
From: Matthew Auld
The basic idea is that each 2M block(page-table) has a color, depending
on if the page-table is occupied by LMEM objects(64K) or SMEM
objects(4K), where our goal is to prevent mixing 64K and 4K GTT pages in
the page-table, which is not supported by the HW.
Signed-off-by:
From: Ayaz A Siddiqui
Xe-hp and latest devices support Flat CCS which reserved a portion of
the device memory to store compression metadata, during the clearing of
device memory buffer object we also need to clear the associated CCS buffer.
Flat CCS memory can not be directly accessed by S/W.
From: Abdiel Janulgue
A portion of device memory is reserved for Flat CCS so usable
device memory will be reduced by size of Flat CCS. Size of
Flat CCS is specified in “XEHPSDV_FLAT_CCS_BASE_ADDR”.
So to get effective device memory we need to subtract
total device memory by Flat CCS memory size.
From: CQ Tang
Gen12+ devices support 3D surface (buffer) compression and various
compression formats. This is accomplished by an additional compression
control state (CCS) stored for each surface.
Gen 12 devices(TGL family and DG1) stores compression states in a separate
region of memory. It is
Remove the Y Tiling modifiers for DG2.
Signed-off-by: Ramalingam C
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_fb.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index
From: Matthew Auld
On some platforms the hw has dropped support for 4K GTT pages when
dealing with LMEM, and due to the design of 64K GTT pages in the hw, we
can only mark the *entire* page-table as operating in 64K GTT mode,
since the enable bit is still on the pde, and not the pte. And since
From: Matthew Auld
XEHPSDV optimises 64K GTT pages for local-memory, since everything
should be allocated at 64K granularity. We say goodbye to sparse
entries, and instead get a compact 256B page-table for 64K pages,
which should be more cache friendly. 4K pages for local-memory
are no longer
Move it next to its partner in crime; gpu_write_needs_clflush. For
better readability lets keep gpu vs cpu at least in the same file.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 12
On Wed, 27 Oct 2021 at 15:54, Lucas De Marchi wrote:
>
> On Wed, Oct 27, 2021 at 08:57:48AM +0100, Matthew Auld wrote:
> >On Thu, 21 Oct 2021 at 13:54, Matthew Auld wrote:
> >>
> >> wbinvd_on_all_cpus() is only defined on x86 it seems, plus we need to
> >> include asm/smp.h here.
> >>
> >>
== Series Details ==
Series: drm/i915: make array states static const (rev2)
URL : https://patchwork.freedesktop.org/series/94688/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10797 -> Patchwork_21464
Summary
---
PSR2 is supported in transcoder A and B on Alderlake-P.
v2:
- explicity checking for transcoder A and B to avoid invalid transcoder
BSpec: 49185
Reviewed-by: Jouni Högander # v1
Cc: Jani Nikula
Cc: Mika Kahola
Cc: Jouni Hogander
Signed-off-by: José Roberto de Souza
---
== Series Details ==
Series: Prepare error capture for asynchronous migration (rev2)
URL : https://patchwork.freedesktop.org/series/96281/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10796_full -> Patchwork_21460_full
In theory if clflush_work_create() somehow fails here, and we don't yet
have mm.pages populated then we end up resetting cache_dirty, which is
likely wrong, since that will potentially skip the flush-on-acquire, if
it was needed.
It looks like intel_user_framebuffer_dirty() can arrive here before
== Series Details ==
Series: drm/i915/fb: Simplify modifier handling more (rev2)
URL : https://patchwork.freedesktop.org/series/96308/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10797 -> Patchwork_21461
Summary
---
We seem to have an unfortunate issue where we arrive from:
i915_gem_object_flush_if_display+0x86/0xd0 [i915]
intel_user_framebuffer_dirty+0x1a/0x50 [i915]
drm_mode_dirtyfb_ioctl+0xfb/0x1b0
which can be before the pages are populated(and pinned for display), and
so
== Series Details ==
Series: drm/i915/dg2: Tile 4 plane format support (rev2)
URL : https://patchwork.freedesktop.org/series/95715/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b258619cd9e1 drm/i915/dg2: Tile 4 plane format support
-:168: WARNING:LINE_CONTINUATIONS: Avoid
== Series Details ==
Series: series starting with [v2,1/4] drm/i915/clflush: fixup handling of
cache_dirty
URL : https://patchwork.freedesktop.org/series/96348/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3f9f5df03650 drm/i915/clflush: fixup handling of cache_dirty
On Tue, Oct 26, 2021 at 05:48:20PM -0700, Umesh Nerlige Ramappa wrote:
> In preparation for GuC pmu stats, add a name to the execlists stats
> structure so that it can be differentiated from the GuC stats.
>
> Signed-off-by: Umesh Nerlige Ramappa
> ---
>
== Series Details ==
Series: drm/i915/dg2: Enabling 64k page size and flat ccs (rev3)
URL : https://patchwork.freedesktop.org/series/95686/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
== Series Details ==
Series: drm/i915/adlp: Extend PSR2 support in transcoder B (rev2)
URL : https://patchwork.freedesktop.org/series/96321/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10798_full -> Patchwork_21467_full
== Series Details ==
Series: drm/i915/dg2: Enabling 64k page size and flat ccs (rev3)
URL : https://patchwork.freedesktop.org/series/95686/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10799 -> Patchwork_21470
Summary
On Wed, 2021-10-27 at 10:48 +0100, Matthew Auld wrote:
> On Wed, 27 Oct 2021 at 10:44, Jani Nikula
> wrote:
> >
> > On Wed, 27 Oct 2021, Matthew Auld
> > wrote:
> > > On Wed, 27 Oct 2021 at 09:58, Jani Nikula
> > > wrote:
> > > >
> > > > On Wed, 27 Oct 2021, Matthew Auld
> > > > wrote:
> > >
> -Original Message-
> From: Navare, Manasi D
> Sent: Thursday, October 28, 2021 12:57 AM
> To: Kulkarni, Vandita
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> Subject: Re: [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
>
> On Wed, Oct 27, 2021 at 03:23:16PM +0530,
== Series Details ==
Series: drm/i915/psr2: Do full fetches when doing async flips
URL : https://patchwork.freedesktop.org/series/96357/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10799_full -> Patchwork_21468_full
== Series Details ==
Series: series starting with [v2,1/4] drm/i915/clflush: fixup handling of
cache_dirty
URL : https://patchwork.freedesktop.org/series/96348/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10797_full -> Patchwork_21466_full
== Series Details ==
Series: drm/i915/dcs: demote noisy drm_info() to drm_kms_dbg()
URL : https://patchwork.freedesktop.org/series/96344/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10797_full -> Patchwork_21463_full
== Series Details ==
Series: drm/i915: make array states static const (rev2)
URL : https://patchwork.freedesktop.org/series/94688/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10797_full -> Patchwork_21464_full
Summary
Hi "Thomas,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
drm/drm-next tegra-drm/drm/tegra/for-next airlied/drm-next v5.15-rc7
next-20211027]
[If your patch is ap
topic/amdgpu-dp2.0-mst-2021-10-27:
UAPI Changes:
Nope!
Cross-subsystem Changes:
drm_dp_update_payload_part1() takes a new argument for specifying what the
VCPI slot start is
Core Changes:
Make the DP MST helpers aware of the current starting VCPI slot/VCPI total
slot count...
Driver Changes:
On Wed, 2021-10-27 at 14:15 +0300, Joonas Lahtinen wrote:
+ Jani and Rodrigo in order to pick this to -fixes.
picked up to drm-intel-next-fixes.
thanks,
Rodrigo.
Quoting Patchwork (2021-10-27 13:31:33)
Patch Details
Series: drm/i915: Revert 'guc_id' from i915_request tracepoint
URL:
er to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Hi Patchwork,
I am not using git, therefore there is no ancestor information.
This patch applies to linux-next-20211027 (today where I am).
Can I jus
== Series Details ==
Series: drm/i915/dg2: Tile 4 plane format support (rev2)
URL : https://patchwork.freedesktop.org/series/95715/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10797_full -> Patchwork_21465_full
Summary
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/kmb/kmb_drv.c
between commit:
c026565fe9be ("drm/kmb: Enable alpha blended second plane")
from Linus' tree and commit:
099afadc533f ("drm/kmb: Enable support for framebuffer console")
from the
On Fri, Oct 08, 2021 at 02:56:26PM -0700, Matt Roper wrote:
From: Daniele Ceraolo Spurio
In coming patches we'll be doing the actual tile initialization between
these two uncore init phases.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
Hi Ville,
>
> On Mon, Oct 25, 2021 at 11:38:11PM -0700, Vivek Kasireddy wrote:
> > On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or
> > more framebuffers/scanout buffers results in only one that is mappable/
> > fenceable. Therefore, pageflipping between these 2 FBs where
On Fri, Oct 08, 2021 at 02:56:29PM -0700, Matt Roper wrote:
From: Tvrtko Ursulin
Add some basic plumbing to support more than one dynamically allocated
struct intel_gt. Up to four gts are supported in i915->gts[], with slot
zero shadowing the existing i915->gt to enable source compatibility
On Fri, Oct 08, 2021 at 02:56:25PM -0700, Matt Roper wrote:
From: Paulo Zanoni
We'll be adding multi-tile support soon; on multi-tile platforms
interrupts are per-tile and every tile has the full set of
interrupt registers.
In this commit we start passing intel_gt instead of dev_priv for the
Hi, John,
On 10/26/21 21:55, John Harrison wrote:
On 10/21/2021 23:23, Thomas Hellström wrote:
On 10/21/21 22:37, Matthew Brost wrote:
On Thu, Oct 21, 2021 at 08:15:49AM +0200, Thomas Hellström wrote:
Hi, Matthew,
On Mon, 2021-10-11 at 16:47 -0700, Matthew Brost wrote:
The hangcheck
Hi Ville,
Thanks for the patch and getting a unified approach for DP, HDMI and DFP
for YCbCr420 output.
I am trying to have 8k@60 YUV420 via an HDMI2.1 PCON, without having to
use PCONs Color conversion capability,
but running into different issues, and failing miserably. I think this
On Wed, 27 Oct 2021, Imre Deak wrote:
> On Tue, Oct 26, 2021 at 08:52:12PM +0300, Jani Nikula wrote:
>> AFAICT there are no intel_plane_caps references anywhere after this, and
>> it no longer looks like an enum, so perhaps it just shouldn't be an enum
>> anymore? Just make them macros?
>
> There
Quoting Matthew Brost (2021-10-26 18:51:17)
> On Tue, Oct 26, 2021 at 11:59:35AM +0300, Joonas Lahtinen wrote:
> > Quoting Matthew Brost (2021-10-25 18:15:09)
> > > On Mon, Oct 25, 2021 at 12:37:02PM +0300, Joonas Lahtinen wrote:
> > > > Quoting Matthew Brost (2021-10-22 19:42:19)
> > > > > On
On Fri, Oct 08, 2021 at 02:56:31PM -0700, Matt Roper wrote:
From: Paulo Zanoni
The first step of interrupt handling is to read a tile0 register that
tells us in which tile the interrupt happened; we can then we read the
usual interrupt registers from the appropriate tile.
Note that this is
Hi Lyude,
On Mon, Oct 25, 2021 at 09:30:14PM -0400, Lyude Paul wrote:
> topic/amdgpu-dp2.0-mst-2021-10-25:
> UAPI Changes:
> Nope!
>
> Cross-subsystem Changes:
> drm_dp_update_payload_part1() takes a new argument for specifying what the
> VCPI slot start is
>
> Core Changes:
> Make the DP MST
On Tue, 2021-10-26 at 15:33 -0700, José Roberto de Souza wrote:
> PSR2 is supported in transcoder A and B on Alderlake-P.
>
> BSpec: 49185
> Cc: Mika Kahola
> Cc: Jouni Hogander
> Signed-off-by: José Roberto de Souza
LGTM
Reviewed-by: Jouni Högander
> ---
>
On Tue, 26 Oct 2021, Lucas De Marchi wrote:
> On Wed, Oct 13, 2021 at 03:12:55PM +0300, Jani Nikula wrote:
>>On Fri, 08 Oct 2021, Matt Roper wrote:
>>> On a multi-tile platform, each tile has its own registers + GGTT space,
>>> and BAR 0 is extended to cover all of them. Upcoming patches will
On Wed, Oct 27, 2021 at 12:57:37PM +0530, Nautiyal, Ankit K wrote:
>
> On 10/15/2021 7:09 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > We lack sufficient state tracking to figure out whether
> > we want the DFP to perform the RGB->YCbCr conversion for us
> > or not. So currently we
On 10/15/2021 7:09 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Consolidate the double pfit call, and reorder things so that
intel_dp_output_format() and intel_dp_compute_link_config() are
back-to-back. They are intimately related, and will need to be
called twice to properly handle the
On Thu, 21 Oct 2021 at 13:54, Matthew Auld wrote:
>
> wbinvd_on_all_cpus() is only defined on x86 it seems, plus we need to
> include asm/smp.h here.
>
> Reported-by: kernel test robot
> Signed-off-by: Matthew Auld
> Cc: Thomas Hellström
Jani, would it make sense to cherry-pick this to
On Tue, 26 Oct 2021 11:02:31 -0400
Harry Wentland wrote:
> On 2021-10-12 17:01, Shankar, Uma wrote:
> >
> >
> >> -Original Message-
> >> From: Pekka Paalanen
> >> Sent: Tuesday, October 12, 2021 5:25 PM
> >> To: Shankar, Uma
> >> Cc: intel-gfx@lists.freedesktop.org;
On Wed, Oct 27, 2021 at 06:41:25AM +, Kasireddy, Vivek wrote:
> Hi Ville,
>
> >
> > On Mon, Oct 25, 2021 at 11:38:11PM -0700, Vivek Kasireddy wrote:
> > > On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or
> > > more framebuffers/scanout buffers results in only one that is
On Wed, 27 Oct 2021, Matthew Auld wrote:
> On Thu, 21 Oct 2021 at 13:54, Matthew Auld wrote:
>>
>> wbinvd_on_all_cpus() is only defined on x86 it seems, plus we need to
>> include asm/smp.h here.
>>
>> Reported-by: kernel test robot
>> Signed-off-by: Matthew Auld
>> Cc: Thomas Hellström
>
>
On Wed, 27 Oct 2021 at 09:58, Jani Nikula wrote:
>
> On Wed, 27 Oct 2021, Matthew Auld wrote:
> > On Thu, 21 Oct 2021 at 13:54, Matthew Auld wrote:
> >>
> >> wbinvd_on_all_cpus() is only defined on x86 it seems, plus we need to
> >> include asm/smp.h here.
> >>
> >> Reported-by: kernel test
On Wed, 27 Oct 2021 at 09:36, Thomas Hellström
wrote:
>
> GPU relocs are gone. There should be no need for this workaround anymore.
> Remove it.
>
> Signed-off-by: Thomas Hellström
I was completely wrong here, sorry. Digging through the git history it
looks like this came from:
Commit
On Tue, Oct 26, 2021 at 08:52:12PM +0300, Jani Nikula wrote:
> On Tue, 26 Oct 2021, Imre Deak wrote:
> > By using the modifier plane capability flags to encode the modifiers'
> > CCS type and tiling attributes, it becomes simpler to the check for
> > any of these capabilities when providing the
On Wed, Oct 13, 2021 at 03:12:55PM +0300, Jani Nikula wrote:
On Fri, 08 Oct 2021, Matt Roper wrote:
On a multi-tile platform, each tile has its own registers + GGTT space,
and BAR 0 is extended to cover all of them. Upcoming patches will start
exposing the tiles as multiple GTs within a
On 10/15/2021 7:09 PM, Ville Syrjala wrote:
From: Ville Syrjälä
We lack sufficient state tracking to figure out whether
we want the DFP to perform the RGB->YCbCr conversion for us
or not. So currently we are blindly just enabling that all the
time when supported by the DFP. That is nonsense.
On Tue, 26 Oct 2021 11:36:33 -0400
Harry Wentland wrote:
> On 2021-10-14 15:44, Shankar, Uma wrote:
> >
...
> > +
> > +* Plane CTM
> > + * This is a Property to program the color transformation
> > matrix.
>
> No mode property here? Is there any hardware
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