[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gem: Don't try to map and fence 8K/bigjoiner scanout buffers (rev3)

== Series Details == Series: drm/i915/gem: Don't try to map and fence 8K/bigjoiner scanout buffers (rev3) URL : https://patchwork.freedesktop.org/series/96279/ State : warning == Summary == $ dim checkpatch origin/drm-tip fd0a2abfb9d0 drm/i915/gem: Don't try to map and fence large scanout

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/8] drm/i915: Remove gen6_ppgtt_unpin_all

== Series Details == Series: series starting with [v3,1/8] drm/i915: Remove gen6_ppgtt_unpin_all URL : https://patchwork.freedesktop.org/series/96421/ State : warning == Summary == $ dim checkpatch origin/drm-tip 65fcc4f52c2d drm/i915: Remove gen6_ppgtt_unpin_all 49a476ed0c79 drm/i915: Create

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Don't try to map and fence 8K/bigjoiner scanout buffers (rev3)

== Series Details == Series: drm/i915/gem: Don't try to map and fence 8K/bigjoiner scanout buffers (rev3) URL : https://patchwork.freedesktop.org/series/96279/ State : success == Summary == CI Bug Log - changes from CI_DRM_10813 -> Patchwork_21487

Re: [Intel-gfx] [PATCH v3 1/3] drm: Rename lut check functions to lut channel checks

On Thu, Oct 28, 2021 at 11:03:54PM -0400, Mark Yacoub wrote: > On Thu, Oct 28, 2021 at 8:42 PM Sean Paul wrote: > > > > On Tue, Oct 26, 2021 at 03:21:00PM -0400, Mark Yacoub wrote: > > > From: Mark Yacoub > > > > > > [Why] > > > This function and enum do not do generic checking on the luts but

Re: [Intel-gfx] [PATCH v2] drm/i915/dmabuf: drop the flush on discrete

On 10/29/21 14:21, Matthew Auld wrote: We were overzealous here; even though discrete is non-LLC, it should still be always coherent. v2(Thomas & Daniel) - Be extra cautious and limit to DG1 - Add some more commentary Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Daniel Vetter

[Intel-gfx] [PATCH v3 7/8] drm/i915: Drain the ttm delayed workqueue too

From: Maarten Lankhorst Lets be thorough here. Users of the TTM backend would likely expect this behaviour. Signed-off-by: Maarten Lankhorst Reviewed-by: Matthew Auld Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/i915_drv.h | 1 + 1 file changed, 1 insertion(+) diff --git

[Intel-gfx] [PATCH v3 5/8] drm/i915: Remove resv from i915_vma

From: Maarten Lankhorst It's just an alias to vma->obj->base.resv, no need to duplicate it. Signed-off-by: Maarten Lankhorst Reviewed-by: Niranjana Vishwanathapura Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++-- drivers/gpu/drm/i915/i915_vma.c

[Intel-gfx] [PATCH v3 8/8] drm/i915: Require object lock when freeing pages during destruction

From: Maarten Lankhorst TTM already requires this, and we require it for delayed destroy. Signed-off-by: Maarten Lankhorst Reviewed-by: Matthew Auld Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/gem/i915_gem_object.c | 5 + 1 file changed, 5 insertions(+) diff --git

[Intel-gfx] [PATCH v3 6/8] drm/i915: Rework context handling in hugepages selftests

From: Maarten Lankhorst In the next commit, we don't evict when refcount = 0, so we need to call drain freed objects, because we want to pin new bo's in the same place, causing a test failure. Furthermore, since each subtest is separated, it's a lot better to use i915_live_selftests, so each

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Prepare error capture for asynchronous migration (rev5)

== Series Details == Series: Prepare error capture for asynchronous migration (rev5) URL : https://patchwork.freedesktop.org/series/96281/ State : warning == Summary == $ dim checkpatch origin/drm-tip 24b403667c6b drm/i915: Introduce refcounted sg-tables 46ad510d88a8 drm/i915: Update error

[Intel-gfx] ✓ Fi.CI.BAT: success for Prepare error capture for asynchronous migration (rev5)

== Series Details == Series: Prepare error capture for asynchronous migration (rev5) URL : https://patchwork.freedesktop.org/series/96281/ State : success == Summary == CI Bug Log - changes from CI_DRM_10813 -> Patchwork_21488 Summary

[Intel-gfx] [PATCH v2] drm/i915/dmabuf: drop the flush on discrete

We were overzealous here; even though discrete is non-LLC, it should still be always coherent. v2(Thomas & Daniel) - Be extra cautious and limit to DG1 - Add some more commentary Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Daniel Vetter ---

[Intel-gfx] ✗ Fi.CI.IGT: failure for Some fixes in HDMI2.1 PCON FRL configuration

== Series Details == Series: Some fixes in HDMI2.1 PCON FRL configuration URL : https://patchwork.freedesktop.org/series/96411/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10810_full -> Patchwork_21486_full Summary

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/8] drm/i915: Remove gen6_ppgtt_unpin_all

== Series Details == Series: series starting with [v3,1/8] drm/i915: Remove gen6_ppgtt_unpin_all URL : https://patchwork.freedesktop.org/series/96421/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10814 -> Patchwork_21489

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dmabuf: drop the flush on discrete

== Series Details == Series: drm/i915/dmabuf: drop the flush on discrete URL : https://patchwork.freedesktop.org/series/96426/ State : success == Summary == CI Bug Log - changes from CI_DRM_10814 -> Patchwork_21490 Summary ---

Re: [Intel-gfx] [PATCH v3 12/14] dt-bindings: msm/dp: Add bindings for HDCP registers

On Mon, Oct 04, 2021 at 02:58:41PM -0500, Bjorn Andersson wrote: > On Fri 01 Oct 10:11 CDT 2021, Sean Paul wrote: > > > From: Sean Paul > > > > This patch adds the bindings for the MSM DisplayPort HDCP registers > > which are required to write the HDCP key into the display controller as > >

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/fb: Simplify modifier handling more (rev2)

On Wed, Oct 27, 2021 at 08:51:45PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/fb: Simplify modifier handling more (rev2) > URL : https://patchwork.freedesktop.org/series/96308/ > State : success Thanks for the reviews, pushed to drm-intel-next. > > == Summary == > >

Re: [Intel-gfx] [PULL] topic/amdgpu-dp2.0-mst

On Fri, 29 Oct 2021, Jani Nikula wrote: > On Wed, 27 Oct 2021, Lyude Paul wrote: >> topic/amdgpu-dp2.0-mst-2021-10-27: >> UAPI Changes: >> Nope! >> >> Cross-subsystem Changes: >> drm_dp_update_payload_part1() takes a new argument for specifying what the >> VCPI slot start is >> >> Core Changes:

[Intel-gfx] [PATCH v3 1/8] drm/i915: Remove gen6_ppgtt_unpin_all

From: Maarten Lankhorst gen6_ppgtt_unpin_all is unused, kill it. Signed-off-by: Maarten Lankhorst Reviewed-by: Matthew Auld Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 11 --- drivers/gpu/drm/i915/gt/gen6_ppgtt.h | 1 - 2 files changed, 12 deletions(-)

[Intel-gfx] [PATCH v3 2/8] drm/i915: Create a dummy object for gen6 ppgtt

From: Maarten Lankhorst We currently have to special case vma->obj being NULL because of gen6 ppgtt and mock_engine. Fix gen6 ppgtt, so we may soon be able to remove a few checks. As the object only exists as a fake object pointing to ggtt, we have no backing storage, so no real object is

[Intel-gfx] [PATCH v3 3/8] drm/i915: Create a full object for mock_ring, v2.

From: Maarten Lankhorst This allows us to finally get rid of all the assumptions that vma->obj is NULL. Changes since v1: - Ensure the mock_ring vma is pinned to prevent a fault. - Pin it high to avoid failure in evict_for_vma selftest. Signed-off-by: Maarten Lankhorst Reviewed-by: Matthew

[Intel-gfx] [PATCH v3 4/8] drm/i915: vma is always backed by an object.

From: Maarten Lankhorst vma->obj and vma->resv are now never NULL, and some checks can be removed. Signed-off-by: Maarten Lankhorst Reviewed-by: Matthew Auld Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/gt/intel_context.c | 2 +- .../gpu/drm/i915/gt/intel_ring_submission.c

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/8] drm/i915: Remove gen6_ppgtt_unpin_all

== Series Details == Series: series starting with [v3,1/8] drm/i915: Remove gen6_ppgtt_unpin_all URL : https://patchwork.freedesktop.org/series/96421/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked

Re: [Intel-gfx] [PATCH v3 1/3] drm: Rename lut check functions to lut channel checks

On 2021-10-29 09:43, Sean Paul wrote: > On Thu, Oct 28, 2021 at 11:03:54PM -0400, Mark Yacoub wrote: >> On Thu, Oct 28, 2021 at 8:42 PM Sean Paul wrote: >>> >>> On Tue, Oct 26, 2021 at 03:21:00PM -0400, Mark Yacoub wrote: From: Mark Yacoub [Why] This function and enum do

Re: [Intel-gfx] [PATCH 4/7] drm/i915/adlp/fb: Fix remapping of linear CCS AUX surfaces

On Tue, 26 Oct 2021 at 23:51, Imre Deak wrote: > > During remapping CCS FBs the CCS AUX surface mapped size and offset->x,y > coordinate calculations assumed a tiled layout. This works as long as > the CCS surface height is aligned to 64 lines (ensuring a 4k bytes CCS > surface tile layout).

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/8] tests/i915/gem_exec_capture: Cope with larger page sizes

On Thu, Oct 21, 2021 at 04:40:38PM -0700, john.c.harri...@intel.com wrote: > From: John Harrison > > At some point, larger than 4KB page sizes were added to the i915 > driver. This included adding an informational line to the buffer > entries in error capture logs. However, the error capture

Re: [Intel-gfx] [PULL] topic/amdgpu-dp2.0-mst

JFYI - the wrapping was because of evolution, sorry about that. Going to make sure that gets fixed the next time I have to send out a topic branch On Fri, 2021-10-29 at 13:35 +0300, Jani Nikula wrote: > On Fri, 29 Oct 2021, Jani Nikula wrote: > > On Wed, 27 Oct 2021, Lyude Paul wrote: > > >

Re: [Intel-gfx] [PATCH] drm/i915/display: Check async flip state of every crtc and plane once

On Fri, 2021-10-29 at 09:24 +0300, Ville Syrjälä wrote: > On Thu, Oct 28, 2021 at 01:34:18PM -0700, José Roberto de Souza wrote: > > For every crtc in state, intel_atomic_check_async() was checking all > > the crtc and plane states again. > > > > Cc: Karthik B S > > Cc: Vandita Kulkarni > > Cc:

Re: [Intel-gfx] [PATCH] drm/i915/adlp: Implement workaround 16013190616

On Thu, Oct 28, 2021 at 04:04:49PM -0700, José Roberto de Souza wrote: > New workaround added to specification, requiring bit 15 of > GEN8_CHICKEN_DCPR_1 to be programed before power well 1 is enabled. > > BSpec: 54369 > Signed-off-by: José Roberto de Souza Reviewed-by: Imre Deak The spec

Re: [Intel-gfx] [PATCH] drm/i915/adlp: Implement workaround 16013190616

On Fri, Oct 29, 2021 at 05:58:22PM +0300, Imre Deak wrote: > On Thu, Oct 28, 2021 at 04:04:49PM -0700, José Roberto de Souza wrote: > > New workaround added to specification, requiring bit 15 of > > GEN8_CHICKEN_DCPR_1 to be programed before power well 1 is enabled. > > > > BSpec: 54369 > >

Re: [Intel-gfx] [PATCH 3/7] drm/i915/fb: Factor out functions to remap contiguous FB obj pages

On Tue, 26 Oct 2021 at 23:51, Imre Deak wrote: > > Factor out functions needed to map contiguous FB obj pages to a GTT/DPT > VMA view in the next patch. > > No functional changes. > > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/gt/intel_ggtt.c | 110 +++ > 1

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/4] drm/i915/clflush: fixup handling of cache_dirty (rev2)

Filed https://gitlab.freedesktop.org/drm/intel/-/issues/4412 and reported. igt@i915_hangman@engine-hang@vcs0 - incomplete - No warnings/errors Lakshmi. -Original Message- From: Auld, Matthew Sent: Friday, October 29, 2021 2:10 AM To: intel-gfx@lists.freedesktop.org; Vudum,

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/4] drm/i915/clflush: fixup handling of cache_dirty (rev2)

== Series Details == Series: series starting with [v2,1/4] drm/i915/clflush: fixup handling of cache_dirty (rev2) URL : https://patchwork.freedesktop.org/series/96348/ State : success == Summary == CI Bug Log - changes from CI_DRM_10805_full -> Patchwork_21471_full

Re: [Intel-gfx] [PATCH 3/7] drm/i915/fb: Factor out functions to remap contiguous FB obj pages

On Fri, Oct 29, 2021 at 05:26:05PM +0100, Matthew Auld wrote: > On Tue, 26 Oct 2021 at 23:51, Imre Deak wrote: > > > > Factor out functions needed to map contiguous FB obj pages to a GTT/DPT > > VMA view in the next patch. > > > > No functional changes. > > > > Signed-off-by: Imre Deak > > --- >

Re: [Intel-gfx] [PATCH 4/7] drm/i915/adlp/fb: Fix remapping of linear CCS AUX surfaces

On Fri, Oct 29, 2021 at 05:54:41PM +0100, Matthew Auld wrote: > On Tue, 26 Oct 2021 at 23:51, Imre Deak wrote: > > > > During remapping CCS FBs the CCS AUX surface mapped size and offset->x,y > > coordinate calculations assumed a tiled layout. This works as long as > > the CCS surface height is

[Intel-gfx] ✗ Fi.CI.IGT: failure for Prepare error capture for asynchronous migration (rev5)

== Series Details == Series: Prepare error capture for asynchronous migration (rev5) URL : https://patchwork.freedesktop.org/series/96281/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10813_full -> Patchwork_21488_full

Re: [Intel-gfx] [PATCH] drm/i915/display: Check async flip state of every crtc and plane once

On Fri, Oct 29, 2021 at 05:47:22PM +, Souza, Jose wrote: > On Fri, 2021-10-29 at 09:24 +0300, Ville Syrjälä wrote: > > On Thu, Oct 28, 2021 at 01:34:18PM -0700, José Roberto de Souza wrote: > > > For every crtc in state, intel_atomic_check_async() was checking all > > > the crtc and plane

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Don't request GMBUS to generate irqs when called while irqs are off

== Series Details == Series: series starting with [1/2] drm/i915: Don't request GMBUS to generate irqs when called while irqs are off URL : https://patchwork.freedesktop.org/series/96433/ State : warning == Summary == $ dim checkpatch origin/drm-tip c0d28b1ef5bf drm/i915: Don't request GMBUS

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for Selective fetch support for biplanar formats

On Fri, 2021-10-22 at 15:56 +, Patchwork wrote: Patch Details Series: Selective fetch support for biplanar formats URL:https://patchwork.freedesktop.org/series/96113/ State: success Details: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21401/index.html CI Bug Log - changes

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/adlp: Implement workaround 16013190616

On Fri, 2021-10-29 at 08:23 +, Patchwork wrote: Patch Details Series: drm/i915/adlp: Implement workaround 16013190616 URL:https://patchwork.freedesktop.org/series/96405/ State: failure Details: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21482/index.html CI Bug Log -

[Intel-gfx] [PATCH v2] drm/i915/display: Check async flip state of every crtc and plane once

For every crtc in state, intel_atomic_check_async() was checking all the crtc and plane states again. v2: comparing pipe ids instead of crtc pointers when iterating over planes Cc: Karthik B S Cc: Vandita Kulkarni Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza ---

Re: [Intel-gfx] [PATCH 2/2] Revert "drm/i915/display/psr: Do full fetch when handling multi-planar formats"

On Thu, 2021-10-21 at 13:10 +0300, Jouni Högander wrote: > This reverts commit 1f61f0655b95d5b89589390e6f83c4a61d9b1e8d. > > Now we are supporting selective fetch for biplanar formats. We can revert WA > patch which forced using full fetch for biplanar formats. > Reviewed-by: José Roberto de

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Don't request GMBUS to generate irqs when called while irqs are off

== Series Details == Series: series starting with [1/2] drm/i915: Don't request GMBUS to generate irqs when called while irqs are off URL : https://patchwork.freedesktop.org/series/96433/ State : success == Summary == CI Bug Log - changes from CI_DRM_10816 -> Patchwork_21491

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gem: Don't try to map and fence 8K/bigjoiner scanout buffers (rev3)

== Series Details == Series: drm/i915/gem: Don't try to map and fence 8K/bigjoiner scanout buffers (rev3) URL : https://patchwork.freedesktop.org/series/96279/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10813_full -> Patchwork_21487_full

[Intel-gfx] [PATCH 1/2] drm/i915: Don't request GMBUS to generate irqs when called while irqs are off

From: Ville Syrjälä We will need to do some i2c poking from the encoder->shutdown() hook. Currently that gets called after irqs have been turned off. We still poll the gmbus status bits even if the interrupt never arrives so things will work just fine. But seems like asking gmbus to generate

[Intel-gfx] [PATCH 2/2] drm/i915/hdmi: Turn DP++ TMDS output buffers back on in encoder->shutdown()

From: Ville Syrjälä Looks like our VBIOS/GOP generally fail to turn the DP dual mode adater TMDS output buffers back on after a reboot. This leads to a black screen after reboot if we turned the TMDS output buffers off prior to reboot. And if i915 decides to do a fastboot the black screen will

Re: [Intel-gfx] [PATCH 1/2] drm/i915/display: Add initial selective fetch support for biplanar formats

On Thu, 2021-10-21 at 13:10 +0300, Jouni Högander wrote: > Biplanar formats are using two planes (Y and UV). This patch adds handling > of Y selective fetch area by utilizing existing linked plane mechanism. > Also UV plane Y offset configuration is modified according to Bspec. > > Signed-off-by:

Re: [Intel-gfx] [PATCH 10/16] drm/i915: Query the vswing levels per-lane for tgl dkl phy

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Prepare for per-lane drive settings by querying the desired vswing > level per-lane. > > Note that the code only does two loops, with each one writing the > levels for two TX lanes. The register offsets also look

Re: [Intel-gfx] [PATCH 09/16] drm/i915: Query the vswing levels per-lane for icl mg phy

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Prepare for per-lane drive settings by querying the desired vswing > level per-lane. > > Note that the code only does two loops, with each one writing the > levels for two TX lanes. > > Signed-off-by: Ville

Re: [Intel-gfx] [PATCH 14/16] drm/i915: Use intel_de_rmw() for icl mg phy programming

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Streamline the code by using intel_de_rmw(). Some lines above 100 cols, other than that: Reviewed-by: José Roberto de Souza > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_ddi.c |

Re: [Intel-gfx] [PATCH 13/16] drm/i915: Use intel_de_rmw() for tgl dkl phy programming

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Streamline the code by using intel_de_rmw(). Reviewed-by: José Roberto de Souza > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 36 +++- > 1 file

[Intel-gfx] [PATCH] drm/i915/display: Exit PSR when doing async flips

Changing the buffer in the middle of the scanout then entering an period of flip idleness will cause part of the previous buffer being diplayed to user when PSR is enabled. So here disabling and scheduling activation after a few milliseconds when async flip is enabled in the state. The async

Re: [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips

On Fri, 2021-10-29 at 22:55 +, Souza, Jose wrote: > On Fri, 2021-10-29 at 09:22 +0300, Ville Syrjälä wrote: > > On Thu, Oct 28, 2021 at 08:18:48PM +, Souza, Jose wrote: > > > On Thu, 2021-10-28 at 20:46 +0300, Ville Syrjälä wrote: > > > > On Thu, Oct 28, 2021 at 05:43:51PM +, Souza,

Re: [Intel-gfx] [PATCH 08/16] drm/i915: Query the vswing levels per-lane for icl combo phy

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Prepare for per-lane drive settings by querying the desired vswing > level per-lane. > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++- > 1 file changed, 6

Re: [Intel-gfx] [PATCH 11/16] drm/i915: Query the vswing levels per-lane for snps phy

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Prepare for per-lane drive settings by querying the desired vswing > level per-lane. Reviewed-by: José Roberto de Souza > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_snps_phy.c |

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dmabuf: drop the flush on discrete

== Series Details == Series: drm/i915/dmabuf: drop the flush on discrete URL : https://patchwork.freedesktop.org/series/96426/ State : success == Summary == CI Bug Log - changes from CI_DRM_10814_full -> Patchwork_21490_full Summary

Re: [Intel-gfx] [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp

On Wed, Oct 27, 2021 at 09:37:10PM -0700, Kulkarni, Vandita wrote: > > -Original Message- > > From: Navare, Manasi D > > Sent: Thursday, October 28, 2021 12:57 AM > > To: Kulkarni, Vandita > > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani > > Subject: Re: [PATCH] drm/i915/dsc: Fix

Re: [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569

On Wed, 2021-10-27 at 17:55 +0300, Jani Nikula wrote: > On Wed, 27 Oct 2021, "Tolakanahalli Pradeep, Madhumitha" < > madhumitha.tolakanahalli.prad...@intel.com> wrote: > > On Mon, 2021-07-05 at 13:28 +0300, Jani Nikula wrote: > > > On Tue, 29 Jun 2021, "Souza, Jose" > > > wrote: > > > > On

Re: [Intel-gfx] [PATCH 07/16] drm/i915: Stop using group access when progrmming icl combo phy TX

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Program each TX lane individually so that we can start to use per-lane > drive settings. > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 28 ++-- > 1 file

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Check async flip state of every crtc and plane once (rev2)

== Series Details == Series: drm/i915/display: Check async flip state of every crtc and plane once (rev2) URL : https://patchwork.freedesktop.org/series/96402/ State : success == Summary == CI Bug Log - changes from CI_DRM_10817 -> Patchwork_21492

Re: [Intel-gfx] [PATCH 15/16] drm/i915: Use intel_de_rmw() for icl combo phy programming

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Streamline the code by using intel_de_rmw(). Reviewed-by: José Roberto de Souza > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 44 ++-- > 1 file

Re: [Intel-gfx] [PATCH 12/16] drm/i915: Enable per-lane drive settings for icl+

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Now that the link buf_trans, link training, and the > combo/mg/dkl/snps phy programming are all fixed up we can > allow per-lane DP drive settings on icl+. Make it so. Reviewed-by: José Roberto de Souza > >

Re: [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips

On Fri, 2021-10-29 at 09:22 +0300, Ville Syrjälä wrote: > On Thu, Oct 28, 2021 at 08:18:48PM +, Souza, Jose wrote: > > On Thu, 2021-10-28 at 20:46 +0300, Ville Syrjälä wrote: > > > On Thu, Oct 28, 2021 at 05:43:51PM +, Souza, Jose wrote: > > > > On Thu, 2021-10-28 at 20:38 +0300, Ville

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Don't request GMBUS to generate irqs when called while irqs are off

== Series Details == Series: series starting with [1/2] drm/i915: Don't request GMBUS to generate irqs when called while irqs are off URL : https://patchwork.freedesktop.org/series/96433/ State : success == Summary == CI Bug Log - changes from CI_DRM_10816_full -> Patchwork_21491_full

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/8] tests/i915/gem_exec_capture: Cope with larger page sizes

On 10/29/2021 10:39, Matthew Brost wrote: On Thu, Oct 21, 2021 at 04:40:38PM -0700, john.c.harri...@intel.com wrote: From: John Harrison At some point, larger than 4KB page sizes were added to the i915 driver. This included adding an informational line to the buffer entries in error capture

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Exit PSR when doing async flips

== Series Details == Series: drm/i915/display: Exit PSR when doing async flips URL : https://patchwork.freedesktop.org/series/96440/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10817 -> Patchwork_21493 Summary ---

Re: [Intel-gfx] [PATCH 2/2] drm/i915/pmu: Connect engine busyness stats from GuC to pmu

On Tue, Oct 26, 2021 at 05:48:21PM -0700, Umesh Nerlige Ramappa wrote: With GuC handling scheduling, i915 is not aware of the time that a context is scheduled in and out of the engine. Since i915 pmu relies on this info to provide engine busyness to the user, GuC shares this info with i915 for

[Intel-gfx] [PATCH v4 1/4] drm/i915: Introduce refcounted sg-tables

As we start to introduce asynchronous failsafe object migration, where we update the object state and then submit asynchronous commands we need to record what memory resources are actually used by various part of the command stream. Initially for three purposes: 1) Error capture. 2) Asynchronous

[Intel-gfx] [PATCH v4 0/4] Prepare error capture for asynchronous migration

This patch series prepares error capture for asynchronous migration, where the vma pages may not reflect the pages the GPU is currently executing from but may be several migrations ahead. The first patch deals with refcounting sg-list so that they don't disappear under the capture code, which

[Intel-gfx] [PATCH v4 2/4] drm/i915: Update error capture code to avoid using the current vma state

With asynchronous migrations, the vma state may be several migrations ahead of the state that matches the request we're capturing. Address that by introducing an i915_vma_snapshot structure that can be used to snapshot relevant state at request submission. In order to make sure we access the

[Intel-gfx] [PATCH v4 4/4] drm/i915: Initial introduction of vma resources

From: Thomas Hellström The vma resource are needed for asynchronous bind management and are similar to TTM resources. They contain the data needed for asynchronous unbinding (typically the vm range, any backend private information and a means to do refcounting and to hold the unbinding for error

[Intel-gfx] [PATCH v4 3/4] drm/i915: Use GFP_NOWAIT in the capture code

The capture code is typically run entirely in the fence signalling critical path. Recently added lockdep annotation reveals a lockdep splat similar to the below one. Fix the splats and the associated potential deadlocks using GFP_NOWAIT rather than GFP_KERNEL for memory allocation in the capture

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/adlp: Implement workaround 16013190616

== Series Details == Series: drm/i915/adlp: Implement workaround 16013190616 URL : https://patchwork.freedesktop.org/series/96405/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10809_full -> Patchwork_21482_full Summary

[Intel-gfx] [PATCH v2 08/10] drm/i915: Rework context handling in hugepages selftests

From: Maarten Lankhorst In the next commit, we don't evict when refcount = 0, so we need to call drain freed objects, because we want to pin new bo's in the same place, causing a test failure. Furthermore, since each subtest is separated, it's a lot better to use i915_live_selftests, so each

[Intel-gfx] [PATCH v2 06/10] drm/i915/pm: Move CONTEXT_VALID_BIT check

From: Maarten Lankhorst Resetting will clear the CONTEXT_VALID_BIT, so wait until after that to test. Signed-off-by: Maarten Lankhorst Reviewed-by: Niranjana Vishwanathapura Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/gt/intel_engine_pm.c | 5 +++-- 1 file changed, 3 insertions(+),

[Intel-gfx] [PATCH v2 03/10] drm/i915: Create a dummy object for gen6 ppgtt

From: Maarten Lankhorst We currently have to special case vma->obj being NULL because of gen6 ppgtt and mock_engine. Fix gen6 ppgtt, so we may soon be able to remove a few checks. As the object only exists as a fake object pointing to ggtt, we have no backing storage, so no real object is

[Intel-gfx] [PATCH v2 04/10] drm/i915: Create a full object for mock_ring, v2.

From: Maarten Lankhorst This allows us to finally get rid of all the assumptions that vma->obj is NULL. Changes since v1: - Ensure the mock_ring vma is pinned to prevent a fault. - Pin it high to avoid failure in evict_for_vma selftest. Signed-off-by: Maarten Lankhorst Reviewed-by: Matthew

[Intel-gfx] [PATCH v2 05/10] drm/i915: vma is always backed by an object.

From: Maarten Lankhorst vma->obj and vma->resv are now never NULL, and some checks can be removed. Signed-off-by: Maarten Lankhorst Reviewed-by: Matthew Auld Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/gt/intel_context.c | 2 +- .../gpu/drm/i915/gt/intel_ring_submission.c

[Intel-gfx] [PATCH v2 07/10] drm/i915: Remove resv from i915_vma

From: Maarten Lankhorst It's just an alias to vma->obj->base.resv, no need to duplicate it. Signed-off-by: Maarten Lankhorst Reviewed-by: Niranjana Vishwanathapura Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++-- drivers/gpu/drm/i915/i915_vma.c

[Intel-gfx] [PATCH v2 01/10] drm/i915: Remove unused bits of i915_vma/active api

From: Maarten Lankhorst When reworking the code to move the eviction fence to the object, the best code is removed code. Remove some functions that are unused, and change the function definition if it's only used in 1 place. Signed-off-by: Maarten Lankhorst Reviewed-by: Niranjana

[Intel-gfx] [PATCH v2 02/10] drm/i915: Remove gen6_ppgtt_unpin_all

From: Maarten Lankhorst gen6_ppgtt_unpin_all is unused, kill it. Signed-off-by: Maarten Lankhorst Reviewed-by: Matthew Auld Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 11 --- drivers/gpu/drm/i915/gt/gen6_ppgtt.h | 1 - 2 files changed, 12 deletions(-)

[Intel-gfx] [PATCH v2 10/10] drm/i915: Require object lock when freeing pages during destruction

From: Maarten Lankhorst TTM already requires this, and we require it for delayed destroy. Signed-off-by: Maarten Lankhorst Reviewed-by: Matthew Auld Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/gem/i915_gem_object.c | 5 + 1 file changed, 5 insertions(+) diff --git

[Intel-gfx] [PATCH v2 09/10] drm/i915: Drain the ttm delayed workqueue too

From: Maarten Lankhorst Lets be thorough here. Users of the TTM backend would likely expect this behaviour. Signed-off-by: Maarten Lankhorst Reviewed-by: Matthew Auld Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/i915_drv.h | 1 + 1 file changed, 1 insertion(+) diff --git

[Intel-gfx] [PATCH 0/2] Some fixes in HDMI2.1 PCON FRL configuration

Some optimizations in HDMI2.1 PCON configuration and avoiding resetting the config DPCD. Ankit Nautiyal (2): drm/i915/dp: Optimize the FRL configuration for HDMI2.1 PCON drm/i915/dp: For PCON TMDS mode set only the relavant bits in config DPCD drivers/gpu/drm/i915/display/intel_dp.c |

[Intel-gfx] [PATCH 1/2] drm/i915/dp: Optimize the FRL configuration for HDMI2.1 PCON

Currently the HDMI2.1 PCON's frl link config DPCD registers are reset and configured even if they are already configured. Also the HDMI Link Mode does not settle to FRL MODE immediately after HDMI Link Status is active. This patch: -Checks if the PCON is already configured for FRL. -Include HDMI

[Intel-gfx] [PATCH 2/2] drm/i915/dp: For PCON TMDS mode set only the relavant bits in config DPCD

Currently we reset the whole PCON linkConfig DPCD to set the TMDS mode. This also resets the Source control bit and HDMI link enable bit and goes to autonomous mode of operation, which is seen to spoil the PCONs internal state. This patch avoids resetting the PCON link config register and sets

Re: [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips

On Thu, Oct 28, 2021 at 08:18:48PM +, Souza, Jose wrote: > On Thu, 2021-10-28 at 20:46 +0300, Ville Syrjälä wrote: > > On Thu, Oct 28, 2021 at 05:43:51PM +, Souza, Jose wrote: > > > On Thu, 2021-10-28 at 20:38 +0300, Ville Syrjälä wrote: > > > > On Thu, Oct 28, 2021 at 05:02:41PM +,

Re: [Intel-gfx] [PATCH] drm/i915/display: Check async flip state of every crtc and plane once

On Thu, Oct 28, 2021 at 01:34:18PM -0700, José Roberto de Souza wrote: > For every crtc in state, intel_atomic_check_async() was checking all > the crtc and plane states again. > > Cc: Karthik B S > Cc: Vandita Kulkarni > Cc: Ville Syrjälä > Signed-off-by: José Roberto de Souza > --- >

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Check async flip state of every crtc and plane once

== Series Details == Series: drm/i915/display: Check async flip state of every crtc and plane once URL : https://patchwork.freedesktop.org/series/96402/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10809_full -> Patchwork_21480_full

Re: [Intel-gfx] [PATCH v3 2/3] drm/i915: Update error capture code to avoid using the current vma state

On 10/29/21 00:55, Matthew Brost wrote: On Thu, Oct 28, 2021 at 02:01:27PM +0200, Thomas Hellström wrote: With asynchronous migrations, the vma state may be several migrations ahead of the state that matches the request we're capturing. Address that by introducing an i915_vma_snapshot

Re: [Intel-gfx] [PATCH v3 2/3] drm: Add Gamma and Degamma LUT sizes props to drm_crtc to validate.

Dear Mark, On 26.10.21 21:21, Mark Yacoub wrote: From: Mark Yacoub [Why] 1. drm_atomic_helper_check doesn't check for the LUT sizes of either Gamma or Degamma props in the new CRTC state, allowing any invalid size to be passed on. 2. Each driver has its own LUT size, which could also be

[Intel-gfx] ✗ Fi.CI.IGT: failure for Prepare error capture for asynchronous migration (rev4)

== Series Details == Series: Prepare error capture for asynchronous migration (rev4) URL : https://patchwork.freedesktop.org/series/96281/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10809_full -> Patchwork_21481_full

[Intel-gfx] ✓ Fi.CI.BAT: success for Some fixes in HDMI2.1 PCON FRL configuration

== Series Details == Series: Some fixes in HDMI2.1 PCON FRL configuration URL : https://patchwork.freedesktop.org/series/96411/ State : success == Summary == CI Bug Log - changes from CI_DRM_10810 -> Patchwork_21486 Summary ---

Re: [Intel-gfx] linux-next: manual merge of the char-misc tree with the drm-intel tree

On Thu, Oct 28, 2021 at 06:27:53PM +1100, Stephen Rothwell wrote: > Hi all, > > Today's linux-next merge of the char-misc tree got a conflict in: > > drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c > > between commit: > > 5740211ea442 ("drm/i915/dmabuf: fix broken build") > > from the

[Intel-gfx] [PATCH] drm/i915/gem: Don't try to map and fence large scanout buffers (v3)

On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or more framebuffers/scanout buffers results in only one that is mappable/ fenceable. Therefore, pageflipping between these 2 FBs where only one is mappable/fenceable creates latencies large enough to miss alternate vblanks thereby

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/4] drm/i915/clflush: fixup handling of cache_dirty (rev2)

On 28/10/2021 13:57, Patchwork wrote: *Patch Details* *Series:* series starting with [v2,1/4] drm/i915/clflush: fixup handling of cache_dirty (rev2) *URL:* https://patchwork.freedesktop.org/series/96348/ *State:*failure *Details:*

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/resets: Don't set / test for per-engine reset bits with GuC submission

== Series Details == Series: drm/i915/resets: Don't set / test for per-engine reset bits with GuC submission URL : https://patchwork.freedesktop.org/series/96406/ State : success == Summary == CI Bug Log - changes from CI_DRM_10809_full -> Patchwork_21483_full

[Intel-gfx] ✓ Fi.CI.IGT: success for i915: Initial multi-tile support (rev3)

== Series Details == Series: i915: Initial multi-tile support (rev3) URL : https://patchwork.freedesktop.org/series/95631/ State : success == Summary == CI Bug Log - changes from CI_DRM_10809_full -> Patchwork_21485_full Summary ---

Re: [Intel-gfx] [PULL] topic/amdgpu-dp2.0-mst

On Wed, 27 Oct 2021, Lyude Paul wrote: > topic/amdgpu-dp2.0-mst-2021-10-27: > UAPI Changes: > Nope! > > Cross-subsystem Changes: > drm_dp_update_payload_part1() takes a new argument for specifying what the > VCPI slot start is > > Core Changes: > Make the DP MST helpers aware of the current