[Intel-gfx] [PATCH 0/4] Async flip optimization for DG2
Limitting the WM levels to 0 for DG2 during async flips, allows to slightly increase the performance, as recommended by HW team. Stanislav Lisovskiy (4): drm/i915: Pass plane to watermark calculation functions drm/i915: Introduce do_async_flip flag to intel_plane_state drm/i915: Use wm0 only during async flips for DG2 drm/i915: Don't allocate extra ddb during async flip for DG2 .../gpu/drm/i915/display/intel_atomic_plane.c | 5 +- .../gpu/drm/i915/display/intel_atomic_plane.h | 4 +- drivers/gpu/drm/i915/display/intel_display.c | 31 ++- .../drm/i915/display/intel_display_types.h| 3 + drivers/gpu/drm/i915/intel_pm.c | 83 ++- 5 files changed, 102 insertions(+), 24 deletions(-) -- 2.24.1.485.gad05a3d8e5
[Intel-gfx] [PATCH 1/4] drm/i915: Pass plane to watermark calculation functions
Sometimes we might need to change the way we calculate
watermarks, based on which particular plane it is calculated
for. Thus it would be convenient to pass plane struct to those
functions.
v2: Pass plane instead of plane_id
v3: Do not pass plane to skl_cursor_allocation(Ville Syrjälä)
v4: - Make intel_crtc_get_plane static again(Ville Syrjälä)
- s/cursor_plane/plane(Ville Syrjälä)
- Pass plane to skl_compute_wm_* instead of plane_id(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
.../gpu/drm/i915/display/intel_atomic_plane.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 37 +++
2 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 7907f601598e..ead789709477 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -16,6 +16,7 @@ struct intel_crtc;
struct intel_crtc_state;
struct intel_plane;
struct intel_plane_state;
+enum plane_id;
unsigned int intel_adjusted_rate(const struct drm_rect *src,
const struct drm_rect *dst,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2ec8e48806b6..06707d2b5fc5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4240,7 +4240,9 @@ static int skl_compute_wm_params(const struct
intel_crtc_state *crtc_state,
u64 modifier, unsigned int rotation,
u32 plane_pixel_rate, struct skl_wm_params *wp,
int color_plane);
+
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
+struct intel_plane *plane,
int level,
unsigned int latency,
const struct skl_wm_params *wp,
@@ -4251,6 +4253,7 @@ static unsigned int
skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
int num_active)
{
+ struct intel_plane *plane =
to_intel_plane(crtc_state->uapi.crtc->cursor);
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
struct skl_wm_level wm = {};
@@ -4267,7 +4270,7 @@ skl_cursor_allocation(const struct intel_crtc_state
*crtc_state,
for (level = 0; level <= max_level; level++) {
unsigned int latency = dev_priv->wm.skl_latency[level];
- skl_compute_plane_wm(crtc_state, level, latency, , , );
+ skl_compute_plane_wm(crtc_state, plane, level, latency, ,
, );
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -5495,6 +5498,7 @@ static int skl_wm_max_lines(struct drm_i915_private
*dev_priv)
}
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
+struct intel_plane *plane,
int level,
unsigned int latency,
const struct skl_wm_params *wp,
@@ -5622,6 +5626,7 @@ static void skl_compute_plane_wm(const struct
intel_crtc_state *crtc_state,
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
+ struct intel_plane *plane,
const struct skl_wm_params *wm_params,
struct skl_wm_level *levels)
{
@@ -5633,7 +5638,7 @@ skl_compute_wm_levels(const struct intel_crtc_state
*crtc_state,
struct skl_wm_level *result = [level];
unsigned int latency = dev_priv->wm.skl_latency[level];
- skl_compute_plane_wm(crtc_state, level, latency,
+ skl_compute_plane_wm(crtc_state, plane, level, latency,
wm_params, result_prev, result);
result_prev = result;
@@ -5641,6 +5646,7 @@ skl_compute_wm_levels(const struct intel_crtc_state
*crtc_state,
}
static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
+ struct intel_plane *plane,
const struct skl_wm_params *wm_params,
struct skl_plane_wm *plane_wm)
{
@@ -5649,7 +5655,7 @@ static void tgl_compute_sagv_wm(const struct
intel_crtc_state *crtc_state,
struct skl_wm_level *levels = plane_wm->wm;
unsigned int latency = dev_priv->wm.skl_latency[0] +
dev_priv->sagv_block_time_us;
- skl_compute_plane_wm(crtc_state, 0, latency,
+ skl_compute_plane_wm(crtc_state, plane, 0, latency,
wm_params, [0],
sagv_wm);
}
@@ -5719,11 +5725,11 @@ static void skl_compute_transition_wm(struct
drm_i915_private *dev_priv,
static int
[Intel-gfx] [PATCH 2/4] drm/i915: Introduce do_async_flip flag to intel_plane_state
There might be various logical contructs when we might want
to enable async flip, so lets calculate those and set this
flag, so that there is no need in long conditions in other
places.
v2: - Set do_async_flip flag to False, if no async flip needed.
Lets not rely that it will be 0-initialized, but set
explicitly, so that the logic is clear as well.
v3: - Clear do_async_flip in intel_plane_duplicate_state(Ville Syrjälä)
- Check with do_async_flip also when calling
intel_crtc_{enable,disable}_flip_done(Ville Syrjälä)
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index c2c512cd8ec0..b20cf2c16691 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -109,6 +109,7 @@ intel_plane_duplicate_state(struct drm_plane *plane)
intel_state->ggtt_vma = NULL;
intel_state->dpt_vma = NULL;
intel_state->flags = 0;
+ intel_state->do_async_flip = false;
/* add reference to fb */
if (intel_state->hw.fb)
@@ -491,7 +492,7 @@ void intel_plane_update_arm(struct intel_plane *plane,
trace_intel_plane_update_arm(>base, crtc);
- if (crtc_state->uapi.async_flip && plane->async_flip)
+ if (plane_state->do_async_flip)
plane->async_flip(plane, crtc_state, plane_state, true);
else
plane->update_arm(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0964b2403e2d..a65bae1f0c35 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1369,7 +1369,8 @@ static void intel_crtc_enable_flip_done(struct
intel_atomic_state *state,
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
if (plane->enable_flip_done &&
plane->pipe == crtc->pipe &&
- update_planes & BIT(plane->id))
+ update_planes & BIT(plane->id) &&
+ plane_state->do_async_flip)
plane->enable_flip_done(plane);
}
}
@@ -1387,7 +1388,8 @@ static void intel_crtc_disable_flip_done(struct
intel_atomic_state *state,
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
if (plane->disable_flip_done &&
plane->pipe == crtc->pipe &&
- update_planes & BIT(plane->id))
+ update_planes & BIT(plane->id) &&
+ plane_state->do_async_flip)
plane->disable_flip_done(plane);
}
}
@@ -5027,6 +5029,9 @@ int intel_plane_atomic_calc_changes(const struct
intel_crtc_state *old_crtc_stat
needs_scaling(new_plane_state
new_crtc_state->disable_lp_wm = true;
+ if (new_crtc_state->uapi.async_flip && plane->async_flip)
+ new_plane_state->do_async_flip = true;
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 41e3dd25a78f..6b107872ad39 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -634,6 +634,9 @@ struct intel_plane_state {
struct intel_fb_view view;
+ /* Indicates if async flip is required */
+ bool do_async_flip;
+
/* Plane pxp decryption state */
bool decrypt;
--
2.24.1.485.gad05a3d8e5
[Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
In terms of async flip optimization we don't to allocate
extra ddb space, so lets skip it.
v2: - Extracted min ddb async flip check to separate function
(Ville Syrjälä)
- Used this function to prevent false positive WARN
to be triggered(Ville Syrjälä)
v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
it more universal.
- Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
- Use rate = 0 instead of just setting extra = 0, thus
letting other planes to use extra ddb and avoiding WARN
(Ville Syrjälä)
v4: - Renamed needs_min_ddb as s/needs/use/ to match
the wm0 counterpart(Ville Syrjälä)
- Added plane->async_flip check to use_min_ddb(now
passing plane as a parameter to do that)(Ville Syrjälä)
- Account for use_min_ddb also when calculating total data rate
(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 +-
drivers/gpu/drm/i915/intel_pm.c | 53 ++-
3 files changed, 44 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index b20cf2c16691..9d79ab987b2e 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -374,7 +374,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
old_plane_state,
new_plane_state);
}
-static struct intel_plane *
+struct intel_plane *
intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index ead789709477..aaddcc636f98 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -23,7 +23,8 @@ unsigned int intel_adjusted_rate(const struct drm_rect *src,
unsigned int rate);
unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state
*plane_state);
-
+struct intel_plane *intel_crtc_get_plane(struct intel_crtc *crtc,
+ enum plane_id plane_id);
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8269f1e9c784..fbe6a45801bc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4988,6 +4988,25 @@ skl_get_total_relative_data_rate(struct
intel_atomic_state *state,
return total_data_rate;
}
+static bool use_min_ddb(struct intel_crtc_state *crtc_state,
+ struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ return DISPLAY_VER(i915) >= 13 && crtc_state->uapi.async_flip &&
+ plane->async_flip;
+}
+
+static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
+struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ return DISPLAY_VER(i915) >= 13 &&
+ crtc_state->uapi.async_flip &&
+ plane->async_flip;
+}
+
static u64
icl_get_total_relative_data_rate(struct intel_atomic_state *state,
struct intel_crtc *crtc)
@@ -5033,8 +5052,15 @@ icl_get_total_relative_data_rate(struct
intel_atomic_state *state,
}
}
- for_each_plane_id_on_crtc(crtc, plane_id)
- total_data_rate += crtc_state->plane_data_rate[plane_id];
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ /*
+* We calculate extra ddb based on ratio plane rate/total data
rate
+* in case, in some cases we should not allocate extra ddb for
the plane,
+* so do not count its data rate, if this is the case.
+*/
+ if (!use_min_ddb(crtc_state, plane))
+ total_data_rate +=
crtc_state->plane_data_rate[plane->id];
+ }
return total_data_rate;
}
@@ -5199,6 +5225,8 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
for_each_plane_id_on_crtc(crtc, plane_id) {
const struct skl_plane_wm *wm =
_state->wm.skl.optimal.planes[plane_id];
+ struct intel_plane *plane =
+ intel_crtc_get_plane(crtc, plane_id);
u64 rate;
u16
[Intel-gfx] [PATCH 3/4] drm/i915: Use wm0 only during async flips for DG2
This optimization allows to achieve higher perfomance
during async flips.
For the first async flip we have to still temporarily
switch to sync flip, in order to reprogram plane
watermarks, so this requires taking into account
old plane state's do_async_flip flag.
v2: - Removed redundant new_plane_state->do_async_flip
check from needs_async_flip_wm_override condition
(Ville Syrjälä)
- Extract dg2_async_flip_optimization to separate
function(Ville Syrjälä)
- Check for plane->async_flip instead of plane_id
(Ville Syrjälä)
v3: - Rename "needs_async_flip_wm_override" to
"intel_plane_do_async_flip" and move all the required
checks there (Ville Syrjälä)
- Rename "dg2_async_flip_optimization" to
"use_minimal_wm0_only" (Ville Syrjälä)
v4: - Swap new/old_crtc_state in intel_plane_do_async_flip
argument list(Ville Syrjälä)
- Use plane->base.dev to grab i915 pointer in
intel_plane_do_async_flip(Ville Syrjälä)
- Remove const modifier from plane parameter in
use_minimal_wm0_only(Ville Syrjälä)
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 24 +++-
drivers/gpu/drm/i915/intel_pm.c | 13 ++-
2 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a65bae1f0c35..d4ba6c2910fc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4910,6 +4910,28 @@ static bool needs_scaling(const struct intel_plane_state
*state)
return (src_w != dst_w || src_h != dst_h);
}
+static bool intel_plane_do_async_flip(struct intel_plane *plane,
+ const struct intel_crtc_state
*old_crtc_state,
+ const struct intel_crtc_state
*new_crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ if (!plane->async_flip)
+ return false;
+
+ if (!new_crtc_state->uapi.async_flip)
+ return false;
+
+ /*
+* In platforms after DISPLAY13, we might need to override
+* first async flip in order to change watermark levels
+* as part of optimization.
+* So for those, we are checking if this is a first async flip.
+* For platforms earlier than DISPLAY13 we always do async flip.
+*/
+ return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
+}
+
int intel_plane_atomic_calc_changes(const struct intel_crtc_state
*old_crtc_state,
struct intel_crtc_state *new_crtc_state,
const struct intel_plane_state
*old_plane_state,
@@ -5029,7 +5051,7 @@ int intel_plane_atomic_calc_changes(const struct
intel_crtc_state *old_crtc_stat
needs_scaling(new_plane_state
new_crtc_state->disable_lp_wm = true;
- if (new_crtc_state->uapi.async_flip && plane->async_flip)
+ if (intel_plane_do_async_flip(plane, new_crtc_state, old_crtc_state))
new_plane_state->do_async_flip = true;
return 0;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 06707d2b5fc5..8269f1e9c784 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5497,6 +5497,16 @@ static int skl_wm_max_lines(struct drm_i915_private
*dev_priv)
return 31;
}
+static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
+struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ return DISPLAY_VER(i915) >= 13 &&
+ crtc_state->uapi.async_flip &&
+ plane->async_flip;
+}
+
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
struct intel_plane *plane,
int level,
@@ -5510,7 +5520,8 @@ static void skl_compute_plane_wm(const struct
intel_crtc_state *crtc_state,
uint_fixed_16_16_t selected_result;
u32 blocks, lines, min_ddb_alloc = 0;
- if (latency == 0) {
+ if (latency == 0 ||
+ (use_minimal_wm0_only(crtc_state, plane) && level > 0)) {
/* reject it */
result->min_ddb_alloc = U16_MAX;
return;
--
2.24.1.485.gad05a3d8e5
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
On Mon, Jan 24, 2022 at 11:06:53AM +0200, Stanislav Lisovskiy wrote:
> In terms of async flip optimization we don't to allocate
> extra ddb space, so lets skip it.
>
> v2: - Extracted min ddb async flip check to separate function
> (Ville Syrjälä)
> - Used this function to prevent false positive WARN
> to be triggered(Ville Syrjälä)
>
> v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
> it more universal.
> - Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
> - Use rate = 0 instead of just setting extra = 0, thus
> letting other planes to use extra ddb and avoiding WARN
> (Ville Syrjälä)
>
> v4: - Renamed needs_min_ddb as s/needs/use/ to match
> the wm0 counterpart(Ville Syrjälä)
> - Added plane->async_flip check to use_min_ddb(now
> passing plane as a parameter to do that)(Ville Syrjälä)
> - Account for use_min_ddb also when calculating total data rate
> (Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
> .../gpu/drm/i915/display/intel_atomic_plane.h | 3 +-
> drivers/gpu/drm/i915/intel_pm.c | 53 ++-
> 3 files changed, 44 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index b20cf2c16691..9d79ab987b2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -374,7 +374,7 @@ int intel_plane_atomic_check_with_state(const struct
> intel_crtc_state *old_crtc_
> old_plane_state,
> new_plane_state);
> }
>
> -static struct intel_plane *
> +struct intel_plane *
> intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
> {
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index ead789709477..aaddcc636f98 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -23,7 +23,8 @@ unsigned int intel_adjusted_rate(const struct drm_rect *src,
>unsigned int rate);
> unsigned int intel_plane_pixel_rate(const struct intel_crtc_state
> *crtc_state,
> const struct intel_plane_state
> *plane_state);
> -
> +struct intel_plane *intel_crtc_get_plane(struct intel_crtc *crtc,
> + enum plane_id plane_id);
> unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state);
> void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8269f1e9c784..fbe6a45801bc 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4988,6 +4988,25 @@ skl_get_total_relative_data_rate(struct
> intel_atomic_state *state,
> return total_data_rate;
> }
>
> +static bool use_min_ddb(struct intel_crtc_state *crtc_state,
> + struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +
> + return DISPLAY_VER(i915) >= 13 && crtc_state->uapi.async_flip &&
> +plane->async_flip;
> +}
> +
> +static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
> + struct intel_plane *plane)
Please put this function into the right spot to begin with.
Avoids polluting this patch with unrelated code movement.
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +
> + return DISPLAY_VER(i915) >= 13 &&
> +crtc_state->uapi.async_flip &&
> +plane->async_flip;
Line wrapping is different between the two functions despite the
identical contents, which looks a bit weird.
> +}
> +
> static u64
> icl_get_total_relative_data_rate(struct intel_atomic_state *state,
>struct intel_crtc *crtc)
> @@ -5033,8 +5052,15 @@ icl_get_total_relative_data_rate(struct
> intel_atomic_state *state,
> }
> }
>
> - for_each_plane_id_on_crtc(crtc, plane_id)
> - total_data_rate += crtc_state->plane_data_rate[plane_id];
> + for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
for_each_intel_plane_on_crtc() otherwise we miss all
the planes not in the state.
> + /*
> + * We calculate extra ddb based on ratio plane rate/total data
> rate
> + * in case, in some cases we should not allocate extra ddb for
> the plane,
> + * so do not count its data rate, if this is the case.
> + */
> + if
[Intel-gfx] [PATCH v2] drm/i915: fix header file inclusion for might_alloc()
Replace "linux/slab.h" with "linux/sched/mm.h" header inclusion
as the first is not required, while the second, if not included,
prdouces the following error:
drivers/gpu/drm/i915/i915_vma_resource.c: In function
‘i915_vma_resource_bind_dep_await’:
drivers/gpu/drm/i915/i915_vma_resource.c:381:9: error: implicit declaration of
function ‘might_alloc’; did you mean ‘might_lock’?
[-Werror=implicit-function-declaration]
381 | might_alloc(gfp);
| ^~~
| might_lock
Fixes: 2f6b90da9192 ("drm/i915: Use vma resources for async unbinding")
Signed-off-by: Andi Shyti
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
Hi,
in V2 I just added the Fixes tag (I think I got the right commit)
and added Thomas r-b.
Andi
drivers/gpu/drm/i915/i915_vma_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_vma_resource.c
b/drivers/gpu/drm/i915/i915_vma_resource.c
index 1f41c0c699eb..bbb0ff14272f 100644
--- a/drivers/gpu/drm/i915/i915_vma_resource.c
+++ b/drivers/gpu/drm/i915/i915_vma_resource.c
@@ -4,7 +4,7 @@
*/
#include
-#include
+#include
#include "i915_sw_fence.h"
#include "i915_vma_resource.h"
--
2.34.1
Re: [Intel-gfx] [PATCH 3/4] drm/i915: Use wm0 only during async flips for DG2
On Mon, Jan 24, 2022 at 11:06:52AM +0200, Stanislav Lisovskiy wrote:
> This optimization allows to achieve higher perfomance
> during async flips.
> For the first async flip we have to still temporarily
> switch to sync flip, in order to reprogram plane
> watermarks, so this requires taking into account
> old plane state's do_async_flip flag.
>
> v2: - Removed redundant new_plane_state->do_async_flip
> check from needs_async_flip_wm_override condition
> (Ville Syrjälä)
> - Extract dg2_async_flip_optimization to separate
> function(Ville Syrjälä)
> - Check for plane->async_flip instead of plane_id
> (Ville Syrjälä)
>
> v3: - Rename "needs_async_flip_wm_override" to
> "intel_plane_do_async_flip" and move all the required
> checks there (Ville Syrjälä)
> - Rename "dg2_async_flip_optimization" to
> "use_minimal_wm0_only" (Ville Syrjälä)
>
> v4: - Swap new/old_crtc_state in intel_plane_do_async_flip
> argument list(Ville Syrjälä)
> - Use plane->base.dev to grab i915 pointer in
> intel_plane_do_async_flip(Ville Syrjälä)
> - Remove const modifier from plane parameter in
> use_minimal_wm0_only(Ville Syrjälä)
>
> Reviewed-by: Ville Syrjälä
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 24 +++-
> drivers/gpu/drm/i915/intel_pm.c | 13 ++-
> 2 files changed, 35 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index a65bae1f0c35..d4ba6c2910fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4910,6 +4910,28 @@ static bool needs_scaling(const struct
> intel_plane_state *state)
> return (src_w != dst_w || src_h != dst_h);
> }
>
> +static bool intel_plane_do_async_flip(struct intel_plane *plane,
> + const struct intel_crtc_state
> *old_crtc_state,
> + const struct intel_crtc_state
> *new_crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +
> + if (!plane->async_flip)
> + return false;
> +
> + if (!new_crtc_state->uapi.async_flip)
> + return false;
> +
> + /*
> + * In platforms after DISPLAY13, we might need to override
> + * first async flip in order to change watermark levels
> + * as part of optimization.
> + * So for those, we are checking if this is a first async flip.
> + * For platforms earlier than DISPLAY13 we always do async flip.
> + */
> + return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
> +}
> +
> int intel_plane_atomic_calc_changes(const struct intel_crtc_state
> *old_crtc_state,
> struct intel_crtc_state *new_crtc_state,
> const struct intel_plane_state
> *old_plane_state,
> @@ -5029,7 +5051,7 @@ int intel_plane_atomic_calc_changes(const struct
> intel_crtc_state *old_crtc_stat
>needs_scaling(new_plane_state
> new_crtc_state->disable_lp_wm = true;
>
> - if (new_crtc_state->uapi.async_flip && plane->async_flip)
> + if (intel_plane_do_async_flip(plane, new_crtc_state, old_crtc_state))
need to swap the new vs. old here too.
> new_plane_state->do_async_flip = true;
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 06707d2b5fc5..8269f1e9c784 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5497,6 +5497,16 @@ static int skl_wm_max_lines(struct drm_i915_private
> *dev_priv)
> return 31;
> }
>
> +static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
> + struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +
> + return DISPLAY_VER(i915) >= 13 &&
> +crtc_state->uapi.async_flip &&
> +plane->async_flip;
> +}
> +
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>struct intel_plane *plane,
>int level,
> @@ -5510,7 +5520,8 @@ static void skl_compute_plane_wm(const struct
> intel_crtc_state *crtc_state,
> uint_fixed_16_16_t selected_result;
> u32 blocks, lines, min_ddb_alloc = 0;
>
> - if (latency == 0) {
> + if (latency == 0 ||
> + (use_minimal_wm0_only(crtc_state, plane) && level > 0)) {
> /* reject it */
> result->min_ddb_alloc = U16_MAX;
> return;
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH] drm/i915: fix header file inclusion for might_alloc()
Hi Am 24.01.22 um 02:08 schrieb Andi Shyti: Replace "linux/slab.h" with "linux/sched/mm.h" header inclusion as the first is not required, while the second, if not included, prdouces the following error: 'produces' drivers/gpu/drm/i915/i915_vma_resource.c: In function ‘i915_vma_resource_bind_dep_await’: drivers/gpu/drm/i915/i915_vma_resource.c:381:9: error: implicit declaration of function ‘might_alloc’; did you mean ‘might_lock’? [-Werror=implicit-function-declaration] 381 | might_alloc(gfp); | ^~~ | might_lock Signed-off-by: Andi Shyti Cc: Thomas Hellström --- drivers/gpu/drm/i915/i915_vma_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_vma_resource.c b/drivers/gpu/drm/i915/i915_vma_resource.c index 1f41c0c699eb..bbb0ff14272f 100644 --- a/drivers/gpu/drm/i915/i915_vma_resource.c +++ b/drivers/gpu/drm/i915/i915_vma_resource.c @@ -4,7 +4,7 @@ */ #include -#include +#include #include "i915_sw_fence.h" #include "i915_vma_resource.h" -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Ivo Totev OpenPGP_signature Description: OpenPGP digital signature
Re: [Intel-gfx] [PATCH 3/4] drm/i915: Use wm0 only during async flips for DG2
On Mon, Jan 24, 2022 at 11:11:14AM +0200, Ville Syrjälä wrote:
> On Mon, Jan 24, 2022 at 11:06:52AM +0200, Stanislav Lisovskiy wrote:
> > This optimization allows to achieve higher perfomance
> > during async flips.
> > For the first async flip we have to still temporarily
> > switch to sync flip, in order to reprogram plane
> > watermarks, so this requires taking into account
> > old plane state's do_async_flip flag.
> >
> > v2: - Removed redundant new_plane_state->do_async_flip
> > check from needs_async_flip_wm_override condition
> > (Ville Syrjälä)
> > - Extract dg2_async_flip_optimization to separate
> > function(Ville Syrjälä)
> > - Check for plane->async_flip instead of plane_id
> > (Ville Syrjälä)
> >
> > v3: - Rename "needs_async_flip_wm_override" to
> > "intel_plane_do_async_flip" and move all the required
> > checks there (Ville Syrjälä)
> > - Rename "dg2_async_flip_optimization" to
> > "use_minimal_wm0_only" (Ville Syrjälä)
> >
> > v4: - Swap new/old_crtc_state in intel_plane_do_async_flip
> > argument list(Ville Syrjälä)
> > - Use plane->base.dev to grab i915 pointer in
> > intel_plane_do_async_flip(Ville Syrjälä)
> > - Remove const modifier from plane parameter in
> > use_minimal_wm0_only(Ville Syrjälä)
> >
> > Reviewed-by: Ville Syrjälä
> > Signed-off-by: Stanislav Lisovskiy
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 24 +++-
> > drivers/gpu/drm/i915/intel_pm.c | 13 ++-
> > 2 files changed, 35 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index a65bae1f0c35..d4ba6c2910fc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -4910,6 +4910,28 @@ static bool needs_scaling(const struct
> > intel_plane_state *state)
> > return (src_w != dst_w || src_h != dst_h);
> > }
> >
> > +static bool intel_plane_do_async_flip(struct intel_plane *plane,
> > + const struct intel_crtc_state
> > *old_crtc_state,
> > + const struct intel_crtc_state
> > *new_crtc_state)
> > +{
> > + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> > +
> > + if (!plane->async_flip)
> > + return false;
> > +
> > + if (!new_crtc_state->uapi.async_flip)
> > + return false;
> > +
> > + /*
> > +* In platforms after DISPLAY13, we might need to override
> > +* first async flip in order to change watermark levels
> > +* as part of optimization.
> > +* So for those, we are checking if this is a first async flip.
> > +* For platforms earlier than DISPLAY13 we always do async flip.
> > +*/
> > + return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
> > +}
> > +
> > int intel_plane_atomic_calc_changes(const struct intel_crtc_state
> > *old_crtc_state,
> > struct intel_crtc_state *new_crtc_state,
> > const struct intel_plane_state
> > *old_plane_state,
> > @@ -5029,7 +5051,7 @@ int intel_plane_atomic_calc_changes(const struct
> > intel_crtc_state *old_crtc_stat
> > needs_scaling(new_plane_state
> > new_crtc_state->disable_lp_wm = true;
> >
> > - if (new_crtc_state->uapi.async_flip && plane->async_flip)
> > + if (intel_plane_do_async_flip(plane, new_crtc_state, old_crtc_state))
>
> need to swap the new vs. old here too.
Damn right, thanks for spotting. Stupid mistake..
Stan
>
> > new_plane_state->do_async_flip = true;
> >
> > return 0;
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 06707d2b5fc5..8269f1e9c784 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5497,6 +5497,16 @@ static int skl_wm_max_lines(struct drm_i915_private
> > *dev_priv)
> > return 31;
> > }
> >
> > +static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
> > +struct intel_plane *plane)
> > +{
> > + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> > +
> > + return DISPLAY_VER(i915) >= 13 &&
> > + crtc_state->uapi.async_flip &&
> > + plane->async_flip;
> > +}
> > +
> > static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> > struct intel_plane *plane,
> > int level,
> > @@ -5510,7 +5520,8 @@ static void skl_compute_plane_wm(const struct
> > intel_crtc_state *crtc_state,
> > uint_fixed_16_16_t selected_result;
> > u32 blocks, lines, min_ddb_alloc = 0;
> >
> > - if (latency == 0) {
> > + if (latency == 0 ||
> > + (use_minimal_wm0_only(crtc_state, plane) && level > 0)) {
> > /*
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
On Mon, Jan 24, 2022 at 11:16:36AM +0200, Ville Syrjälä wrote:
> On Mon, Jan 24, 2022 at 11:06:53AM +0200, Stanislav Lisovskiy wrote:
> > In terms of async flip optimization we don't to allocate
> > extra ddb space, so lets skip it.
> >
> > v2: - Extracted min ddb async flip check to separate function
> > (Ville Syrjälä)
> > - Used this function to prevent false positive WARN
> > to be triggered(Ville Syrjälä)
> >
> > v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
> > it more universal.
> > - Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
> > - Use rate = 0 instead of just setting extra = 0, thus
> > letting other planes to use extra ddb and avoiding WARN
> > (Ville Syrjälä)
> >
> > v4: - Renamed needs_min_ddb as s/needs/use/ to match
> > the wm0 counterpart(Ville Syrjälä)
> > - Added plane->async_flip check to use_min_ddb(now
> > passing plane as a parameter to do that)(Ville Syrjälä)
> > - Account for use_min_ddb also when calculating total data rate
> > (Ville Syrjälä)
> >
> > Signed-off-by: Stanislav Lisovskiy
> > ---
> > .../gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
> > .../gpu/drm/i915/display/intel_atomic_plane.h | 3 +-
> > drivers/gpu/drm/i915/intel_pm.c | 53 ++-
> > 3 files changed, 44 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > index b20cf2c16691..9d79ab987b2e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > @@ -374,7 +374,7 @@ int intel_plane_atomic_check_with_state(const struct
> > intel_crtc_state *old_crtc_
> >old_plane_state,
> > new_plane_state);
> > }
> >
> > -static struct intel_plane *
> > +struct intel_plane *
> > intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
> > {
> > struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > index ead789709477..aaddcc636f98 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > @@ -23,7 +23,8 @@ unsigned int intel_adjusted_rate(const struct drm_rect
> > *src,
> > unsigned int rate);
> > unsigned int intel_plane_pixel_rate(const struct intel_crtc_state
> > *crtc_state,
> > const struct intel_plane_state
> > *plane_state);
> > -
> > +struct intel_plane *intel_crtc_get_plane(struct intel_crtc *crtc,
> > + enum plane_id plane_id);
> > unsigned int intel_plane_data_rate(const struct intel_crtc_state
> > *crtc_state,
> >const struct intel_plane_state *plane_state);
> > void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state
> > *plane_state,
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 8269f1e9c784..fbe6a45801bc 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4988,6 +4988,25 @@ skl_get_total_relative_data_rate(struct
> > intel_atomic_state *state,
> > return total_data_rate;
> > }
> >
> > +static bool use_min_ddb(struct intel_crtc_state *crtc_state,
> > + struct intel_plane *plane)
> > +{
> > + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> > +
> > + return DISPLAY_VER(i915) >= 13 && crtc_state->uapi.async_flip &&
> > + plane->async_flip;
> > +}
> > +
> > +static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
> > +struct intel_plane *plane)
>
> Please put this function into the right spot to begin with.
> Avoids polluting this patch with unrelated code movement.
It happened this way, because initially use_minimal_wm0_only which
is needed only by skl_compute_plane_wm was much lower, however as
you recommended to group it with use_min_ddb, so had to move it higher,
because use_min_ddb is required way higher in the file.
However I will then change the patch where it was introduced, so that
its already there.
>
> > +{
> > + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> > +
> > + return DISPLAY_VER(i915) >= 13 &&
> > + crtc_state->uapi.async_flip &&
> > + plane->async_flip;
>
> Line wrapping is different between the two functions despite the
> identical contents, which looks a bit weird.
>
> > +}
> > +
> > static u64
> > icl_get_total_relative_data_rate(struct intel_atomic_state *state,
> > struct intel_crtc *crtc)
> > @@ -5033,8 +5052,15 @@ icl_get_total_relative_data_rate(struct
> > intel_atomic_state *state,
> > }
> >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: fix header file inclusion for might_alloc() (rev2)
== Series Details == Series: drm/i915: fix header file inclusion for might_alloc() (rev2) URL : https://patchwork.freedesktop.org/series/99215/ State : success == Summary == CI Bug Log - changes from CI_DRM_11120 -> Patchwork_22075 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22075/index.html Participating hosts (49 -> 33) -- Missing(16): fi-ilk-m540 fi-bdw-samus shard-tglu bat-dg1-6 fi-hsw-4200u fi-icl-u2 fi-bsw-cyan bat-adlp-6 fi-ctg-p8600 fi-cfl-8109u fi-kbl-8809g bat-rpls-1 shard-rkl shard-dg1 bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_22075 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-bsw-n3050: [PASS][1] -> [INCOMPLETE][2] ([i915#2940]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22075/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html * igt@kms_flip@basic-flip-vs-wf_vblank@b-hdmi-a1: - fi-elk-e7500: [PASS][3] -> [FAIL][4] ([i915#2122]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-elk-e7500/igt@kms_flip@basic-flip-vs-wf_vbl...@b-hdmi-a1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22075/fi-elk-e7500/igt@kms_flip@basic-flip-vs-wf_vbl...@b-hdmi-a1.html * igt@runner@aborted: - fi-tgl-1115g4: NOTRUN -> [FAIL][5] ([i915#4312]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22075/fi-tgl-1115g4/igt@run...@aborted.html - fi-bsw-n3050: NOTRUN -> [FAIL][6] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22075/fi-bsw-n3050/igt@run...@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 Build changes - * Linux: CI_DRM_11120 -> Patchwork_22075 CI-20190529: 20190529 CI_DRM_11120: d8e524ded1a6cb24bbd2da0785b04f199c03f1b9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6330: f73008bac9a8db0779264b170f630483e9165764 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_22075: e88e293f760284f0f7745fe00fc49743980c1ed8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e88e293f7602 drm/i915: fix header file inclusion for might_alloc() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22075/index.html
Re: [Intel-gfx] [PATCH v4 1/2] i915/gvt: Introduce the mmio_info_table.c to support VFIO new mdev API
On Fri, Dec 17, 2021 at 08:52:53AM +, Wang, Zhi A wrote: > Sorry for the late reply as I am supporting the customers recently. I > will refresh this after the christmas. Did you find some time to look into it? Do you want some help?
[Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
In terms of async flip optimization we don't to allocate
extra ddb space, so lets skip it.
v2: - Extracted min ddb async flip check to separate function
(Ville Syrjälä)
- Used this function to prevent false positive WARN
to be triggered(Ville Syrjälä)
v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
it more universal.
- Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
- Use rate = 0 instead of just setting extra = 0, thus
letting other planes to use extra ddb and avoiding WARN
(Ville Syrjälä)
v4: - Renamed needs_min_ddb as s/needs/use/ to match
the wm0 counterpart(Ville Syrjälä)
- Added plane->async_flip check to use_min_ddb(now
passing plane as a parameter to do that)(Ville Syrjälä)
- Account for use_min_ddb also when calculating total data rate
(Ville Syrjälä)
v5:
- Use for_each_intel_plane_on_crtc instead of for_each_intel_plane_id
to get plane->async_flip check and account for all planes(Ville Syrjälä)
- Fix line wrapping(Ville Syrjälä)
- Set plane data rate conditionally, avoiding on redundant assignment
(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
.../gpu/drm/i915/display/intel_atomic_plane.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 40 ---
2 files changed, 35 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index ead789709477..c238177e5563 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -23,7 +23,6 @@ unsigned int intel_adjusted_rate(const struct drm_rect *src,
unsigned int rate);
unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state
*plane_state);
-
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f6c742b583c1..7ce26f22e10e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4988,6 +4988,16 @@ skl_get_total_relative_data_rate(struct
intel_atomic_state *state,
return total_data_rate;
}
+static bool use_min_ddb(struct intel_crtc_state *crtc_state,
+ struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ return DISPLAY_VER(i915) >= 13 &&
+ crtc_state->uapi.async_flip &&
+ plane->async_flip;
+}
+
static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
struct intel_plane *plane)
{
@@ -5002,6 +5012,7 @@ static u64
icl_get_total_relative_data_rate(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_plane_state *plane_state;
@@ -5043,8 +5054,15 @@ icl_get_total_relative_data_rate(struct
intel_atomic_state *state,
}
}
- for_each_plane_id_on_crtc(crtc, plane_id)
- total_data_rate += crtc_state->plane_data_rate[plane_id];
+ for_each_intel_plane_on_crtc(>drm, crtc, plane) {
+ /*
+* We calculate extra ddb based on ratio plane rate/total data
rate
+* in case, in some cases we should not allocate extra ddb for
the plane,
+* so do not count its data rate, if this is the case.
+*/
+ if (!use_min_ddb(crtc_state, plane))
+ total_data_rate +=
crtc_state->plane_data_rate[plane->id];
+ }
return total_data_rate;
}
@@ -5130,6 +5148,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
u16 alloc_size, start = 0;
u16 total[I915_MAX_PLANES] = {};
u16 uv_total[I915_MAX_PLANES] = {};
+ struct intel_plane *plane;
u64 total_data_rate;
enum plane_id plane_id;
u32 blocks;
@@ -5206,7 +5225,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
* watermark level, plus an extra share of the leftover blocks
* proportional to its relative data rate.
*/
- for_each_plane_id_on_crtc(crtc, plane_id) {
+ for_each_intel_plane_on_crtc(_priv->drm, crtc, plane) {
const struct skl_plane_wm *wm =
_state->wm.skl.optimal.planes[plane_id];
u64 rate;
@@ -5222,10 +5241,15 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
if
[Intel-gfx] ✓ Fi.CI.BAT: success for Async flip optimization for DG2 (rev5)
== Series Details ==
Series: Async flip optimization for DG2 (rev5)
URL : https://patchwork.freedesktop.org/series/98981/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11120 -> Patchwork_22076
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22076/index.html
Participating hosts (49 -> 37)
--
Additional (1): fi-pnv-d510
Missing(13): fi-ilk-m540 fi-bdw-samus shard-tglu bat-dg1-6 fi-hsw-4200u
fi-bsw-cyan bat-adlp-6 fi-ctg-p8600 bat-rpls-1 shard-rkl shard-dg1 bat-jsl-2
bat-jsl-1
Known issues
Here are the changes found in Patchwork_22076 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22076/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
- fi-pnv-d510:NOTRUN -> [SKIP][2] ([fdo#109271]) +57 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22076/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22076/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [PASS][4] -> [INCOMPLETE][5] ([i915#2940])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22076/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22076/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271]) +21 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22076/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22076/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@runner@aborted:
- fi-icl-u2: NOTRUN -> [FAIL][9] ([i915#4312])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22076/fi-icl-u2/igt@run...@aborted.html
- fi-tgl-1115g4: NOTRUN -> [FAIL][10] ([i915#4312])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22076/fi-tgl-1115g4/igt@run...@aborted.html
- fi-rkl-11600: NOTRUN -> [FAIL][11] ([i915#4312])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22076/fi-rkl-11600/igt@run...@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][12] ([i915#2426] / [i915#4312])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22076/fi-bdw-5557u/igt@run...@aborted.html
- fi-rkl-guc: NOTRUN -> [FAIL][13] ([i915#4312])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22076/fi-rkl-guc/igt@run...@aborted.html
Possible fixes
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [INCOMPLETE][14] ([i915#4547]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22076/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][16] ([i915#4269]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22076/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#533]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: drm device based logging conversions (rev3)
== Series Details == Series: drm/i915/display: drm device based logging conversions (rev3) URL : https://patchwork.freedesktop.org/series/99151/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] [PATCH v2] drm/i915: fix header file inclusion for might_alloc()
Replace "linux/slab.h" with "linux/sched/mm.h" header inclusion
as the first is not required, while the second, if not included,
prdouces the following error:
drivers/gpu/drm/i915/i915_vma_resource.c: In function
‘i915_vma_resource_bind_dep_await’:
drivers/gpu/drm/i915/i915_vma_resource.c:381:9: error: implicit declaration of
function ‘might_alloc’; did you mean ‘might_lock’?
[-Werror=implicit-function-declaration]
381 | might_alloc(gfp);
| ^~~
| might_lock
Fixes: 2f6b90da9192 ("drm/i915: Use vma resources for async unbinding")
Signed-off-by: Andi Shyti
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
Hi,
in V2 I just added the Fixes tag (I think I got the right commit)
and added Thomas r-b.
Andi
drivers/gpu/drm/i915/i915_vma_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_vma_resource.c
b/drivers/gpu/drm/i915/i915_vma_resource.c
index 1f41c0c699eb..bbb0ff14272f 100644
--- a/drivers/gpu/drm/i915/i915_vma_resource.c
+++ b/drivers/gpu/drm/i915/i915_vma_resource.c
@@ -4,7 +4,7 @@
*/
#include
-#include
+#include
#include "i915_sw_fence.h"
#include "i915_vma_resource.h"
--
2.34.1
[Intel-gfx] [PATCH v3] drm/i915: fix header file inclusion for might_alloc()
Replace "linux/slab.h" with "linux/sched/mm.h" header inclusion
as the first is not required, while the second, if not included,
prodouces the following error:
drivers/gpu/drm/i915/i915_vma_resource.c: In function
‘i915_vma_resource_bind_dep_await’:
drivers/gpu/drm/i915/i915_vma_resource.c:381:9: error: implicit declaration of
function ‘might_alloc’; did you mean ‘might_lock’?
[-Werror=implicit-function-declaration]
381 | might_alloc(gfp);
| ^~~
| might_lock
Fixes: 2f6b90da9192 ("drm/i915: Use vma resources for async unbinding")
Signed-off-by: Andi Shyti
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
Hi,
v3: fixed a typo in the commit log (prduces/produces). (Thanks
Thomas Zimmermann)
v2: added the 'Fixes' tag (I think I got the right commit) and
Thomas Hellström r-b.
Andi
drivers/gpu/drm/i915/i915_vma_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_vma_resource.c
b/drivers/gpu/drm/i915/i915_vma_resource.c
index 1f41c0c699eb..bbb0ff14272f 100644
--- a/drivers/gpu/drm/i915/i915_vma_resource.c
+++ b/drivers/gpu/drm/i915/i915_vma_resource.c
@@ -4,7 +4,7 @@
*/
#include
-#include
+#include
#include "i915_sw_fence.h"
#include "i915_vma_resource.h"
--
2.34.1
Re: [Intel-gfx] [PATCH v4 1/2] i915/gvt: Introduce the mmio_info_table.c to support VFIO new mdev API
Hi Christoph and Jason: Have been talking with Raj. I am going to work on this series this week. Thanks, Zhi. -Original Message- From: Christoph Hellwig Sent: Monday, January 24, 2022 11:40 AM To: Wang, Zhi A Cc: Christoph Hellwig ; Zhi Wang ; intel-gfx@lists.freedesktop.org; intel-gvt-...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org; Jason Gunthorpe ; Jani Nikula ; Joonas Lahtinen ; Vivi, Rodrigo ; Zhenyu Wang ; Xu, Terrence Subject: Re: [PATCH v4 1/2] i915/gvt: Introduce the mmio_info_table.c to support VFIO new mdev API On Fri, Dec 17, 2021 at 08:52:53AM +, Wang, Zhi A wrote: > Sorry for the late reply as I am supporting the customers recently. I > will refresh this after the christmas. Did you find some time to look into it? Do you want some help?
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: drm device based logging conversions (rev3)
== Series Details ==
Series: drm/i915/display: drm device based logging conversions (rev3)
URL : https://patchwork.freedesktop.org/series/99151/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11120 -> Patchwork_22077
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/index.html
Participating hosts (49 -> 41)
--
Additional (1): fi-pnv-d510
Missing(9): fi-kbl-soraka fi-ilk-m540 shard-tglu fi-hsw-4200u fi-bsw-cyan
fi-ctg-p8600 shard-rkl shard-dg1 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22077 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u: [PASS][1] -> [INCOMPLETE][2] ([i915#146])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
- fi-pnv-d510:NOTRUN -> [SKIP][4] ([fdo#109271]) +57 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271]) +21 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@runner@aborted:
- fi-tgl-1115g4: NOTRUN -> [FAIL][9] ([i915#4312])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/fi-tgl-1115g4/igt@run...@aborted.html
Possible fixes
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [INCOMPLETE][10] ([i915#4547]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-
* Linux: CI_DRM_11120 -> Patchwork_22077
CI-20190529: 20190529
CI_DRM_11120: d8e524ded1a6cb24bbd2da0785b04f199c03f1b9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6330: f73008bac9a8db0779264b170f630483e9165764 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22077: 53c0bb02a17bebbf5b5e80b3932cdcfc44c271f0 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
53c0bb02a17b drm/i915/cdclk: convert to drm device based logging
a217f61a4f50 drm/i915/cdclk: update intel_dump_cdclk_config() logging
74ae0578c8de drm/i915/lspcon: convert to drm device based logging
6f6a1eab23e7 drm/i915/sprite: convert to drm device based logging
b53c3cbc5c7c drm/i915/plane: convert to drm device based logging and WARN
1cbb8abc5672 drm/i915/dp: convert to drm device based logging
ed14ffd548f6 drm/i915/hotplug: convert to drm device based logging
c0ed446aaf38 drm/i915/pps: convert to drm device based logging
145b0a01b8e8 drm/i915/snps: convert to drm device based logging
== Logs ==
For more
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Async flip optimization for DG2 (rev5)
== Series Details == Series: Async flip optimization for DG2 (rev5) URL : https://patchwork.freedesktop.org/series/98981/ State : warning == Summary == $ dim checkpatch origin/drm-tip 58dc909288f9 drm/i915: Pass plane to watermark calculation functions a8601bc34503 drm/i915: Introduce do_async_flip flag to intel_plane_state aeefcd12bb9c drm/i915: Use wm0 only during async flips for DG2 -:9: WARNING:TYPO_SPELLING: 'perfomance' may be misspelled - perhaps 'performance'? #9: This optimization allows to achieve higher perfomance ^^ total: 0 errors, 1 warnings, 0 checks, 61 lines checked bdb0b08414b0 drm/i915: Don't allocate extra ddb during async flip for DG2 -:56: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #56: FILE: drivers/gpu/drm/i915/display/intel_atomic_plane.h:27: +struct intel_plane *intel_crtc_get_plane(struct intel_crtc *crtc, + enum plane_id plane_id); total: 0 errors, 0 warnings, 1 checks, 116 lines checked
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: drm device based logging conversions (rev3)
== Series Details == Series: drm/i915/display: drm device based logging conversions (rev3) URL : https://patchwork.freedesktop.org/series/99151/ State : warning == Summary == $ dim checkpatch origin/drm-tip 145b0a01b8e8 drm/i915/snps: convert to drm device based logging c0ed446aaf38 drm/i915/pps: convert to drm device based logging ed14ffd548f6 drm/i915/hotplug: convert to drm device based logging 1cbb8abc5672 drm/i915/dp: convert to drm device based logging b53c3cbc5c7c drm/i915/plane: convert to drm device based logging and WARN 6f6a1eab23e7 drm/i915/sprite: convert to drm device based logging 74ae0578c8de drm/i915/lspcon: convert to drm device based logging -:488: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #488: FILE: drivers/gpu/drm/i915/display/intel_lspcon.c:696: + drm_err(>drm, "LSPCON init failed on port %c\n", port_name(dig_port->base.port)); total: 0 errors, 0 warnings, 1 checks, 451 lines checked a217f61a4f50 drm/i915/cdclk: update intel_dump_cdclk_config() logging 53c0bb02a17b drm/i915/cdclk: convert to drm device based logging
Re: [Intel-gfx] [PATCH v3] drm/i915: fix header file inclusion for might_alloc()
Op 24-01-2022 om 10:44 schreef Andi Shyti:
> Replace "linux/slab.h" with "linux/sched/mm.h" header inclusion
> as the first is not required, while the second, if not included,
> prodouces the following error:
>
> drivers/gpu/drm/i915/i915_vma_resource.c: In function
> ‘i915_vma_resource_bind_dep_await’:
> drivers/gpu/drm/i915/i915_vma_resource.c:381:9: error: implicit declaration
> of function ‘might_alloc’; did you mean ‘might_lock’?
> [-Werror=implicit-function-declaration]
> 381 | might_alloc(gfp);
> | ^~~
> | might_lock
>
> Fixes: 2f6b90da9192 ("drm/i915: Use vma resources for async unbinding")
> Signed-off-by: Andi Shyti
> Cc: Thomas Hellström
> Reviewed-by: Thomas Hellström
> ---
> Hi,
>
> v3: fixed a typo in the commit log (prduces/produces). (Thanks
> Thomas Zimmermann)
>
> v2: added the 'Fixes' tag (I think I got the right commit) and
> Thomas Hellström r-b.
>
> Andi
>
> drivers/gpu/drm/i915/i915_vma_resource.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_vma_resource.c
> b/drivers/gpu/drm/i915/i915_vma_resource.c
> index 1f41c0c699eb..bbb0ff14272f 100644
> --- a/drivers/gpu/drm/i915/i915_vma_resource.c
> +++ b/drivers/gpu/drm/i915/i915_vma_resource.c
> @@ -4,7 +4,7 @@
> */
>
> #include
> -#include
> +#include
>
> #include "i915_sw_fence.h"
> #include "i915_vma_resource.h"
Pushed to drm-intel-gt-next. Should fix drm-tip building, probably needs to be
pulled into drm-fixes asap. :)
Re: [Intel-gfx] [PATCH v2] drm/i915: fix header file inclusion for might_alloc()
Sorry for spamming! Just called the command from the history
On Mon, Jan 24, 2022 at 11:42:43AM +0200, Andi Shyti wrote:
> Replace "linux/slab.h" with "linux/sched/mm.h" header inclusion
> as the first is not required, while the second, if not included,
> prdouces the following error:
>
> drivers/gpu/drm/i915/i915_vma_resource.c: In function
> ‘i915_vma_resource_bind_dep_await’:
> drivers/gpu/drm/i915/i915_vma_resource.c:381:9: error: implicit declaration
> of function ‘might_alloc’; did you mean ‘might_lock’?
> [-Werror=implicit-function-declaration]
> 381 | might_alloc(gfp);
> | ^~~
> | might_lock
>
> Fixes: 2f6b90da9192 ("drm/i915: Use vma resources for async unbinding")
> Signed-off-by: Andi Shyti
> Cc: Thomas Hellström
> Reviewed-by: Thomas Hellström
> ---
> Hi,
>
> in V2 I just added the Fixes tag (I think I got the right commit)
> and added Thomas r-b.
>
> Andi
>
> drivers/gpu/drm/i915/i915_vma_resource.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_vma_resource.c
> b/drivers/gpu/drm/i915/i915_vma_resource.c
> index 1f41c0c699eb..bbb0ff14272f 100644
> --- a/drivers/gpu/drm/i915/i915_vma_resource.c
> +++ b/drivers/gpu/drm/i915/i915_vma_resource.c
> @@ -4,7 +4,7 @@
> */
>
> #include
> -#include
> +#include
>
> #include "i915_sw_fence.h"
> #include "i915_vma_resource.h"
> --
> 2.34.1
[Intel-gfx] [PATCH 3/4] drm/i915: Use wm0 only during async flips for DG2
This optimization allows to achieve higher perfomance
during async flips.
For the first async flip we have to still temporarily
switch to sync flip, in order to reprogram plane
watermarks, so this requires taking into account
old plane state's do_async_flip flag.
v2: - Removed redundant new_plane_state->do_async_flip
check from needs_async_flip_wm_override condition
(Ville Syrjälä)
- Extract dg2_async_flip_optimization to separate
function(Ville Syrjälä)
- Check for plane->async_flip instead of plane_id
(Ville Syrjälä)
v3: - Rename "needs_async_flip_wm_override" to
"intel_plane_do_async_flip" and move all the required
checks there (Ville Syrjälä)
- Rename "dg2_async_flip_optimization" to
"use_minimal_wm0_only" (Ville Syrjälä)
v4: - Swap new/old_crtc_state in intel_plane_do_async_flip
argument list(Ville Syrjälä)
- Use plane->base.dev to grab i915 pointer in
intel_plane_do_async_flip(Ville Syrjälä)
- Remove const modifier from plane parameter in
use_minimal_wm0_only(Ville Syrjälä)
- Swap also new/old_crtc_state at intel_plane_do_async_flip
call site(Ville Syrjälä)
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 24 +++-
drivers/gpu/drm/i915/intel_pm.c | 13 ++-
2 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a65bae1f0c35..54cb7e9bfa59 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4910,6 +4910,28 @@ static bool needs_scaling(const struct intel_plane_state
*state)
return (src_w != dst_w || src_h != dst_h);
}
+static bool intel_plane_do_async_flip(struct intel_plane *plane,
+ const struct intel_crtc_state
*old_crtc_state,
+ const struct intel_crtc_state
*new_crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ if (!plane->async_flip)
+ return false;
+
+ if (!new_crtc_state->uapi.async_flip)
+ return false;
+
+ /*
+* In platforms after DISPLAY13, we might need to override
+* first async flip in order to change watermark levels
+* as part of optimization.
+* So for those, we are checking if this is a first async flip.
+* For platforms earlier than DISPLAY13 we always do async flip.
+*/
+ return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
+}
+
int intel_plane_atomic_calc_changes(const struct intel_crtc_state
*old_crtc_state,
struct intel_crtc_state *new_crtc_state,
const struct intel_plane_state
*old_plane_state,
@@ -5029,7 +5051,7 @@ int intel_plane_atomic_calc_changes(const struct
intel_crtc_state *old_crtc_stat
needs_scaling(new_plane_state
new_crtc_state->disable_lp_wm = true;
- if (new_crtc_state->uapi.async_flip && plane->async_flip)
+ if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state))
new_plane_state->do_async_flip = true;
return 0;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 06707d2b5fc5..f6c742b583c1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4988,6 +4988,16 @@ skl_get_total_relative_data_rate(struct
intel_atomic_state *state,
return total_data_rate;
}
+static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
+struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ return DISPLAY_VER(i915) >= 13 &&
+ crtc_state->uapi.async_flip &&
+ plane->async_flip;
+}
+
static u64
icl_get_total_relative_data_rate(struct intel_atomic_state *state,
struct intel_crtc *crtc)
@@ -5510,7 +5520,8 @@ static void skl_compute_plane_wm(const struct
intel_crtc_state *crtc_state,
uint_fixed_16_16_t selected_result;
u32 blocks, lines, min_ddb_alloc = 0;
- if (latency == 0) {
+ if (latency == 0 ||
+ (use_minimal_wm0_only(crtc_state, plane) && level > 0)) {
/* reject it */
result->min_ddb_alloc = U16_MAX;
return;
--
2.24.1.485.gad05a3d8e5
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
On Mon, Jan 24, 2022 at 11:51:23AM +0200, Stanislav Lisovskiy wrote:
> In terms of async flip optimization we don't to allocate
> extra ddb space, so lets skip it.
>
> v2: - Extracted min ddb async flip check to separate function
> (Ville Syrjälä)
> - Used this function to prevent false positive WARN
> to be triggered(Ville Syrjälä)
>
> v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
> it more universal.
> - Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
> - Use rate = 0 instead of just setting extra = 0, thus
> letting other planes to use extra ddb and avoiding WARN
> (Ville Syrjälä)
>
> v4: - Renamed needs_min_ddb as s/needs/use/ to match
> the wm0 counterpart(Ville Syrjälä)
> - Added plane->async_flip check to use_min_ddb(now
> passing plane as a parameter to do that)(Ville Syrjälä)
> - Account for use_min_ddb also when calculating total data rate
> (Ville Syrjälä)
>
> v5:
> - Use for_each_intel_plane_on_crtc instead of for_each_intel_plane_id
> to get plane->async_flip check and account for all planes(Ville Syrjälä)
> - Fix line wrapping(Ville Syrjälä)
> - Set plane data rate conditionally, avoiding on redundant assignment
> (Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.h | 1 -
> drivers/gpu/drm/i915/intel_pm.c | 40 ---
> 2 files changed, 35 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index ead789709477..c238177e5563 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -23,7 +23,6 @@ unsigned int intel_adjusted_rate(const struct drm_rect *src,
>unsigned int rate);
> unsigned int intel_plane_pixel_rate(const struct intel_crtc_state
> *crtc_state,
> const struct intel_plane_state
> *plane_state);
> -
supurious whitespace changes
> unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state);
> void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f6c742b583c1..7ce26f22e10e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4988,6 +4988,16 @@ skl_get_total_relative_data_rate(struct
> intel_atomic_state *state,
> return total_data_rate;
> }
>
> +static bool use_min_ddb(struct intel_crtc_state *crtc_state,
> + struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +
> + return DISPLAY_VER(i915) >= 13 &&
> +crtc_state->uapi.async_flip &&
> +plane->async_flip;
> +}
> +
> static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
>struct intel_plane *plane)
> {
> @@ -5002,6 +5012,7 @@ static u64
> icl_get_total_relative_data_rate(struct intel_atomic_state *state,
>struct intel_crtc *crtc)
> {
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> const struct intel_plane_state *plane_state;
> @@ -5043,8 +5054,15 @@ icl_get_total_relative_data_rate(struct
> intel_atomic_state *state,
> }
> }
>
> - for_each_plane_id_on_crtc(crtc, plane_id)
> - total_data_rate += crtc_state->plane_data_rate[plane_id];
Hmm. I was going to say we should remove plane_id now, but looks like
the other loop still uses it. I would move the declaration into that
loop now to make it less likely we mess up and use the wrong thing.
> + for_each_intel_plane_on_crtc(>drm, crtc, plane) {
> + /*
> + * We calculate extra ddb based on ratio plane rate/total data
> rate
> + * in case, in some cases we should not allocate extra ddb for
> the plane,
> + * so do not count its data rate, if this is the case.
> + */
> + if (!use_min_ddb(crtc_state, plane))
> + total_data_rate +=
> crtc_state->plane_data_rate[plane->id];
> + }
>
> return total_data_rate;
> }
> @@ -5130,6 +5148,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> u16 alloc_size, start = 0;
> u16 total[I915_MAX_PLANES] = {};
> u16 uv_total[I915_MAX_PLANES] = {};
> + struct intel_plane *plane;
> u64 total_data_rate;
> enum plane_id plane_id;
> u32 blocks;
> @@ -5206,7 +5225,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>* watermark level, plus
Re: [Intel-gfx] [PATCH 5/5] drm/i915: split out gem/i915_gem_domain.h from i915_drv.h
Op 12-01-2022 om 09:51 schreef Jani Nikula:
> We already have the gem/i915_gem_domain.c file.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dpt.c| 4 +++-
> drivers/gpu/drm/i915/display/intel_fb_pin.c | 1 +
> drivers/gpu/drm/i915/gem/i915_gem_domain.c | 5 +++--
> drivers/gpu/drm/i915/gem/i915_gem_domain.h | 15 +++
> drivers/gpu/drm/i915/i915_drv.h | 3 ---
> 5 files changed, 22 insertions(+), 6 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_domain.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
> b/drivers/gpu/drm/i915/display/intel_dpt.c
> index 63a83d5f85a1..16b273e19d17 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpt.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpt.c
> @@ -3,11 +3,13 @@
> * Copyright © 2021 Intel Corporation
> */
>
> +#include "gem/i915_gem_domain.h"
> +#include "gt/gen8_ppgtt.h"
> +
> #include "i915_drv.h"
> #include "intel_display_types.h"
> #include "intel_dpt.h"
> #include "intel_fb.h"
> -#include "gt/gen8_ppgtt.h"
>
> struct i915_dpt {
> struct i915_address_space vm;
> diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
> b/drivers/gpu/drm/i915/display/intel_fb_pin.c
> index 31c15e5fca95..e60046d90124 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
> @@ -7,6 +7,7 @@
> * DOC: display pinning helpers
> */
>
> +#include "gem/i915_gem_domain.h"
> #include "gem/i915_gem_object.h"
>
> #include "i915_drv.h"
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> index 26532c07d467..3e5d6057b3ef 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> @@ -9,12 +9,13 @@
>
> #include "i915_drv.h"
> #include "i915_gem_clflush.h"
> +#include "i915_gem_domain.h"
> #include "i915_gem_gtt.h"
> #include "i915_gem_ioctls.h"
> -#include "i915_gem_object.h"
> -#include "i915_vma.h"
> #include "i915_gem_lmem.h"
> #include "i915_gem_mman.h"
> +#include "i915_gem_object.h"
> +#include "i915_vma.h"
>
> static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
> {
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.h
> b/drivers/gpu/drm/i915/gem/i915_gem_domain.h
> new file mode 100644
> index ..9622df962bfc
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef __I915_GEM_DOMAIN_H__
> +#define __I915_GEM_DOMAIN_H__
> +
> +struct drm_i915_gem_object;
> +enum i915_cache_level;
> +
> +int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
> + enum i915_cache_level cache_level);
> +
> +#endif /* __I915_GEM_DOMAIN_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 95899661d567..32cd07e144dc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1686,9 +1686,6 @@ void i915_gem_driver_release(struct drm_i915_private
> *dev_priv);
>
> int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
>
> -int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
> - enum i915_cache_level cache_level);
> -
> static inline struct i915_address_space *
> i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id)
> {
All looks sane.
Reviewed-by: Maarten Lankhorst
[Intel-gfx] [PATCH 01/11] drm/radeon: use ttm_resource_manager_debug
Instead of calling the debug operation directly. Signed-off-by: Christian König Reviewed-by: Huang Rui --- drivers/gpu/drm/radeon/radeon_ttm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 11b21d605584..0d1283cdc8fb 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -802,7 +802,7 @@ static int radeon_mm_vram_dump_table_show(struct seq_file *m, void *unused) TTM_PL_VRAM); struct drm_printer p = drm_seq_file_printer(m); - man->func->debug(man, ); + ttm_resource_manager_debug(man, ); return 0; } @@ -820,7 +820,7 @@ static int radeon_mm_gtt_dump_table_show(struct seq_file *m, void *unused) TTM_PL_TT); struct drm_printer p = drm_seq_file_printer(m); - man->func->debug(man, ); + ttm_resource_manager_debug(man, ); return 0; } -- 2.25.1
[Intel-gfx] [PATCH 08/11] dma-buf: add dma_fence_chain_contained helper
It's a reoccurring pattern that we need to extract the fence
from a dma_fence_chain object. Add a helper for this.
Signed-off-by: Christian König
---
drivers/dma-buf/dma-fence-chain.c | 6 ++
include/linux/dma-fence-chain.h | 15 +++
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/dma-buf/dma-fence-chain.c
b/drivers/dma-buf/dma-fence-chain.c
index 084c6927b735..06f8ef97c6e8 100644
--- a/drivers/dma-buf/dma-fence-chain.c
+++ b/drivers/dma-buf/dma-fence-chain.c
@@ -148,8 +148,7 @@ static bool dma_fence_chain_enable_signaling(struct
dma_fence *fence)
dma_fence_get(>base);
dma_fence_chain_for_each(fence, >base) {
- struct dma_fence_chain *chain = to_dma_fence_chain(fence);
- struct dma_fence *f = chain ? chain->fence : fence;
+ struct dma_fence *f = dma_fence_chain_contained(fence);
dma_fence_get(f);
if (!dma_fence_add_callback(f, >cb, dma_fence_chain_cb)) {
@@ -165,8 +164,7 @@ static bool dma_fence_chain_enable_signaling(struct
dma_fence *fence)
static bool dma_fence_chain_signaled(struct dma_fence *fence)
{
dma_fence_chain_for_each(fence, fence) {
- struct dma_fence_chain *chain = to_dma_fence_chain(fence);
- struct dma_fence *f = chain ? chain->fence : fence;
+ struct dma_fence *f = dma_fence_chain_contained(fence);
if (!dma_fence_is_signaled(f)) {
dma_fence_put(fence);
diff --git a/include/linux/dma-fence-chain.h b/include/linux/dma-fence-chain.h
index ee906b659694..10d51bcdf7b7 100644
--- a/include/linux/dma-fence-chain.h
+++ b/include/linux/dma-fence-chain.h
@@ -66,6 +66,21 @@ to_dma_fence_chain(struct dma_fence *fence)
return container_of(fence, struct dma_fence_chain, base);
}
+/**
+ * dma_fence_chain_contained - return the contained fence
+ * @fence: the fence to test
+ *
+ * If the fence is a dma_fence_chain the function returns the fence contained
+ * inside the chain object, otherwise it returns the fence itself.
+ */
+static inline struct dma_fence *
+dma_fence_chain_contained(struct dma_fence *fence)
+{
+ struct dma_fence_chain *chain = to_dma_fence_chain(fence);
+
+ return chain ? chain->fence : fence;
+}
+
/**
* dma_fence_chain_alloc
*
--
2.25.1
[Intel-gfx] [PATCH 06/11] dma-buf: warn about containers in dma_resv object
Drivers should not add containers as shared fences to the dma_resv object, instead each fence should be added individually. Signed-off-by: Christian König Reviewed-by: Daniel Vetter --- drivers/dma-buf/dma-resv.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c index 6dd9a40b55d4..e8a0c1d51da2 100644 --- a/drivers/dma-buf/dma-resv.c +++ b/drivers/dma-buf/dma-resv.c @@ -256,6 +256,11 @@ void dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fence) dma_resv_assert_held(obj); + /* Drivers should not add containers here, instead add each fence +* individually. +*/ + WARN_ON(dma_fence_is_container(fence)); + fobj = dma_resv_shared_list(obj); count = fobj->shared_count; -- 2.25.1
[Intel-gfx] [RFC PATCH 5/5] drm/i915/flat-CCS: handle creation and destruction of flat CCS bo's
When a flat-CCS lmem-bound BO is evicted onto smem for the first time, a
separate swap gem object is created to hold the contents of the CCS block.
It is assumed that, for a flat-CCS bo to be migrated back onto lmem, it
should've begun its life in lmem.
It also handles destruction of the swap bo when the original TTM object
reaches the end of its life.
Signed-off-by: Adrian Larumbe
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 11 +++
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 78 +++-
2 files changed, 87 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 84cae740b4a5..24708d6bfd9c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -474,11 +474,22 @@ static int i915_ttm_shrink(struct drm_i915_gem_object
*obj, unsigned int flags)
static void i915_ttm_delete_mem_notify(struct ttm_buffer_object *bo)
{
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+ struct drm_i915_private *i915 =
+ container_of(bo->bdev, typeof(*i915), bdev);
if (likely(obj)) {
__i915_gem_object_pages_fini(obj);
i915_ttm_free_cached_io_rsgt(obj);
}
+
+ if (HAS_FLAT_CCS(i915) && obj->flat_css.enabled) {
+ struct drm_i915_gem_object *swap_obj = obj->flat_css.swap;
+
+ if (swap_obj) {
+ swap_obj->base.funcs->free(_obj->base);
+ obj->flat_css.swap = NULL;
+ }
+ }
}
static struct i915_refct_sgt *i915_ttm_tt_get_st(struct ttm_tt *ttm)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 1de306c03aaf..3479c4a37bd8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -162,6 +162,56 @@ int i915_ttm_move_notify(struct ttm_buffer_object *bo)
return 0;
}
+static int
+i915_ccs_handle_move(struct drm_i915_gem_object *obj,
+struct ttm_resource *dst_mem)
+{
+ struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
+ struct drm_i915_private *i915 = container_of(bo->bdev, typeof(*i915),
+bdev);
+ struct intel_memory_region *dst_reg;
+ size_t ccs_blk_size;
+ int ret;
+
+ dst_reg = i915_ttm_region(bo->bdev, dst_mem->mem_type);
+ ccs_blk_size = GET_CCS_SIZE(i915, obj->base.size);
+
+ if (dst_reg->type != INTEL_MEMORY_LOCAL &&
+ dst_reg->type != INTEL_MEMORY_SYSTEM) {
+ DRM_DEBUG_DRIVER("Wrong memory region when using flat CCS.\n");
+ return -EINVAL;
+ }
+
+ if (dst_reg->type == INTEL_MEMORY_LOCAL &&
+ (obj->flat_css.swap == NULL ||
!i915_gem_object_has_pages(obj->flat_css.swap))) {
+ /*
+* All BOs begin their life cycle in smem, even if meant to be
+* lmem-bound. Then, upon running the execbuf2 ioctl, get moved
+* onto lmem before first use. Therefore, migrating a flat-CCS
+* lmem-only buffer into lmem means a CCS swap buffer had
already
+* been allocated when first migrating it onto smem from lmem.
+*/
+
+ drm_err(>drm, "BO hasn't been evicted into smem yet\n");
+ return -EINVAL;
+
+ } else if (dst_reg->type == INTEL_MEMORY_SYSTEM &&
+ !obj->flat_css.swap) {
+ /* First time object is swapped out onto smem */
+ obj->flat_css.swap =
+
i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_SMEM],
+ ccs_blk_size, 0, 0);
+ if (IS_ERR(obj->flat_css.swap))
+ return -ENOMEM;
+
+ ret = __i915_gem_object_get_pages(obj->flat_css.swap);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static struct dma_fence *i915_ttm_accel_move(struct ttm_buffer_object *bo,
bool clear,
struct ttm_resource *dst_mem,
@@ -172,9 +222,10 @@ static struct dma_fence *i915_ttm_accel_move(struct
ttm_buffer_object *bo,
struct drm_i915_private *i915 = container_of(bo->bdev, typeof(*i915),
bdev);
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+ struct i915_refct_sgt *ccs_rsgt = NULL;
struct i915_request *rq;
struct ttm_tt *src_ttm = bo->ttm;
- enum i915_cache_level src_level, dst_level;
+ enum i915_cache_level src_level, dst_level, ccs_level;
int ret;
if (!to_gt(i915)->migrate.context || intel_gt_is_wedged(to_gt(i915)))
@@ -196,6 +247,7 @@ static struct dma_fence
[Intel-gfx] [PATCH 04/11] dma-buf: warn about dma_fence_array container rules v2
It's not allowed to nest another dma_fence container into a dma_fence_array or otherwise we can run into recursion. Warn about that when we create a dma_fence_array. v2: fix comment style and typo in the warning pointed out by Thomas Signed-off-by: Christian König Reviewed-by: Daniel Vetter --- drivers/dma-buf/dma-fence-array.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/drivers/dma-buf/dma-fence-array.c b/drivers/dma-buf/dma-fence-array.c index 3e07f961e2f3..cb1bacb5a42b 100644 --- a/drivers/dma-buf/dma-fence-array.c +++ b/drivers/dma-buf/dma-fence-array.c @@ -176,6 +176,20 @@ struct dma_fence_array *dma_fence_array_create(int num_fences, array->base.error = PENDING_ERROR; + /* +* dma_fence_array objects should never contain any other fence +* containers or otherwise we run into recursion and potential kernel +* stack overflow on operations on the dma_fence_array. +* +* The correct way of handling this is to flatten out the array by the +* caller instead. +* +* Enforce this here by checking that we don't create a dma_fence_array +* with any container inside. +*/ + while (num_fences--) + WARN_ON(dma_fence_is_container(fences[num_fences])); + return array; } EXPORT_SYMBOL(dma_fence_array_create); -- 2.25.1
[Intel-gfx] [PATCH 17/54] gpu: drm: replace cpumask_weight with cpumask_empty where appropriate
i915_pmu_cpu_online() calls cpumask_weight() to check if any bit of a given cpumask is set. We can do it more efficiently with cpumask_empty() because cpumask_empty() stops traversing the cpumask as soon as it finds first set bit, while cpumask_weight() counts all bits unconditionally. Signed-off-by: Yury Norov --- drivers/gpu/drm/i915/i915_pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index ea655161793e..1894c876b31d 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -1048,7 +1048,7 @@ static int i915_pmu_cpu_online(unsigned int cpu, struct hlist_node *node) GEM_BUG_ON(!pmu->base.event_init); /* Select the first online CPU as a designated reader. */ - if (!cpumask_weight(_pmu_cpumask)) + if (cpumask_empty(_pmu_cpumask)) cpumask_set_cpu(cpu, _pmu_cpumask); return 0; -- 2.30.2
[Intel-gfx] [RFC PATCH 3/5] drm/i915/flat-CCS: move GET_CCS_SIZE macro into driver-wide header
It has to be used by other files other than low-level migration code.
Signed-off-by: Adrian Larumbe
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 1 -
drivers/gpu/drm/i915/i915_drv.h | 5 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index a210c911905e..716f2f51c7f9 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -16,7 +16,6 @@ struct insert_pte_data {
};
#define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
-#define GET_CCS_SIZE(i915, size) (HAS_FLAT_CCS(i915) ? (size) >> 8 : 0)
static bool engine_supports_migration(struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5623892ceab9..6b890a6674e4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -105,6 +105,7 @@
#include "i915_request.h"
#include "i915_scheduler.h"
#include "gt/intel_timeline.h"
+#include "gt/intel_gpu_commands.h"
#include "i915_vma.h"
@@ -1526,6 +1527,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs)
+#define GET_CCS_SIZE(i915, size) (HAS_FLAT_CCS(i915) ? \
+ DIV_ROUND_UP(size, NUM_CCS_BYTES_PER_BLOCK) \
+ 0)
+
#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
#define HAS_POOLED_EU(dev_priv)(INTEL_INFO(dev_priv)->has_pooled_eu)
--
2.34.1
[Intel-gfx] [PATCH 02/11] drm/amdgpu: use ttm_resource_manager_debug
Instead of calling the debug operation directly. Signed-off-by: Christian König Reviewed-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index fb0d8bffdce2..eac2ff4647e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2076,7 +2076,7 @@ static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused) TTM_PL_VRAM); struct drm_printer p = drm_seq_file_printer(m); - man->func->debug(man, ); + ttm_resource_manager_debug(man, ); return 0; } @@ -2094,7 +2094,7 @@ static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused) TTM_PL_TT); struct drm_printer p = drm_seq_file_printer(m); - man->func->debug(man, ); + ttm_resource_manager_debug(man, ); return 0; } @@ -2105,7 +2105,7 @@ static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused) AMDGPU_PL_GDS); struct drm_printer p = drm_seq_file_printer(m); - man->func->debug(man, ); + ttm_resource_manager_debug(man, ); return 0; } @@ -2116,7 +2116,7 @@ static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused) AMDGPU_PL_GWS); struct drm_printer p = drm_seq_file_printer(m); - man->func->debug(man, ); + ttm_resource_manager_debug(man, ); return 0; } @@ -2127,7 +2127,7 @@ static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused) AMDGPU_PL_OA); struct drm_printer p = drm_seq_file_printer(m); - man->func->debug(man, ); + ttm_resource_manager_debug(man, ); return 0; } -- 2.25.1
[Intel-gfx] [PATCH 03/11] dma-buf: consolidate dma_fence subclass checking
Consolidate the wrapper functions to check for dma_fence
subclasses in the dma_fence header.
This makes it easier to document and also check the different
requirements for fence containers in the subclasses.
Signed-off-by: Christian König
---
include/linux/dma-fence-array.h | 15 +
include/linux/dma-fence-chain.h | 3 +--
include/linux/dma-fence.h | 38 +
3 files changed, 40 insertions(+), 16 deletions(-)
diff --git a/include/linux/dma-fence-array.h b/include/linux/dma-fence-array.h
index 303dd712220f..fec374f69e12 100644
--- a/include/linux/dma-fence-array.h
+++ b/include/linux/dma-fence-array.h
@@ -45,19 +45,6 @@ struct dma_fence_array {
struct irq_work work;
};
-extern const struct dma_fence_ops dma_fence_array_ops;
-
-/**
- * dma_fence_is_array - check if a fence is from the array subsclass
- * @fence: fence to test
- *
- * Return true if it is a dma_fence_array and false otherwise.
- */
-static inline bool dma_fence_is_array(struct dma_fence *fence)
-{
- return fence->ops == _fence_array_ops;
-}
-
/**
* to_dma_fence_array - cast a fence to a dma_fence_array
* @fence: fence to cast to a dma_fence_array
@@ -68,7 +55,7 @@ static inline bool dma_fence_is_array(struct dma_fence *fence)
static inline struct dma_fence_array *
to_dma_fence_array(struct dma_fence *fence)
{
- if (fence->ops != _fence_array_ops)
+ if (!fence || !dma_fence_is_array(fence))
return NULL;
return container_of(fence, struct dma_fence_array, base);
diff --git a/include/linux/dma-fence-chain.h b/include/linux/dma-fence-chain.h
index 54fe3443fd2c..ee906b659694 100644
--- a/include/linux/dma-fence-chain.h
+++ b/include/linux/dma-fence-chain.h
@@ -49,7 +49,6 @@ struct dma_fence_chain {
spinlock_t lock;
};
-extern const struct dma_fence_ops dma_fence_chain_ops;
/**
* to_dma_fence_chain - cast a fence to a dma_fence_chain
@@ -61,7 +60,7 @@ extern const struct dma_fence_ops dma_fence_chain_ops;
static inline struct dma_fence_chain *
to_dma_fence_chain(struct dma_fence *fence)
{
- if (!fence || fence->ops != _fence_chain_ops)
+ if (!fence || !dma_fence_is_chain(fence))
return NULL;
return container_of(fence, struct dma_fence_chain, base);
diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h
index 1ea691753bd3..775cdc0b4f24 100644
--- a/include/linux/dma-fence.h
+++ b/include/linux/dma-fence.h
@@ -587,4 +587,42 @@ struct dma_fence *dma_fence_get_stub(void);
struct dma_fence *dma_fence_allocate_private_stub(void);
u64 dma_fence_context_alloc(unsigned num);
+extern const struct dma_fence_ops dma_fence_array_ops;
+extern const struct dma_fence_ops dma_fence_chain_ops;
+
+/**
+ * dma_fence_is_array - check if a fence is from the array subclass
+ * @fence: the fence to test
+ *
+ * Return true if it is a dma_fence_array and false otherwise.
+ */
+static inline bool dma_fence_is_array(struct dma_fence *fence)
+{
+ return fence->ops == _fence_array_ops;
+}
+
+/**
+ * dma_fence_is_chain - check if a fence is from the chain subclass
+ * @fence: the fence to test
+ *
+ * Return true if it is a dma_fence_chain and false otherwise.
+ */
+static inline bool dma_fence_is_chain(struct dma_fence *fence)
+{
+ return fence->ops == _fence_chain_ops;
+}
+
+/**
+ * dma_fence_is_container - check if a fence is a container for other fences
+ * @fence: the fence to test
+ *
+ * Return true if this fence is a container for other fences, false otherwise.
+ * This is important since we can't build up large fence structure or otherwise
+ * we run into recursion during operation on those fences.
+ */
+static inline bool dma_fence_is_container(struct dma_fence *fence)
+{
+ return dma_fence_is_array(fence) || dma_fence_is_chain(fence);
+}
+
#endif /* __LINUX_DMA_FENCE_H */
--
2.25.1
[Intel-gfx] [RFC PATCH 1/5] drm/i915/flat-CCS: Add GEM bo structure fields for flat-CCS
When a flat-CCS aware bo is evicted from lmem, its control surface will be
written out into smem. This will be done in the shape of a kernel-only bo
attached to the original bo.
Signed-off-by: Adrian Larumbe
---
drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 71e778ecaeb8..9f574e149c58 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -628,6 +628,16 @@ struct drm_i915_gem_object {
void *gvt_info;
};
+
+ /**
+* This is set if the object is lmem-placeable, supports flat
+* CCS and is compressed. In that case, a separate block of
+* stolen lmem memory will contain its compression data.
+*/
+ struct {
+ struct drm_i915_gem_object *swap;
+ bool enabled:1;
+ } flat_css;
};
static inline struct drm_i915_gem_object *
--
2.34.1
[Intel-gfx] [PATCH 09/11] drm/amdgpu: use dma_fence_chain_contained
Instead of manually extracting the fence.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index f7d8487799b2..40e06745fae9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -261,10 +261,9 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, struct
amdgpu_sync *sync,
dma_resv_for_each_fence(, resv, true, f) {
dma_fence_chain_for_each(f, f) {
- struct dma_fence_chain *chain = to_dma_fence_chain(f);
+ struct dma_fence *tmp = dma_fence_chain_contained(f);
- if (amdgpu_sync_test_fence(adev, mode, owner, chain ?
- chain->fence : f)) {
+ if (amdgpu_sync_test_fence(adev, mode, owner, tmp)) {
r = amdgpu_sync_fence(sync, f);
dma_fence_put(f);
if (r)
--
2.25.1
[Intel-gfx] [PATCH] drm/i915/selftests: make static read-only array page_count const
The static array page_count is read-only so it make sense to make
it const.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/i915/selftests/scatterlist.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/scatterlist.c
b/drivers/gpu/drm/i915/selftests/scatterlist.c
index d599186d5b71..a4f2fbb451e2 100644
--- a/drivers/gpu/drm/i915/selftests/scatterlist.c
+++ b/drivers/gpu/drm/i915/selftests/scatterlist.c
@@ -195,7 +195,7 @@ static unsigned int random_page_size_pages(unsigned long n,
struct rnd_state *rnd)
{
/* 4K, 64K, 2M */
- static unsigned int page_count[] = {
+ static const unsigned int page_count[] = {
BIT(12) >> PAGE_SHIFT,
BIT(16) >> PAGE_SHIFT,
BIT(21) >> PAGE_SHIFT,
--
2.33.1
Re: [Intel-gfx] [PATCH] drm/i915: nuke local versions of WARN_ON/WARN_ON_ONCE
On Fri, 21 Jan 2022, Lucas De Marchi wrote: > On Fri, Jan 21, 2022 at 03:29:57PM +0200, Jani Nikula wrote: >>In general, we should avoid redefining kernel macros like this. It can >>get confusing, and what gets used will depend on whether the header is >>included or not. Moreover, we should prefer drm_WARN_ON() and >>drm_WARN_ON_ONCE() anyway, which include the stringified error condition >>in the message. >> >>Signed-off-by: Jani Nikula > > > Reviewed-by: Lucas De Marchi Thanks, pushed to drm-intel-next. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Don't check CT descriptor status before CT write / read
On Fri, 21 Jan 2022, Matthew Brost wrote:
> On Fri, Jan 21, 2022 at 09:28:46AM +0200, Jani Nikula wrote:
>> On Thu, 20 Jan 2022, Matthew Brost wrote:
>> > Don't check CT descriptor status, unless CONFIG_DRM_I915_DEBUG_GUC is
>> > set, before CT write / read as this could result in a read across the
>> > PCIe bus thus adding latency to every CT write / read. On well behavied
>> > systems this vaue should always read as zero. For some reason it doesn't
>> > the CT channel is broken and will eventually recover from a GT reset,
>> > albeit the GT reset will not be triggered immediately by seeing that
>> > descriptor status is non-zero.
>> >
>> > v2:
>> > (CI)
>> > - Fix build error (hide corrupted label in write function behind
>> > CONFIG_DRM_I915_DEBUG_GUC)
>> >
>> > Signed-off-by: Matthew Brost
>> > ---
>> > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 ++
>> > 1 file changed, 6 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> > index de89d40abd38d..948cf31429412 100644
>> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> > @@ -379,8 +379,10 @@ static int ct_write(struct intel_guc_ct *ct,
>> >u32 *cmds = ctb->cmds;
>> >unsigned int i;
>> >
>> > +#ifdef CONFIG_DRM_I915_DEBUG_GUC
>> >if (unlikely(desc->status))
>> >goto corrupted;
>> > +#endif
>>
>> Please don't add #ifdefs inline. You can use
>> IS_ENABLED(CONFIG_DRM_I915_DEBUG_GUC) in if statements, but otherwise
>> the code needs to be split out to a separate function.
>>
>
> Sure, but I feel like I've actually been by someone else to not use the
> IS_ENABLED macro and use ifdefs inlines...
Citation needed.
Basically never use #if/#ifdef inline. Only use them at the top level
like this:
#if IS_ENABLED(CONFIG_FOO)
static int bar(void)
{
/* implementation with foo */
}
#else
static int bar(void)
{
/* implementation without foo */
}
#endif
Sometimes you can avoid the above boilerplate with IS_ENABLED() inline:
if (IS_ENABLED(CONFIG_FOO))
...
Basically if you think #if/#ifdef inline is the easiest, you need to
refactor the code to do it cleanly without them.
BR,
Jani.
>
> Matt
>
>> BR,
>> Jani.
>>
>> >
>> >GEM_BUG_ON(tail > size);
>> >
>> > @@ -445,11 +447,13 @@ static int ct_write(struct intel_guc_ct *ct,
>> >
>> >return 0;
>> >
>> > +#ifdef CONFIG_DRM_I915_DEBUG_GUC
>> > corrupted:
>> >CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
>> > desc->head, desc->tail, desc->status);
>> >ctb->broken = true;
>> >return -EPIPE;
>> > +#endif
>> > }
>> >
>> > /**
>> > @@ -815,8 +819,10 @@ static int ct_read(struct intel_guc_ct *ct, struct
>> > ct_incoming_msg **msg)
>> >if (unlikely(ctb->broken))
>> >return -EPIPE;
>> >
>> > +#ifdef CONFIG_DRM_I915_DEBUG_GUC
>> >if (unlikely(desc->status))
>> >goto corrupted;
>> > +#endif
>> >
>> >GEM_BUG_ON(head > size);
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH 10/11] drm/i915: use dma_fence extractor functions
Instead of manually messing with the data structures use the iterators
and extraction helpers provided by the framework.
This whole handling should essentially go away when boost handling is
implemented in the core dma-buf framework.
Signed-off-by: Christian König
---
drivers/gpu/drm/i915/gem/i915_gem_busy.c | 40 ++--
drivers/gpu/drm/i915/gem/i915_gem_wait.c | 31
drivers/gpu/drm/i915/i915_request.c | 47 +++-
3 files changed, 33 insertions(+), 85 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_busy.c
b/drivers/gpu/drm/i915/gem/i915_gem_busy.c
index 470fdfd61a0f..4ea7a5b26405 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_busy.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_busy.c
@@ -41,6 +41,8 @@ static __always_inline unsigned int
__busy_set_if_active(struct dma_fence *fence, u32 (*flag)(u16 id))
{
const struct i915_request *rq;
+ struct dma_fence *current_fence;
+ unsigned int i;
/*
* We have to check the current hw status of the fence as the uABI
@@ -58,40 +60,22 @@ __busy_set_if_active(struct dma_fence *fence, u32
(*flag)(u16 id))
*
* 2. A single i915 request.
*/
- if (dma_fence_is_array(fence)) {
- struct dma_fence_array *array = to_dma_fence_array(fence);
- struct dma_fence **child = array->fences;
- unsigned int nchild = array->num_fences;
-
- do {
- struct dma_fence *current_fence = *child++;
-
- /* Not an i915 fence, can't be busy per above */
- if (!dma_fence_is_i915(current_fence) ||
- !test_bit(I915_FENCE_FLAG_COMPOSITE,
- _fence->flags)) {
- return 0;
- }
-
- rq = to_request(current_fence);
- if (!i915_request_completed(rq))
- return flag(rq->engine->uabi_class);
- } while (--nchild);
-
- /* All requests in array complete, not busy */
- return 0;
- } else {
- if (!dma_fence_is_i915(fence))
- return 0;
+ dma_fence_array_for_each(current_fence, i, fence) {
- rq = to_request(fence);
- if (i915_request_completed(rq))
+ /* Not an i915 fence, can't be busy per above */
+ if (!dma_fence_is_i915(current_fence) ||
+ !test_bit(I915_FENCE_FLAG_COMPOSITE, _fence->flags))
return 0;
+ rq = to_request(current_fence);
/* Beware type-expansion follies! */
BUILD_BUG_ON(!typecheck(u16, rq->engine->uabi_class));
- return flag(rq->engine->uabi_class);
+ if (!i915_request_completed(rq))
+ return flag(rq->engine->uabi_class);
}
+
+ /* All requests in array complete, not busy */
+ return 0;
}
static __always_inline unsigned int
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
index dab3d30c09a0..13f37b6aedf7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
@@ -72,11 +72,6 @@ static void fence_set_priority(struct dma_fence *fence,
rcu_read_unlock();
}
-static inline bool __dma_fence_is_chain(const struct dma_fence *fence)
-{
- return fence->ops == _fence_chain_ops;
-}
-
void i915_gem_fence_wait_priority(struct dma_fence *fence,
const struct i915_sched_attr *attr)
{
@@ -85,25 +80,15 @@ void i915_gem_fence_wait_priority(struct dma_fence *fence,
local_bh_disable();
- /* Recurse once into a fence-array */
- if (dma_fence_is_array(fence)) {
- struct dma_fence_array *array = to_dma_fence_array(fence);
- int i;
+ /* The chain is ordered; if we boost the last, we boost all */
+ dma_fence_chain_for_each(fence, fence) {
+ struct dma_fence *array, *element;
+ unsigned int i;
- for (i = 0; i < array->num_fences; i++)
- fence_set_priority(array->fences[i], attr);
- } else if (__dma_fence_is_chain(fence)) {
- struct dma_fence *iter;
-
- /* The chain is ordered; if we boost the last, we boost all */
- dma_fence_chain_for_each(iter, fence) {
- fence_set_priority(to_dma_fence_chain(iter)->fence,
- attr);
- break;
- }
- dma_fence_put(iter);
- } else {
- fence_set_priority(fence, attr);
+ /* Recurse once into a fence-array */
+ array = dma_fence_chain_contained(fence);
+
[Intel-gfx] [RFC PATCH 4/5] drm/i915/flat-CCS: handle CCS block blit for bo migrations
Because the smem-evicted bo that holds the CCS block has to be blitted
separately from the original compressed bo, two sets of PTEs have to
be emitted for every bo copy.
This commit is partially based off another commit from Ramalingam C
, currently under discussion.
Signed-off-by: Adrian Larumbe
---
drivers/gpu/drm/i915/gt/intel_migrate.c| 288 +++--
drivers/gpu/drm/i915/gt/intel_migrate.h| 2 +
drivers/gpu/drm/i915/gt/selftest_migrate.c | 3 +-
3 files changed, 207 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 716f2f51c7f9..da0fcc42c43c 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -447,14 +447,183 @@ static bool wa_1209644611_applies(int ver, u32 size)
return height % 4 == 3 && height <= 8;
}
+static inline u32 *i915_flush_dw(u32 *cmd, u64 dst, u32 flags)
+{
+ /* Mask the 3 LSB to use the PPGTT address space */
+ *cmd++ = MI_FLUSH_DW | flags;
+ *cmd++ = lower_32_bits(dst);
+ *cmd++ = upper_32_bits(dst);
+
+ return cmd;
+}
+
+static u32 calc_ctrl_surf_instr_size(struct drm_i915_private *i915, int
+size)
+{
+ u32 num_cmds, num_blks, total_size;
+
+ if (!GET_CCS_SIZE(i915, size))
+ return 0;
+
+ /*
+* XY_CTRL_SURF_COPY_BLT transfers CCS in 256 byte
+* blocks. one XY_CTRL_SURF_COPY_BLT command can
+* trnasfer upto 1024 blocks.
+*/
+ num_blks = (GET_CCS_SIZE(i915, size) +
+ (NUM_CCS_BYTES_PER_BLOCK - 1)) >> 8;
+ num_cmds = (num_blks + (NUM_CCS_BLKS_PER_XFER - 1)) >> 10;
+ total_size = (XY_CTRL_SURF_INSTR_SIZE) * num_cmds;
+
+ /*
+* We need to add a flush before and after
+* XY_CTRL_SURF_COPY_BLT
+*/
+ total_size += 2 * MI_FLUSH_DW_SIZE;
+ return total_size;
+}
+
+static u32 *_i915_ctrl_surf_copy_blt(u32 *cmd, u64 src_addr, u64 dst_addr,
+u8 src_mem_access, u8 dst_mem_access,
+int src_mocs, int dst_mocs,
+u16 num_ccs_blocks)
+{
+ int i = num_ccs_blocks;
+
+ /*
+* The XY_CTRL_SURF_COPY_BLT instruction is used to copy the CCS
+* data in and out of the CCS region.
+*
+* We can copy at most 1024 blocks of 256 bytes using one
+* XY_CTRL_SURF_COPY_BLT instruction.
+*
+* In case we need to copy more than 1024 blocks, we need to add
+* another instruction to the same batch buffer.
+*
+* 1024 blocks of 256 bytes of CCS represent a total 256KB of CCS.
+*
+* 256 KB of CCS represents 256 * 256 KB = 64 MB of LMEM.
+*/
+ do {
+ /*
+* We use logical AND with 1023 since the size field
+* takes values which is in the range of 0 - 1023
+*/
+ *cmd++ = ((XY_CTRL_SURF_COPY_BLT) |
+ (src_mem_access << SRC_ACCESS_TYPE_SHIFT) |
+ (dst_mem_access << DST_ACCESS_TYPE_SHIFT) |
+ (((i - 1) & 1023) << CCS_SIZE_SHIFT));
+ *cmd++ = lower_32_bits(src_addr);
+ *cmd++ = ((upper_32_bits(src_addr) & 0x) |
+ (src_mocs << XY_CTRL_SURF_MOCS_SHIFT));
+ *cmd++ = lower_32_bits(dst_addr);
+ *cmd++ = ((upper_32_bits(dst_addr) & 0x) |
+ (dst_mocs << XY_CTRL_SURF_MOCS_SHIFT));
+ src_addr += SZ_64M;
+ dst_addr += SZ_64M;
+ i -= NUM_CCS_BLKS_PER_XFER;
+ } while (i > 0);
+
+ return cmd;
+}
+
+
+static int emit_ccs(struct i915_request *rq,
+ struct sgt_dma *it_lmem,
+ enum i915_cache_level lmem_cache_level,
+ struct sgt_dma *it_css,
+ enum i915_cache_level css_cache_level,
+ bool lmem2smem,
+ int size)
+{
+ struct drm_i915_private *i915 = rq->engine->i915;
+ u32 num_ccs_blks = (GET_CCS_SIZE(i915, size) +
+ NUM_CCS_BYTES_PER_BLOCK - 1) >> 8;
+ struct sgt_dma *it_src, *it_dst;
+ enum i915_cache_level src_cache_level;
+ enum i915_cache_level dst_cache_level;
+ u8 src_access, dst_access;
+ u32 src_offset, dst_offset;
+ u32 ccs_ring_size;
+ int err, len;
+ u32 *cs;
+
+ ccs_ring_size = calc_ctrl_surf_instr_size(i915, size);
+
+ err = emit_no_arbitration(rq);
+ if (err)
+ return -EINVAL;
+
+ src_offset = 0;
+ dst_offset = CHUNK_SZ;
+ if (HAS_64K_PAGES(i915)) {
+ src_offset = 0;
+ dst_offset = 0;
+ if (lmem2smem)
+ src_offset = CHUNK_SZ;
+ else
+
Re: [Intel-gfx] [PATCH V2 0/7] DRM kmap() fixes and kmap_local_page() conversions
Am 24.01.22 um 02:54 schrieb ira.we...@intel.com: From: Ira Weiny Changes from V1: Use memcpy_to_page() where appropriate Rebased to latest The kmap() call may cause issues with work being done with persistent memory. For this and other reasons it is being deprecated. I'm really wondering how we should be able to implement the kernel mapping without kmap in TTM. This series starts by converting the last easy kmap() uses in the drm tree to kmap_local_page(). The final 2 patches fix bugs found while working on the ttm_bo_kmap_ttm() conversion. They are valid fixes but were found via code inspection not because of any actual bug so don't require a stable tag.[1] There is one more call to kmap() used in ttm_bo_kmap_ttm(). Unfortunately, fixing this is not straight forward so it is left to future work.[2] Patches #2, #4, #6 and #7 are Reviewed-by: Christian König How to you now want to push those upstream? I can pick them up for the AMD tree like Daniel suggested or you can push them through something else. Regards, Christian. [1] https://lore.kernel.org/lkml/fb71af05-a889-8f6e-031b-426b58a64...@amd.com/ [2] https://lore.kernel.org/lkml/20211215210949.gw3538...@iweiny-desk2.sc.intel.com/ Ira Weiny (7): drm/i915: Replace kmap() with kmap_local_page() drm/amd: Replace kmap() with kmap_local_page() drm/gma: Remove calls to kmap() drm/radeon: Replace kmap() with kmap_local_page() drm/msm: Alter comment to use kmap_local_page() drm/amdgpu: Ensure kunmap is called on error drm/radeon: Ensure kunmap is called on error drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 1 + drivers/gpu/drm/gma500/gma_display.c | 6 ++ drivers/gpu/drm/gma500/mmu.c | 8 drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 6 ++ drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 8 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 4 ++-- drivers/gpu/drm/i915/gt/shmem_utils.c | 7 ++- drivers/gpu/drm/i915/i915_gem.c | 8 drivers/gpu/drm/i915/i915_gpu_error.c | 4 ++-- drivers/gpu/drm/msm/msm_gem_submit.c | 4 ++-- drivers/gpu/drm/radeon/radeon_ttm.c | 4 ++-- drivers/gpu/drm/radeon/radeon_uvd.c | 1 + 13 files changed, 32 insertions(+), 37 deletions(-) -- 2.31.1
[Intel-gfx] [PATCH 07/11] dma-buf: Add dma_fence_array_for_each (v2)
From: Christian König
Add a helper to iterate over all fences in a dma_fence_array object.
v2 (Jason Ekstrand)
- Return NULL from dma_fence_array_first if head == NULL. This matches
the iterator behavior of dma_fence_chain_for_each in that it iterates
zero times if head == NULL.
- Return NULL from dma_fence_array_next if index > array->num_fences.
Signed-off-by: Jason Ekstrand
Reviewed-by: Jason Ekstrand
Reviewed-by: Christian König
Cc: Daniel Vetter
Cc: Maarten Lankhorst
---
drivers/dma-buf/dma-fence-array.c | 27 +++
include/linux/dma-fence-array.h | 17 +
2 files changed, 44 insertions(+)
diff --git a/drivers/dma-buf/dma-fence-array.c
b/drivers/dma-buf/dma-fence-array.c
index cb1bacb5a42b..52b85d292383 100644
--- a/drivers/dma-buf/dma-fence-array.c
+++ b/drivers/dma-buf/dma-fence-array.c
@@ -219,3 +219,30 @@ bool dma_fence_match_context(struct dma_fence *fence, u64
context)
return true;
}
EXPORT_SYMBOL(dma_fence_match_context);
+
+struct dma_fence *dma_fence_array_first(struct dma_fence *head)
+{
+ struct dma_fence_array *array;
+
+ if (!head)
+ return NULL;
+
+ array = to_dma_fence_array(head);
+ if (!array)
+ return head;
+
+ return array->fences[0];
+}
+EXPORT_SYMBOL(dma_fence_array_first);
+
+struct dma_fence *dma_fence_array_next(struct dma_fence *head,
+ unsigned int index)
+{
+ struct dma_fence_array *array = to_dma_fence_array(head);
+
+ if (!array || index >= array->num_fences)
+ return NULL;
+
+ return array->fences[index];
+}
+EXPORT_SYMBOL(dma_fence_array_next);
diff --git a/include/linux/dma-fence-array.h b/include/linux/dma-fence-array.h
index fec374f69e12..e34dcb0bb462 100644
--- a/include/linux/dma-fence-array.h
+++ b/include/linux/dma-fence-array.h
@@ -61,6 +61,19 @@ to_dma_fence_array(struct dma_fence *fence)
return container_of(fence, struct dma_fence_array, base);
}
+/**
+ * dma_fence_array_for_each - iterate over all fences in array
+ * @fence: current fence
+ * @index: index into the array
+ * @head: potential dma_fence_array object
+ *
+ * Test if @array is a dma_fence_array object and if yes iterate over all
fences
+ * in the array. If not just iterate over the fence in @array itself.
+ */
+#define dma_fence_array_for_each(fence, index, head) \
+ for (index = 0, fence = dma_fence_array_first(head); fence; \
+++(index), fence = dma_fence_array_next(head, index))
+
struct dma_fence_array *dma_fence_array_create(int num_fences,
struct dma_fence **fences,
u64 context, unsigned seqno,
@@ -68,4 +81,8 @@ struct dma_fence_array *dma_fence_array_create(int num_fences,
bool dma_fence_match_context(struct dma_fence *fence, u64 context);
+struct dma_fence *dma_fence_array_first(struct dma_fence *head);
+struct dma_fence *dma_fence_array_next(struct dma_fence *head,
+ unsigned int index);
+
#endif /* __LINUX_DMA_FENCE_ARRAY_H */
--
2.25.1
[Intel-gfx] [RFC PATCH 2/5] drm/i915/flat-CCS: Add flat CCS plane capabilities and modifiers
Adds frame buffer support code for flat-CCS devices, like DG2. A flat-CCS
modifier is attached to a fb object that contains the original bo by means
of the drmModeAddFB2WithModifiers drm API call.
Signed-off-by: Adrian Larumbe
---
drivers/gpu/drm/i915/display/intel_fb.c | 36 ++---
drivers/gpu/drm/i915/display/intel_fb.h | 1 +
2 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 72040f580911..6f998d1956bb 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -158,19 +158,24 @@ static const struct intel_modifier_desc intel_modifiers[]
= {
{
.modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
.display_ver = { 13, 14 },
- .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
+ .plane_caps = INTEL_PLANE_CAP_TILING_4 |
+ INTEL_PLANE_CAP_CCS_MC |
+ INTEL_PLANE_CAP_DG2_CCS,
}, {
.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
.display_ver = { 13, 14 },
- .plane_caps = INTEL_PLANE_CAP_TILING_4 |
INTEL_PLANE_CAP_CCS_RC_CC,
-
+ .plane_caps = INTEL_PLANE_CAP_TILING_4 |
+ INTEL_PLANE_CAP_CCS_RC_CC |
+ INTEL_PLANE_CAP_DG2_CCS,
.ccs.cc_planes = BIT(1),
FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats),
}, {
.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
.display_ver = { 13, 14 },
- .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC,
+ .plane_caps = INTEL_PLANE_CAP_TILING_4 |
+ INTEL_PLANE_CAP_CCS_RC |
+ INTEL_PLANE_CAP_DG2_CCS,
}, {
.modifier = I915_FORMAT_MOD_4_TILED,
.display_ver = { 13, 14 },
@@ -313,6 +318,20 @@ bool intel_fb_is_ccs_modifier(u64 modifier)
INTEL_PLANE_CAP_CCS_MASK);
}
+/**
+ * if (intel_fb_is_dg2_ccs_modifier): Check if a modifier is a DG2 CCS
modifier type
+ * @modifier: Modifier to check
+ *
+ * Returns:
+ * Returns %true if @modifier is a render, render with color clear or
+ * media compression modifier compatible with DG2 devices.
+ */
+bool intel_fb_is_dg2_ccs_modifier(u64 modifier)
+{
+ return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,
+ INTEL_PLANE_CAP_DG2_CCS);
+}
+
/**
* intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC
modifier type
* @modifier: Modifier to check
@@ -2000,6 +2019,15 @@ int intel_framebuffer_init(struct intel_framebuffer
*intel_fb,
intel_fb->dpt_vm = vm;
}
+ /*
+* In devices with flat CCS support, a compressed buffer object
+* will need to shuffle its CCS block back and forth between lmem
+* and smem at object migration events.
+*/
+ if (intel_fb_is_dg2_ccs_modifier(fb->modifier) &&
HAS_FLAT_CCS(dev_priv))
+ if (!i915_gem_object_migratable(obj) &&
i915_gem_object_is_lmem(obj))
+ obj->flat_css.enabled = true;
+
ret = drm_framebuffer_init(_priv->drm, fb, _fb_funcs);
if (ret) {
drm_err(_priv->drm, "framebuffer init failed %d\n", ret);
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
b/drivers/gpu/drm/i915/display/intel_fb.h
index 12386f13a4e0..5bd74ff9a449 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -28,6 +28,7 @@ struct intel_plane_state;
#define INTEL_PLANE_CAP_TILING_Y BIT(4)
#define INTEL_PLANE_CAP_TILING_Yf BIT(5)
#define INTEL_PLANE_CAP_TILING_4 BIT(6)
+#define INTEL_PLANE_CAP_DG2_CCSBIT(7)
bool intel_fb_is_ccs_modifier(u64 modifier);
bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
--
2.34.1
[Intel-gfx] Add WARN_ON nested dma_fence containers
Hi guys, as previously discussed only dma_fence_chain with its previous fence is actually made to build up larger dma_fence structures. Everything else should either flatten all fences into a single dma_fence_array or just add each fence separately to the dma_resv object. Please review and/or comment, Christian.
[Intel-gfx] [PATCH v2] drm/i915/selftests: Fix NULL vs IS_ERR checking for kernel_context
Since i915_gem_create_context() function return error pointers,
the kernel_context() function does not return null, It returns error
pointers too. Using IS_ERR() to check the return value to fix this.
Signed-off-by: Miaoqian Lin
---
Changes in v2:
- clean up unneeded initialization of err.
---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 43 ++--
1 file changed, 30 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index b367ecfa42de..0d453ddcede4 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -1531,7 +1531,7 @@ static int live_busywait_preempt(void *arg)
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
enum intel_engine_id id;
- int err = -ENOMEM;
+ int err;
u32 *map;
/*
@@ -1540,13 +1540,16 @@ static int live_busywait_preempt(void *arg)
*/
ctx_hi = kernel_context(gt->i915, NULL);
- if (!ctx_hi)
- return -ENOMEM;
+ if (IS_ERR(ctx_hi))
+ return IS_ERR(ctx_hi);
+
ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY;
ctx_lo = kernel_context(gt->i915, NULL);
- if (!ctx_lo)
+ if (IS_ERR(ctx_lo)) {
+ err = PTR_ERR(ctx_lo);
goto err_ctx_hi;
+ }
ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY;
obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
@@ -1742,13 +1745,17 @@ static int live_preempt(void *arg)
goto err_spin_hi;
ctx_hi = kernel_context(gt->i915, NULL);
- if (!ctx_hi)
+ if (IS_ERR(ctx_hi)) {
+ err = PTR_ERR(ctx_hi);
goto err_spin_lo;
+ }
ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY;
ctx_lo = kernel_context(gt->i915, NULL);
- if (!ctx_lo)
+ if (IS_ERR(ctx_lo)) {
+ err = PTR_ERR(ctx_lo);
goto err_ctx_hi;
+ }
ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY;
for_each_engine(engine, gt, id) {
@@ -1834,12 +1841,16 @@ static int live_late_preempt(void *arg)
goto err_spin_hi;
ctx_hi = kernel_context(gt->i915, NULL);
- if (!ctx_hi)
+ if (IS_ERR(ctx_hi)) {
+ err = PTR_ERR(ctx_hi);
goto err_spin_lo;
+ }
ctx_lo = kernel_context(gt->i915, NULL);
- if (!ctx_lo)
+ if (IS_ERR(ctx_lo)) {
+ err = PTR_ERR(ctx_lo);
goto err_ctx_hi;
+ }
/* Make sure ctx_lo stays before ctx_hi until we trigger preemption. */
ctx_lo->sched.priority = 1;
@@ -1928,8 +1939,8 @@ struct preempt_client {
static int preempt_client_init(struct intel_gt *gt, struct preempt_client *c)
{
c->ctx = kernel_context(gt->i915, NULL);
- if (!c->ctx)
- return -ENOMEM;
+ if (IS_ERR(c->ctx))
+ return PTR_ERR(c->ctx);
if (igt_spinner_init(>spin, gt))
goto err_ctx;
@@ -3385,13 +3396,17 @@ static int live_preempt_timeout(void *arg)
return -ENOMEM;
ctx_hi = kernel_context(gt->i915, NULL);
- if (!ctx_hi)
+ if (IS_ERR(ctx_hi)) {
+ err = PTR_ERR(ctx_hi);
goto err_spin_lo;
+ }
ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY;
ctx_lo = kernel_context(gt->i915, NULL);
- if (!ctx_lo)
+ if (IS_ERR(ctx_lo)) {
+ err = PTR_ERR(ctx_lo);
goto err_ctx_hi;
+ }
ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY;
for_each_engine(engine, gt, id) {
@@ -3683,8 +3698,10 @@ static int live_preempt_smoke(void *arg)
for (n = 0; n < smoke.ncontext; n++) {
smoke.contexts[n] = kernel_context(smoke.gt->i915, NULL);
- if (!smoke.contexts[n])
+ if (IS_ERR(smoke.contexts[n])) {
+ err = PTR_ERR(smoke.contexts[n]);
goto err_ctx;
+ }
}
for (n = 0; n < ARRAY_SIZE(phase); n++) {
--
2.17.1
[Intel-gfx] [RFC PATCH 0/5] Add basic support for flat-CCS bo evictions
This series is a first attempt at handling the eviction of flat-CCS compressed lmem-placed bo's. The official specification of flat CCS behaviour dictates that: "Flat CCS data needs to be cleared when a lmem object is allocated. And CCS data can be copied in and out of CCS region through XY_CTRL_SURF_COPY_BLT. CPU can't access the CCS data directly. When we exaust the lmem, if the object's placements support smem, then we can directly decompress the compressed lmem object into smem and start using it from smem itself. But when we need to swapout the compressed lmem object into a smem region though objects' placement doesn't support smem, then we copy the lmem content as it is into smem region along with ccs data (using XY_CTRL_SURF_COPY_BLT). When the object is referred, lmem content will be swaped in along with restoration of the CCS data (using XY_CTRL_SURF_COPY_BLT) at corresponding location." Design decisions: - A separate GEM bo of type `ttm_bo_type_kernel` is created to hold the contents of the CCS block when an lmem-only object is evicted onto smem. This is because this bo should never be mmap'able onto user space. - Whether a bo is meant to contain flat-CCS compressed data is marked by adding specific surface modifiers that describe a FB object which contains the relevant bo. This is done through a specific DRM library call. - At an eviction event, the bo's buffer data and its corresponding CCS block have to be moved between smem and lmem in two separate blit operations. Because of my poor knowledge of the blit unit, it's very likely that the way I programmed it is somehow wrong. - At the moment, migrating a flat-CCS lmem-only object from smem back onto lmem will fail if its flat-CCS swap bo had not been created. However, a bo lifecycle begins in smem when it's created, even its original placement specifies lmem only. Between the time that a bo is freshly created and an execbuf2 ioctl actually moves it onto lmem and allocates its backing storage, the user might've called mmap on it, a scenario which I haven't yet accounted for. Part of the blitting engine code was borrowed from Ramalingam C , who has been working in parallel on the same problem, although in a slightly different approach. For testing, a flat-CCS driver self-test is under preparation. Adrian Larumbe (5): drm/i915/flat-CCS: Add GEM BO structure fields for flat-CCS drm/i915/flat-CCS: Add flat CCS plane capabilities and modifiers drm/i915/flat-CCS: move GET_CCS_SIZE macro into driver-wide header drm/i915/flat-CCS: handle CCS block blit for bo migrations drm/i915/flat-CCS: handle creation and destruction of flat CCS bo's drivers/gpu/drm/i915/display/intel_fb.c | 36 ++- drivers/gpu/drm/i915/display/intel_fb.h | 1 + .../gpu/drm/i915/gem/i915_gem_object_types.h | 10 + drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 11 + drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 78 - drivers/gpu/drm/i915/gt/intel_migrate.c | 289 -- drivers/gpu/drm/i915/gt/intel_migrate.h | 2 + drivers/gpu/drm/i915/gt/selftest_migrate.c| 3 +- drivers/gpu/drm/i915/i915_drv.h | 5 + 9 files changed, 342 insertions(+), 93 deletions(-) -- 2.34.1
[Intel-gfx] [PATCH 11/11] drm/vmwgfx: remove vmw_wait_dma_fence
Decomposing fence containers don't seem to make any sense here.
So just remove the function entirely and call dma_fence_wait() directly.
Signed-off-by: Christian König
Cc: VMware Graphics
Cc: Zack Rusin
---
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 2 +-
drivers/gpu/drm/vmwgfx/vmwgfx_fence.c | 46 -
drivers/gpu/drm/vmwgfx/vmwgfx_fence.h | 3 --
3 files changed, 1 insertion(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index 44ca23b0ea4e..0ff28f0e3eb4 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -4500,7 +4500,7 @@ int vmw_execbuf_ioctl(struct drm_device *dev, void *data,
goto mksstats_out;
}
- ret = vmw_wait_dma_fence(dev_priv->fman, in_fence);
+ ret = dma_fence_wait(in_fence, true);
if (ret)
goto out;
}
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c
index c60d395f9e2e..430f83a1847c 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c
@@ -621,52 +621,6 @@ int vmw_user_fence_create(struct drm_file *file_priv,
return ret;
}
-
-/**
- * vmw_wait_dma_fence - Wait for a dma fence
- *
- * @fman: pointer to a fence manager
- * @fence: DMA fence to wait on
- *
- * This function handles the case when the fence is actually a fence
- * array. If that's the case, it'll wait on each of the child fence
- */
-int vmw_wait_dma_fence(struct vmw_fence_manager *fman,
- struct dma_fence *fence)
-{
- struct dma_fence_array *fence_array;
- int ret = 0;
- int i;
-
-
- if (dma_fence_is_signaled(fence))
- return 0;
-
- if (!dma_fence_is_array(fence))
- return dma_fence_wait(fence, true);
-
- /* From i915: Note that if the fence-array was created in
-* signal-on-any mode, we should *not* decompose it into its individual
-* fences. However, we don't currently store which mode the fence-array
-* is operating in. Fortunately, the only user of signal-on-any is
-* private to amdgpu and we should not see any incoming fence-array
-* from sync-file being in signal-on-any mode.
-*/
-
- fence_array = to_dma_fence_array(fence);
- for (i = 0; i < fence_array->num_fences; i++) {
- struct dma_fence *child = fence_array->fences[i];
-
- ret = dma_fence_wait(child, true);
-
- if (ret < 0)
- return ret;
- }
-
- return 0;
-}
-
-
/*
* vmw_fence_fifo_down - signal all unsignaled fence objects.
*/
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fence.h
b/drivers/gpu/drm/vmwgfx/vmwgfx_fence.h
index 079ab4f3ba51..a7eee579c76a 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fence.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fence.h
@@ -104,9 +104,6 @@ extern int vmw_user_fence_create(struct drm_file *file_priv,
struct vmw_fence_obj **p_fence,
uint32_t *p_handle);
-extern int vmw_wait_dma_fence(struct vmw_fence_manager *fman,
- struct dma_fence *fence);
-
extern void vmw_fence_fifo_up(struct vmw_fence_manager *fman);
extern void vmw_fence_fifo_down(struct vmw_fence_manager *fman);
--
2.25.1
[Intel-gfx] [PATCH 05/11] dma-buf: Warn about dma_fence_chain container rules v2
Chaining of dma_fence_chain objects is only allowed through the prev fence and not through the contained fence. Warn about that when we create a dma_fence_chain. v2: fix comment style Signed-off-by: Christian König Reviewed-by: Daniel Vetter Reviewed-by: Thomas Hellström --- drivers/dma-buf/dma-fence-chain.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-fence-chain.c index 1b4cb3e5cec9..084c6927b735 100644 --- a/drivers/dma-buf/dma-fence-chain.c +++ b/drivers/dma-buf/dma-fence-chain.c @@ -254,5 +254,14 @@ void dma_fence_chain_init(struct dma_fence_chain *chain, dma_fence_init(>base, _fence_chain_ops, >lock, context, seqno); + + /* +* Chaining dma_fence_chain container together is only allowed through +* the prev fence and not through the contained fence. +* +* The correct way of handling this is to flatten out the fence +* structure into a dma_fence_array by the caller instead. +*/ + WARN_ON(dma_fence_is_chain(fence)); } EXPORT_SYMBOL(dma_fence_chain_init); -- 2.25.1
[Intel-gfx] [PATCH] drm/i915/overlay: Prevent divide by zero bugs in scaling
Smatch detected a divide by zero bug in check_overlay_scaling().
drivers/gpu/drm/i915/display/intel_overlay.c:976 check_overlay_scaling()
error: potential divide by zero bug '/ rec->dst_height'.
drivers/gpu/drm/i915/display/intel_overlay.c:980 check_overlay_scaling()
error: potential divide by zero bug '/ rec->dst_width'.
Prevent this by ensuring that the dst height and width are non-zero.
Fixes: 02e792fbaadb ("drm/i915: implement drmmode overlay support v4")
Signed-off-by: Dan Carpenter
---
>From static analysis. Not tested.
drivers/gpu/drm/i915/display/intel_overlay.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
b/drivers/gpu/drm/i915/display/intel_overlay.c
index 1a376e9a1ff3..d610e48cab94 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -959,6 +959,9 @@ static int check_overlay_dst(struct intel_overlay *overlay,
const struct intel_crtc_state *pipe_config =
overlay->crtc->config;
+ if (rec->dst_height == 0 || rec->dst_width == 0)
+ return -EINVAL;
+
if (rec->dst_x < pipe_config->pipe_src_w &&
rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
rec->dst_y < pipe_config->pipe_src_h &&
--
2.20.1
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: drm device based logging conversions (rev3)
== Series Details ==
Series: drm/i915/display: drm device based logging conversions (rev3)
URL : https://patchwork.freedesktop.org/series/99151/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11120_full -> Patchwork_22077_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22077_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22077_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 11)
--
Additional (1): shard-tglu
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_22077_full:
### CI changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* boot:
- {shard-tglu}: NOTRUN -> ([PASS][1], [FAIL][2], [PASS][3],
[PASS][4], [PASS][5], [PASS][6], [PASS][7])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/shard-tglu-3/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/shard-tglu-3/boot.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/shard-tglu-2/boot.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/shard-tglu-2/boot.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/shard-tglu-1/boot.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/shard-tglu-1/boot.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/shard-tglu-1/boot.html
### IGT changes ###
Possible regressions
* igt@kms_cursor_crc@pipe-a-cursor-128x128-sliding:
- shard-tglb: [PASS][8] -> [INCOMPLETE][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-tglb1/igt@kms_cursor_...@pipe-a-cursor-128x128-sliding.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/shard-tglb8/igt@kms_cursor_...@pipe-a-cursor-128x128-sliding.html
Known issues
Here are the changes found in Patchwork_22077_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-skl: [PASS][10] -> [INCOMPLETE][11] ([i915#4793])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-skl4/igt@gem_ctx_isolation@preservation...@vcs0.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/shard-skl4/igt@gem_ctx_isolation@preservation...@vcs0.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-skl: NOTRUN -> [TIMEOUT][12] ([i915#3063])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/shard-skl9/igt@gem_...@in-flight-contexts-10ms.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-skl: [PASS][13] -> [TIMEOUT][14] ([i915#3063])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-skl9/igt@gem_...@in-flight-contexts-1us.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/shard-skl7/igt@gem_...@in-flight-contexts-1us.html
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [PASS][15] -> [SKIP][16] ([i915#4525]) +1 similar
issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-iclb1/igt@gem_exec_balan...@parallel-keep-submit-fence.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/shard-iclb6/igt@gem_exec_balan...@parallel-keep-submit-fence.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#2842]) +1 similar
issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-glk8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/shard-glk1/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][19] -> [FAIL][20] ([i915#2842]) +1 similar
issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/shard-kbl7/igt@gem_exec_fair@basic-n...@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][21] -> [FAIL][22] ([i915#2842])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-tglb7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22077/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [PASS][23] -> [FAIL][24] ([i915#2842])
[23]:
[Intel-gfx] [PATCH] drm/i915: Lock dpt_obj around set_cache_level.
set_cache_level may unbind the object, which will result in the below
lockdep splat:
<6> [184.578145] [IGT] kms_addfb_basic: starting subtest
addfb25-framebuffer-vs-set-tiling
<4> [184.578220] [ cut here ]
<4> [184.578221] WARN_ON(debug_locks &&
!(lock_is_held(&(&((obj)->base.resv)->lock.base)->dep_map) != 0))
<4> [184.578237] WARNING: CPU: 6 PID: 5544 at
drivers/gpu/drm/i915/i915_gem.c:123 i915_gem_object_unbind+0x4a9/0x510 [i915]
<4> [184.578323] Modules linked in: vgem drm_shmem_helper snd_hda_codec_hdmi
i915 mei_hdcp x86_pkg_temp_thermal snd_hda_intel coretemp crct10dif_pclmul
snd_intel_dspcfg crc32_pclmul ttm snd_hda_codec ghash_clmulni_intel snd_hwdep
drm_kms_helper snd_hda_core e1000e mei_me syscopyarea ptp snd_pcm sysfillrect
mei pps_core sysimgblt fb_sys_fops prime_numbers intel_lpss_pci smsc75xx usbnet
mii
<4> [184.578349] CPU: 6 PID: 5544 Comm: kms_addfb_basic Not tainted
5.16.0-CI-Patchwork_22006+ #1
<4> [184.578351] Hardware name: Intel Corporation Alder Lake Client
Platform/AlderLake-P DDR4 RVP, BIOS ADLPFWI1.R00.2422.A00.2110131104 10/13/2021
<4> [184.578352] RIP: 0010:i915_gem_object_unbind+0x4a9/0x510 [i915]
<4> [184.578424] Code: 00 be ff ff ff ff 48 8d 78 68 e8 a2 6e 2b e1 85 c0 0f 85
b1 fb ff ff 48 c7 c6 48 37 9e a0 48 c7 c7 d9 fc a1 a0 e8 a3 54 26 e1 <0f> 0b e9
97 fb ff ff 31 ed 48 8b 5c 24 58 65 48 33 1c 25 28 00 00
<4> [184.578426] RSP: 0018:c900013b3b68 EFLAGS: 00010286
<4> [184.578428] RAX: RBX: c900013b3bb0 RCX:
0001
<4> [184.578429] RDX: 8001 RSI: 8230b42d RDI:
<4> [184.578430] RBP: 888120e1 R08: R09:
c0007fff
<4> [184.578431] R10: 0001 R11: c900013b3980 R12:
8881176ea740
<4> [184.578432] R13: 888120e1 R14: R15:
0001
<4> [184.578433] FS: 7f65074f5e40() GS:8f30()
knlGS:
<4> [184.578435] CS: 0010 DS: ES: CR0: 80050033
<4> [184.578436] CR2: 7fff4420ede8 CR3: 00010c2f2005 CR4:
00770ee0
<4> [184.578437] PKRU: 5554
<4> [184.578438] Call Trace:
<4> [184.578439]
<4> [184.578440] ? dma_resv_iter_first_unlocked+0x78/0xf0
<4> [184.578447] intel_dpt_create+0x88/0x220 [i915]
<4> [184.578530] intel_framebuffer_init+0x5b8/0x620 [i915]
<4> [184.578612] intel_framebuffer_create+0x3d/0x60 [i915]
<4> [184.578691] intel_user_framebuffer_create+0x18f/0x2c0 [i915]
<4> [184.578775] drm_internal_framebuffer_create+0x36d/0x4c0
<4> [184.578779] drm_mode_addfb2+0x2f/0xd0
<4> [184.578781] ? drm_mode_addfb_ioctl+0x10/0x10
<4> [184.578784] drm_ioctl_kernel+0xac/0x140
<4> [184.578787] drm_ioctl+0x201/0x3d0
<4> [184.578789] ? drm_mode_addfb_ioctl+0x10/0x10
<4> [184.578796] __x64_sys_ioctl+0x6a/0xa0
<4> [184.578800] do_syscall_64+0x37/0xb0
<4> [184.578803] entry_SYSCALL_64_after_hwframe+0x44/0xae
<4> [184.578805] RIP: 0033:0x7f6506736317
<4> [184.578807] Code: b3 66 90 48 8b 05 71 4b 2d 00 64 c7 00 26 00 00 00 48 c7
c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01
f0 ff ff 73 01 c3 48 8b 0d 41 4b 2d 00 f7 d8 64 89 01 48
<4> [184.578808] RSP: 002b:7fff44211a98 EFLAGS: 0246 ORIG_RAX:
0010
<4> [184.578810] RAX: ffda RBX: 0006 RCX:
7f6506736317
<4> [184.578811] RDX: 7fff44211b30 RSI: c06864b8 RDI:
0006
<4> [184.578812] RBP: 7fff44211b30 R08: 7fff44311170 R09:
<4> [184.578813] R10: 0008 R11: 0246 R12:
c06864b8
<4> [184.578813] R13: 0006 R14: R15:
<4> [184.578819]
<4> [184.578820] irq event stamp: 47931
<4> [184.578821] hardirqs last enabled at (47937): []
__up_console_sem+0x62/0x70
<4> [184.578824] hardirqs last disabled at (47942): []
__up_console_sem+0x47/0x70
<4> [184.578826] softirqs last enabled at (47340): []
__do_softirq+0x32d/0x493
<4> [184.578828] softirqs last disabled at (47335): []
irq_exit_rcu+0xa6/0xe0
<4> [184.578830] ---[ end trace f17ec219f892c7d4 ]---
Fixes: 0f341974cbc2 ("drm/i915: Add i915_vma_unbind_unlocked, and take obj lock
for i915_vma_unbind, v2.")
Signed-off-by: Maarten Lankhorst
Testcase: kms_addfb_basic
---
drivers/gpu/drm/i915/display/intel_dpt.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu/drm/i915/display/intel_dpt.c
index 63a83d5f85a1..c2f8f853db90 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -253,7 +253,11 @@ intel_dpt_create(struct intel_framebuffer *fb)
if (IS_ERR(dpt_obj))
return ERR_CAST(dpt_obj);
- ret = i915_gem_object_set_cache_level(dpt_obj, I915_CACHE_NONE);
+ ret = i915_gem_object_lock_interruptible(dpt_obj, NULL);
+ if (!ret) {
+ ret =
[Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
In terms of async flip optimization we don't to allocate
extra ddb space, so lets skip it.
v2: - Extracted min ddb async flip check to separate function
(Ville Syrjälä)
- Used this function to prevent false positive WARN
to be triggered(Ville Syrjälä)
v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
it more universal.
- Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
- Use rate = 0 instead of just setting extra = 0, thus
letting other planes to use extra ddb and avoiding WARN
(Ville Syrjälä)
v4: - Renamed needs_min_ddb as s/needs/use/ to match
the wm0 counterpart(Ville Syrjälä)
- Added plane->async_flip check to use_min_ddb(now
passing plane as a parameter to do that)(Ville Syrjälä)
- Account for use_min_ddb also when calculating total data rate
(Ville Syrjälä)
v5:
- Use for_each_intel_plane_on_crtc instead of for_each_intel_plane_id
to get plane->async_flip check and account for all planes(Ville Syrjälä)
- Fix line wrapping(Ville Syrjälä)
- Set plane data rate conditionally, avoiding on redundant assignment
(Ville Syrjälä)
- Removed redundant whitespace(Ville Syrjälä)
- Handle use_min_ddb case in skl_plane_relative_data_rate instead of
icl_get_total_relative_data_rate(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0bb4c941f950..bb147e5a77b6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4906,6 +4906,16 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc
*crtc, u8 active_pipes)
return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0;
}
+static bool use_min_ddb(const struct intel_crtc_state *crtc_state,
+ struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ return DISPLAY_VER(i915) >= 13 &&
+ crtc_state->uapi.async_flip &&
+ plane->async_flip;
+}
+
static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
struct intel_plane *plane)
{
@@ -4934,6 +4944,14 @@ skl_plane_relative_data_rate(const struct
intel_crtc_state *crtc_state,
if (plane->id == PLANE_CURSOR)
return 0;
+ /*
+* We calculate extra ddb based on ratio plane rate/total data rate
+* in case, in some cases we should not allocate extra ddb for the
plane,
+* so do not count its data rate, if this is the case.
+*/
+ if (use_min_ddb(crtc_state, plane))
+ return 0;
+
if (color_plane == 1 &&
!intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
return 0;
--
2.24.1.485.gad05a3d8e5
Re: [Intel-gfx] [PATCH 0/9] drm/i915/display: drm device based logging conversions
On Fri, 21 Jan 2022, Ville Syrjälä wrote: > On Fri, Jan 21, 2022 at 03:00:29PM +0200, Jani Nikula wrote: >> Purge some accumulated drm device based logging changes from my local >> branches. >> >> Jani Nikula (9): >> drm/i915/snps: convert to drm device based logging >> drm/i915/pps: convert to drm device based logging >> drm/i915/hotplug: convert to drm device based logging >> drm/i915/dp: convert to drm device based logging >> drm/i915/plane: convert to drm device based logging and WARN >> drm/i915/sprite: convert to drm device based logging >> drm/i915/lspcon: convert to drm device based logging >> drm/i915/cdclk: update intel_dump_cdclk_config() logging >> drm/i915/cdclk: convert to drm device based logging > > Eyeballed it quickly. Looks all right to me. > > Series is > Reviewed-by: Ville Syrjälä Thanks, pushed to drm-intel-next. BR, Jani. > >> >> .../gpu/drm/i915/display/intel_atomic_plane.c | 5 +- >> drivers/gpu/drm/i915/display/intel_cdclk.c| 23 +-- >> drivers/gpu/drm/i915/display/intel_cdclk.h| 3 +- >> drivers/gpu/drm/i915/display/intel_display.c | 2 +- >> .../drm/i915/display/intel_display_power.c| 2 +- >> drivers/gpu/drm/i915/display/intel_dp.c | 35 +++-- >> drivers/gpu/drm/i915/display/intel_hotplug.c | 14 +- >> drivers/gpu/drm/i915/display/intel_lspcon.c | 142 ++ >> drivers/gpu/drm/i915/display/intel_pps.c | 22 +-- >> drivers/gpu/drm/i915/display/intel_snps_phy.c | 29 ++-- >> drivers/gpu/drm/i915/display/intel_sprite.c | 24 +-- >> .../drm/i915/display/skl_universal_plane.c| 10 +- >> 12 files changed, 169 insertions(+), 142 deletions(-) >> >> -- >> 2.30.2 -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH 1/4] drm/i915: Add request cancel low level trace point
Add request cancel trace point guarded by
CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINT.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.h | 1 +
drivers/gpu/drm/i915/i915_trace.h | 10 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index d8c74bbf9aae2..3aed4d77f116c 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -124,6 +124,7 @@ intel_context_is_pinned(struct intel_context *ce)
static inline void intel_context_cancel_request(struct intel_context *ce,
struct i915_request *rq)
{
+ trace_i915_request_cancel(rq);
GEM_BUG_ON(!ce->ops->cancel_request);
return ce->ops->cancel_request(ce, rq);
}
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index 37b5c9e9d260e..d0a11a8bb0ca3 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -324,6 +324,11 @@ DEFINE_EVENT(i915_request, i915_request_add,
);
#if defined(CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS)
+DEFINE_EVENT(i915_request, i915_request_cancel,
+TP_PROTO(struct i915_request *rq),
+TP_ARGS(rq)
+);
+
DEFINE_EVENT(i915_request, i915_request_guc_submit,
TP_PROTO(struct i915_request *rq),
TP_ARGS(rq)
@@ -497,6 +502,11 @@ DEFINE_EVENT(intel_context, intel_context_do_unpin,
#else
#if !defined(TRACE_HEADER_MULTI_READ)
+static inline void
+trace_i915_request_cancel(struct i915_request *rq)
+{
+}
+
static inline void
trace_i915_request_guc_submit(struct i915_request *rq)
{
--
2.34.1
[Intel-gfx] [PATCH 2/4] drm/i915/guc: Cancel requests immediately
Change the preemption timeout to the smallest possible value (1 us) when
disabling scheduling to cancel a request and restore it after
cancellation. This not only cancels the request as fast as possible, it
fixes a bug where the preemption timeout is 0 which results in the
schedule disable hanging forever.
Reported-by: Jani Saarinen
Fixes: 62eaf0ae217d4 ("drm/i915/guc: Support request cancellation")
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/4960
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 5 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 46 +++
2 files changed, 31 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 30cd81ad8911a..730998823dbea 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -198,6 +198,11 @@ struct intel_context {
* each priority bucket
*/
u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
+ /**
+* @preemption_timeout: preemption timeout of the context, used
+* to restore this value after request cancellation
+*/
+ u32 preemption_timeout;
} guc_state;
struct {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 3918f1be114fa..966947c450253 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2147,7 +2147,8 @@ static inline u32 get_children_join_value(struct
intel_context *ce,
return __get_parent_scratch(ce)->join[child_index].semaphore;
}
-static void guc_context_policy_init(struct intel_engine_cs *engine,
+static void guc_context_policy_init(struct intel_context *ce,
+ struct intel_engine_cs *engine,
struct guc_lrc_desc *desc)
{
desc->policy_flags = 0;
@@ -2157,7 +2158,8 @@ static void guc_context_policy_init(struct
intel_engine_cs *engine,
/* NB: For both of these, zero means disabled. */
desc->execution_quantum = engine->props.timeslice_duration_ms * 1000;
- desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;
+ ce->guc_state.preemption_timeout = engine->props.preempt_timeout_ms *
1000;
+ desc->preemption_timeout = ce->guc_state.preemption_timeout;
}
static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
@@ -2193,7 +2195,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
desc->hw_context_desc = ce->lrc.lrca;
desc->priority = ce->guc_state.prio;
desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
- guc_context_policy_init(engine, desc);
+ guc_context_policy_init(ce, engine, desc);
/*
* If context is a parent, we need to register a process descriptor
@@ -2226,7 +2228,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
desc->hw_context_desc = child->lrc.lrca;
desc->priority = ce->guc_state.prio;
desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
- guc_context_policy_init(engine, desc);
+ guc_context_policy_init(child, engine, desc);
}
clear_children_join_go_memory(ce);
@@ -2409,6 +2411,19 @@ static u16 prep_context_pending_disable(struct
intel_context *ce)
return ce->guc_id.id;
}
+static void __guc_context_set_preemption_timeout(struct intel_guc *guc,
+u16 guc_id,
+u32 preemption_timeout)
+{
+ u32 action[] = {
+ INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT,
+ guc_id,
+ preemption_timeout
+ };
+
+ intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action), 0, true);
+}
+
static struct i915_sw_fence *guc_context_block(struct intel_context *ce)
{
struct intel_guc *guc = ce_to_guc(ce);
@@ -2442,8 +2457,10 @@ static struct i915_sw_fence *guc_context_block(struct
intel_context *ce)
spin_unlock_irqrestore(>guc_state.lock, flags);
- with_intel_runtime_pm(runtime_pm, wakeref)
+ with_intel_runtime_pm(runtime_pm, wakeref) {
+ __guc_context_set_preemption_timeout(guc, guc_id, 1);
__guc_context_sched_disable(guc, ce, guc_id);
+ }
return >guc_state.blocked;
}
@@ -2492,8 +2509,10 @@ static void guc_context_unblock(struct intel_context *ce)
spin_unlock_irqrestore(>guc_state.lock, flags);
- if (enable) {
- with_intel_runtime_pm(runtime_pm, wakeref)
+ with_intel_runtime_pm(runtime_pm, wakeref) {
+
[Intel-gfx] [PATCH 3/4] drm/i915/execlists: Fix execlists request cancellation corner case
More than 1 request can be submitted to a single ELSP at a time if
multiple requests are ready run to on the same context. When a request
is canceled it is marked bad, an idle pulse is triggered to the engine
(high priority kernel request), the execlists scheduler sees that
running request is bad and sets preemption timeout to minimum value (1
ms). This fails to work if multiple requests are combined on the ELSP as
only the most recent request is stored in the execlists schedule (the
request stored in the ELSP isn't marked bad, thus preemption timeout
isn't set to the minimum value). If the preempt timeout is configured to
zero, the engine is permanently hung. This is shown by an upcoming
selftest.
To work around this, mark the idle pulse with a flag to force a preempt
with the minimum value.
Fixes: 38b237eab2bc7 ("drm/i915: Individual request cancellation")
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 23 +++
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 1 +
.../drm/i915/gt/intel_execlists_submission.c | 18 ++-
drivers/gpu/drm/i915/i915_request.h | 6 +
4 files changed, 38 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index a3698f611f457..efd1c719b4072 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -243,7 +243,8 @@ void intel_engine_init_heartbeat(struct intel_engine_cs
*engine)
INIT_DELAYED_WORK(>heartbeat.work, heartbeat);
}
-static int __intel_engine_pulse(struct intel_engine_cs *engine)
+static int __intel_engine_pulse(struct intel_engine_cs *engine,
+ bool force_preempt)
{
struct i915_sched_attr attr = { .priority = I915_PRIORITY_BARRIER };
struct intel_context *ce = engine->kernel_context;
@@ -258,6 +259,8 @@ static int __intel_engine_pulse(struct intel_engine_cs
*engine)
return PTR_ERR(rq);
__set_bit(I915_FENCE_FLAG_SENTINEL, >fence.flags);
+ if (force_preempt)
+ __set_bit(I915_FENCE_FLAG_FORCE_PREEMPT, >fence.flags);
heartbeat_commit(rq, );
GEM_BUG_ON(rq->sched.attr.priority < I915_PRIORITY_BARRIER);
@@ -299,7 +302,7 @@ int intel_engine_set_heartbeat(struct intel_engine_cs
*engine,
/* recheck current execution */
if (intel_engine_has_preemption(engine)) {
- err = __intel_engine_pulse(engine);
+ err = __intel_engine_pulse(engine, false);
if (err)
set_heartbeat(engine, saved);
}
@@ -312,7 +315,8 @@ int intel_engine_set_heartbeat(struct intel_engine_cs
*engine,
return err;
}
-int intel_engine_pulse(struct intel_engine_cs *engine)
+static int _intel_engine_pulse(struct intel_engine_cs *engine,
+ bool force_preempt)
{
struct intel_context *ce = engine->kernel_context;
int err;
@@ -325,7 +329,7 @@ int intel_engine_pulse(struct intel_engine_cs *engine)
err = -EINTR;
if (!mutex_lock_interruptible(>timeline->mutex)) {
- err = __intel_engine_pulse(engine);
+ err = __intel_engine_pulse(engine, force_preempt);
mutex_unlock(>timeline->mutex);
}
@@ -334,6 +338,17 @@ int intel_engine_pulse(struct intel_engine_cs *engine)
return err;
}
+int intel_engine_pulse(struct intel_engine_cs *engine)
+{
+ return _intel_engine_pulse(engine, false);
+}
+
+
+int intel_engine_pulse_force_preempt(struct intel_engine_cs *engine)
+{
+ return _intel_engine_pulse(engine, true);
+}
+
int intel_engine_flush_barriers(struct intel_engine_cs *engine)
{
struct i915_sched_attr attr = { .priority = I915_PRIORITY_MIN };
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
index 5da6d809a87a2..d9c8386754cb3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
@@ -21,6 +21,7 @@ void intel_gt_park_heartbeats(struct intel_gt *gt);
void intel_gt_unpark_heartbeats(struct intel_gt *gt);
int intel_engine_pulse(struct intel_engine_cs *engine);
+int intel_engine_pulse_force_preempt(struct intel_engine_cs *engine);
int intel_engine_flush_barriers(struct intel_engine_cs *engine);
#endif /* INTEL_ENGINE_HEARTBEAT_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 960a9aaf4f3a3..f0c2024058731 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1222,26 +1222,29 @@ static void record_preemption(struct
intel_engine_execlists *execlists)
}
static unsigned long
[Intel-gfx] [PATCH 0/4] Fix up request cancel
Fix request cancellation + add request cancel low level trace point. v2: - Update cancel reset selftest preemption timeout value to zero - Fix bug in execlists cancel code Signed-off-by: Matthew Brost Matthew Brost (4): drm/i915: Add request cancel low level trace point drm/i915/guc: Cancel requests immediately drm/i915/execlists: Fix execlists request cancellation corner case drm/i915/selftests: Set preemption timeout to zero in cancel reset test drivers/gpu/drm/i915/gt/intel_context.h | 1 + drivers/gpu/drm/i915/gt/intel_context_types.h | 5 ++ .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 23 -- .../gpu/drm/i915/gt/intel_engine_heartbeat.h | 1 + .../drm/i915/gt/intel_execlists_submission.c | 18 +--- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 46 +++ drivers/gpu/drm/i915/i915_request.h | 6 +++ drivers/gpu/drm/i915/i915_trace.h | 10 drivers/gpu/drm/i915/selftests/i915_request.c | 7 +-- 9 files changed, 84 insertions(+), 33 deletions(-) -- 2.34.1
[Intel-gfx] [PATCH 4/4] drm/i915/selftests: Set preemption timeout to zero in cancel reset test
Set the preemption timeout to zero to prove that request cancellation with preemption disabled works. Also this seals a race between a possible preemption and request cancellation. Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/selftests/i915_request.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 2a99dd7c2fe8a..e522e24129f9b 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -790,8 +790,9 @@ static int __cancel_completed(struct intel_engine_cs *engine) * wait for spinner to start, create a NOP request and submit it, cancel the * spinner, wait for spinner to complete and verify it failed with an error, * finally wait for NOP request to complete verify it succeeded without an - * error. Preemption timeout also reduced / restored so test runs in a timely - * maner. + * error. Preemption timeout also set to zero to ensure cancellation works with + * preemption disabled and to ensure the NOP request doesn't trigger a + * preemption on the spinner sealing a race between a preemption and the cancel. */ static int __cancel_reset(struct drm_i915_private *i915, struct intel_engine_cs *engine) @@ -807,7 +808,7 @@ static int __cancel_reset(struct drm_i915_private *i915, return 0; preempt_timeout_ms = engine->props.preempt_timeout_ms; - engine->props.preempt_timeout_ms = 100; + engine->props.preempt_timeout_ms = 0; if (igt_spinner_init(, engine->gt)) goto out_restore; -- 2.34.1
Re: [Intel-gfx] [PATCH 11/11] drm/vmwgfx: remove vmw_wait_dma_fence
On Mon, 2022-01-24 at 14:03 +0100, Christian König wrote: > Decomposing fence containers don't seem to make any sense here. > > So just remove the function entirely and call dma_fence_wait() > directly. > > Signed-off-by: Christian König > Cc: VMware Graphics > Cc: Zack Rusin Looks good. That's a great cleanup. Reviewed-by: Zack Rusin
Re: [Intel-gfx] [PATCH] drm/i915: Lock dpt_obj around set_cache_level.
On 1/24/22 14:02, Maarten Lankhorst wrote:
set_cache_level may unbind the object, which will result in the below
lockdep splat:
<6> [184.578145] [IGT] kms_addfb_basic: starting subtest
addfb25-framebuffer-vs-set-tiling
<4> [184.578220] [ cut here ]
<4> [184.578221] WARN_ON(debug_locks &&
!(lock_is_held(&(&((obj)->base.resv)->lock.base)->dep_map) != 0))
<4> [184.578237] WARNING: CPU: 6 PID: 5544 at
drivers/gpu/drm/i915/i915_gem.c:123 i915_gem_object_unbind+0x4a9/0x510 [i915]
<4> [184.578323] Modules linked in: vgem drm_shmem_helper snd_hda_codec_hdmi
i915 mei_hdcp x86_pkg_temp_thermal snd_hda_intel coretemp crct10dif_pclmul
snd_intel_dspcfg crc32_pclmul ttm snd_hda_codec ghash_clmulni_intel snd_hwdep
drm_kms_helper snd_hda_core e1000e mei_me syscopyarea ptp snd_pcm sysfillrect mei
pps_core sysimgblt fb_sys_fops prime_numbers intel_lpss_pci smsc75xx usbnet mii
<4> [184.578349] CPU: 6 PID: 5544 Comm: kms_addfb_basic Not tainted
5.16.0-CI-Patchwork_22006+ #1
<4> [184.578351] Hardware name: Intel Corporation Alder Lake Client
Platform/AlderLake-P DDR4 RVP, BIOS ADLPFWI1.R00.2422.A00.2110131104 10/13/2021
<4> [184.578352] RIP: 0010:i915_gem_object_unbind+0x4a9/0x510 [i915]
<4> [184.578424] Code: 00 be ff ff ff ff 48 8d 78 68 e8 a2 6e 2b e1 85 c0 0f 85 b1 fb
ff ff 48 c7 c6 48 37 9e a0 48 c7 c7 d9 fc a1 a0 e8 a3 54 26 e1 <0f> 0b e9 97 fb ff ff
31 ed 48 8b 5c 24 58 65 48 33 1c 25 28 00 00
<4> [184.578426] RSP: 0018:c900013b3b68 EFLAGS: 00010286
<4> [184.578428] RAX: RBX: c900013b3bb0 RCX:
0001
<4> [184.578429] RDX: 8001 RSI: 8230b42d RDI:
<4> [184.578430] RBP: 888120e1 R08: R09:
c0007fff
<4> [184.578431] R10: 0001 R11: c900013b3980 R12:
8881176ea740
<4> [184.578432] R13: 888120e1 R14: R15:
0001
<4> [184.578433] FS: 7f65074f5e40() GS:8f30()
knlGS:
<4> [184.578435] CS: 0010 DS: ES: CR0: 80050033
<4> [184.578436] CR2: 7fff4420ede8 CR3: 00010c2f2005 CR4:
00770ee0
<4> [184.578437] PKRU: 5554
<4> [184.578438] Call Trace:
<4> [184.578439]
<4> [184.578440] ? dma_resv_iter_first_unlocked+0x78/0xf0
<4> [184.578447] intel_dpt_create+0x88/0x220 [i915]
<4> [184.578530] intel_framebuffer_init+0x5b8/0x620 [i915]
<4> [184.578612] intel_framebuffer_create+0x3d/0x60 [i915]
<4> [184.578691] intel_user_framebuffer_create+0x18f/0x2c0 [i915]
<4> [184.578775] drm_internal_framebuffer_create+0x36d/0x4c0
<4> [184.578779] drm_mode_addfb2+0x2f/0xd0
<4> [184.578781] ? drm_mode_addfb_ioctl+0x10/0x10
<4> [184.578784] drm_ioctl_kernel+0xac/0x140
<4> [184.578787] drm_ioctl+0x201/0x3d0
<4> [184.578789] ? drm_mode_addfb_ioctl+0x10/0x10
<4> [184.578796] __x64_sys_ioctl+0x6a/0xa0
<4> [184.578800] do_syscall_64+0x37/0xb0
<4> [184.578803] entry_SYSCALL_64_after_hwframe+0x44/0xae
<4> [184.578805] RIP: 0033:0x7f6506736317
<4> [184.578807] Code: b3 66 90 48 8b 05 71 4b 2d 00 64 c7 00 26 00 00 00 48 c7 c0 ff
ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73
01 c3 48 8b 0d 41 4b 2d 00 f7 d8 64 89 01 48
<4> [184.578808] RSP: 002b:7fff44211a98 EFLAGS: 0246 ORIG_RAX:
0010
<4> [184.578810] RAX: ffda RBX: 0006 RCX:
7f6506736317
<4> [184.578811] RDX: 7fff44211b30 RSI: c06864b8 RDI:
0006
<4> [184.578812] RBP: 7fff44211b30 R08: 7fff44311170 R09:
<4> [184.578813] R10: 0008 R11: 0246 R12:
c06864b8
<4> [184.578813] R13: 0006 R14: R15:
<4> [184.578819]
<4> [184.578820] irq event stamp: 47931
<4> [184.578821] hardirqs last enabled at (47937): []
__up_console_sem+0x62/0x70
<4> [184.578824] hardirqs last disabled at (47942): []
__up_console_sem+0x47/0x70
<4> [184.578826] softirqs last enabled at (47340): []
__do_softirq+0x32d/0x493
<4> [184.578828] softirqs last disabled at (47335): []
irq_exit_rcu+0xa6/0xe0
<4> [184.578830] ---[ end trace f17ec219f892c7d4 ]---
Fixes: 0f341974cbc2 ("drm/i915: Add i915_vma_unbind_unlocked, and take obj lock for
i915_vma_unbind, v2.")
Signed-off-by: Maarten Lankhorst
Testcase: kms_addfb_basic
---
drivers/gpu/drm/i915/display/intel_dpt.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
LGTM. Reviewed-by: Thomas Hellström
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu/drm/i915/display/intel_dpt.c
index 63a83d5f85a1..c2f8f853db90 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -253,7 +253,11 @@ intel_dpt_create(struct intel_framebuffer *fb)
if (IS_ERR(dpt_obj))
return ERR_CAST(dpt_obj);
- ret = i915_gem_object_set_cache_level(dpt_obj, I915_CACHE_NONE);
+ ret =
Re: [Intel-gfx] [RFC PATCH 3/5] drm/i915/flat-CCS: move GET_CCS_SIZE macro into driver-wide header
On Fri, 21 Jan 2022, Adrian Larumbe wrote:
> It has to be used by other files other than low-level migration code.
Maybe, but i915_drv.h is not the dumping ground for this
stuff. Especially you shouldn't add anything in i915_drv.h that requires
you to pull in other headers. The goal is to go in the completely
opposite direction.
BR,
Jani.
>
> Signed-off-by: Adrian Larumbe
> ---
> drivers/gpu/drm/i915/gt/intel_migrate.c | 1 -
> drivers/gpu/drm/i915/i915_drv.h | 5 +
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
> b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index a210c911905e..716f2f51c7f9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -16,7 +16,6 @@ struct insert_pte_data {
> };
>
> #define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
> -#define GET_CCS_SIZE(i915, size) (HAS_FLAT_CCS(i915) ? (size) >> 8 : 0)
>
> static bool engine_supports_migration(struct intel_engine_cs *engine)
> {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5623892ceab9..6b890a6674e4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -105,6 +105,7 @@
> #include "i915_request.h"
> #include "i915_scheduler.h"
> #include "gt/intel_timeline.h"
> +#include "gt/intel_gpu_commands.h"
> #include "i915_vma.h"
>
>
> @@ -1526,6 +1527,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs)
>
> +#define GET_CCS_SIZE(i915, size) (HAS_FLAT_CCS(i915) ? \
> + DIV_ROUND_UP(size, NUM_CCS_BYTES_PER_BLOCK) \
> + 0)
> +
> #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
>
> #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [RFC PATCH 4/5] drm/i915/flat-CCS: handle CCS block blit for bo migrations
On Fri, 21 Jan 2022, Adrian Larumbe wrote:
> Because the smem-evicted bo that holds the CCS block has to be blitted
> separately from the original compressed bo, two sets of PTEs have to
> be emitted for every bo copy.
>
> This commit is partially based off another commit from Ramalingam C
> , currently under discussion.
>
> Signed-off-by: Adrian Larumbe
> ---
> drivers/gpu/drm/i915/gt/intel_migrate.c| 288 +++--
> drivers/gpu/drm/i915/gt/intel_migrate.h| 2 +
> drivers/gpu/drm/i915/gt/selftest_migrate.c | 3 +-
> 3 files changed, 207 insertions(+), 86 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
> b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 716f2f51c7f9..da0fcc42c43c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -447,14 +447,183 @@ static bool wa_1209644611_applies(int ver, u32 size)
> return height % 4 == 3 && height <= 8;
> }
>
> +static inline u32 *i915_flush_dw(u32 *cmd, u64 dst, u32 flags)
As a general rule, please don't use the inline keyword in .c files, just
let the compiler decide. It's a premature optimization. And you won't
get warnings if it's unused.
BR,
Jani.
> +{
> + /* Mask the 3 LSB to use the PPGTT address space */
> + *cmd++ = MI_FLUSH_DW | flags;
> + *cmd++ = lower_32_bits(dst);
> + *cmd++ = upper_32_bits(dst);
> +
> + return cmd;
> +}
> +
> +static u32 calc_ctrl_surf_instr_size(struct drm_i915_private *i915, int
> +size)
> +{
> + u32 num_cmds, num_blks, total_size;
> +
> + if (!GET_CCS_SIZE(i915, size))
> + return 0;
> +
> + /*
> + * XY_CTRL_SURF_COPY_BLT transfers CCS in 256 byte
> + * blocks. one XY_CTRL_SURF_COPY_BLT command can
> + * trnasfer upto 1024 blocks.
> + */
> + num_blks = (GET_CCS_SIZE(i915, size) +
> +(NUM_CCS_BYTES_PER_BLOCK - 1)) >> 8;
> + num_cmds = (num_blks + (NUM_CCS_BLKS_PER_XFER - 1)) >> 10;
> + total_size = (XY_CTRL_SURF_INSTR_SIZE) * num_cmds;
> +
> + /*
> + * We need to add a flush before and after
> + * XY_CTRL_SURF_COPY_BLT
> + */
> + total_size += 2 * MI_FLUSH_DW_SIZE;
> + return total_size;
> +}
> +
> +static u32 *_i915_ctrl_surf_copy_blt(u32 *cmd, u64 src_addr, u64 dst_addr,
> + u8 src_mem_access, u8 dst_mem_access,
> + int src_mocs, int dst_mocs,
> + u16 num_ccs_blocks)
> +{
> + int i = num_ccs_blocks;
> +
> + /*
> + * The XY_CTRL_SURF_COPY_BLT instruction is used to copy the CCS
> + * data in and out of the CCS region.
> + *
> + * We can copy at most 1024 blocks of 256 bytes using one
> + * XY_CTRL_SURF_COPY_BLT instruction.
> + *
> + * In case we need to copy more than 1024 blocks, we need to add
> + * another instruction to the same batch buffer.
> + *
> + * 1024 blocks of 256 bytes of CCS represent a total 256KB of CCS.
> + *
> + * 256 KB of CCS represents 256 * 256 KB = 64 MB of LMEM.
> + */
> + do {
> + /*
> + * We use logical AND with 1023 since the size field
> + * takes values which is in the range of 0 - 1023
> + */
> + *cmd++ = ((XY_CTRL_SURF_COPY_BLT) |
> + (src_mem_access << SRC_ACCESS_TYPE_SHIFT) |
> + (dst_mem_access << DST_ACCESS_TYPE_SHIFT) |
> + (((i - 1) & 1023) << CCS_SIZE_SHIFT));
> + *cmd++ = lower_32_bits(src_addr);
> + *cmd++ = ((upper_32_bits(src_addr) & 0x) |
> + (src_mocs << XY_CTRL_SURF_MOCS_SHIFT));
> + *cmd++ = lower_32_bits(dst_addr);
> + *cmd++ = ((upper_32_bits(dst_addr) & 0x) |
> + (dst_mocs << XY_CTRL_SURF_MOCS_SHIFT));
> + src_addr += SZ_64M;
> + dst_addr += SZ_64M;
> + i -= NUM_CCS_BLKS_PER_XFER;
> + } while (i > 0);
> +
> + return cmd;
> +}
> +
> +
> +static int emit_ccs(struct i915_request *rq,
> + struct sgt_dma *it_lmem,
> + enum i915_cache_level lmem_cache_level,
> + struct sgt_dma *it_css,
> + enum i915_cache_level css_cache_level,
> + bool lmem2smem,
> + int size)
> +{
> + struct drm_i915_private *i915 = rq->engine->i915;
> + u32 num_ccs_blks = (GET_CCS_SIZE(i915, size) +
> + NUM_CCS_BYTES_PER_BLOCK - 1) >> 8;
> + struct sgt_dma *it_src, *it_dst;
> + enum i915_cache_level src_cache_level;
> + enum i915_cache_level dst_cache_level;
> + u8 src_access, dst_access;
> + u32 src_offset, dst_offset;
> + u32 ccs_ring_size;
> + int err, len;
> + u32 *cs;
> +
> + ccs_ring_size = calc_ctrl_surf_instr_size(i915, size);
> +
> + err = emit_no_arbitration(rq);
Re: [Intel-gfx] [PATCH V2 3/7] drm/gma: Remove calls to kmap()
On Sun, Jan 23, 2022 at 05:54:05PM -0800, ira.we...@intel.com wrote:
> From: Ira Weiny
>
> kmap() is being deprecated and these instances are easy to convert to
> kmap_local_page().
>
> Furthermore, in gma_crtc_cursor_set() use the memcpy_from_page() helper
> instead of an open coded use of kmap_local_page().
>
> Signed-off-by: Ira Weiny
Applied to drm-misc-next, the others should all have full time maintainers
to make sure the patches land. Pls holler if not.
Thanks, Daniel
> ---
> drivers/gpu/drm/gma500/gma_display.c | 6 ++
> drivers/gpu/drm/gma500/mmu.c | 8
> 2 files changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/gma500/gma_display.c
> b/drivers/gpu/drm/gma500/gma_display.c
> index 99da3118131a..60ba7de59139 100644
> --- a/drivers/gpu/drm/gma500/gma_display.c
> +++ b/drivers/gpu/drm/gma500/gma_display.c
> @@ -335,7 +335,7 @@ int gma_crtc_cursor_set(struct drm_crtc *crtc,
> struct psb_gem_object *pobj;
> struct psb_gem_object *cursor_pobj = gma_crtc->cursor_pobj;
> struct drm_gem_object *obj;
> - void *tmp_dst, *tmp_src;
> + void *tmp_dst;
> int ret = 0, i, cursor_pages;
>
> /* If we didn't get a handle then turn the cursor off */
> @@ -400,9 +400,7 @@ int gma_crtc_cursor_set(struct drm_crtc *crtc,
> /* Copy the cursor to cursor mem */
> tmp_dst = dev_priv->vram_addr + cursor_pobj->offset;
> for (i = 0; i < cursor_pages; i++) {
> - tmp_src = kmap(pobj->pages[i]);
> - memcpy(tmp_dst, tmp_src, PAGE_SIZE);
> - kunmap(pobj->pages[i]);
> + memcpy_from_page(tmp_dst, pobj->pages[i], 0, PAGE_SIZE);
> tmp_dst += PAGE_SIZE;
> }
>
> diff --git a/drivers/gpu/drm/gma500/mmu.c b/drivers/gpu/drm/gma500/mmu.c
> index fe9ace2a7967..a70b01ccdf70 100644
> --- a/drivers/gpu/drm/gma500/mmu.c
> +++ b/drivers/gpu/drm/gma500/mmu.c
> @@ -184,17 +184,17 @@ struct psb_mmu_pd *psb_mmu_alloc_pd(struct
> psb_mmu_driver *driver,
> pd->invalid_pte = 0;
> }
>
> - v = kmap(pd->dummy_pt);
> + v = kmap_local_page(pd->dummy_pt);
> for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
> v[i] = pd->invalid_pte;
>
> - kunmap(pd->dummy_pt);
> + kunmap_local(v);
>
> - v = kmap(pd->p);
> + v = kmap_local_page(pd->p);
> for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
> v[i] = pd->invalid_pde;
>
> - kunmap(pd->p);
> + kunmap_local(v);
>
> clear_page(kmap(pd->dummy_page));
> kunmap(pd->dummy_page);
> --
> 2.31.1
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
Re: [Intel-gfx] [PATCH 06/11] dma-buf: warn about containers in dma_resv object
Am 24.01.22 um 17:36 schrieb Thomas Hellström (Intel): On 1/24/22 14:03, Christian König wrote: Drivers should not add containers as shared fences to the dma_resv object, instead each fence should be added individually. Signed-off-by: Christian König Reviewed-by: Daniel Vetter Reviewed-by: Thomas Hellström Is there any indication that this triggers on existing drivers? There used to be a case in amdgpu which triggered this, but at least I'm not aware of any in the current code. Christian. Thomas
Re: [Intel-gfx] [PATCH 01/11] drm/radeon: use ttm_resource_manager_debug
Am 24.01.22 um 17:33 schrieb Thomas Hellström: On Mon, 2022-01-24 at 14:03 +0100, Christian König wrote: Instead of calling the debug operation directly. Signed-off-by: Christian König Reviewed-by: Huang Rui The first two patches seem unrelated to the series. No idea what happened here, those two are already upstream. I probably just forgot to pull drm-misc-next changes from a different system. Also is there a chance of a series cover-letter? Going to add one the next time, but I though it would be pretty clear what this is now about. Thanks, Christian. Thanks, Thomas --- drivers/gpu/drm/radeon/radeon_ttm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 11b21d605584..0d1283cdc8fb 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -802,7 +802,7 @@ static int radeon_mm_vram_dump_table_show(struct seq_file *m, void *unused) TTM_PL_VRAM); struct drm_printer p = drm_seq_file_printer(m); - man->func->debug(man, ); + ttm_resource_manager_debug(man, ); return 0; } @@ -820,7 +820,7 @@ static int radeon_mm_gtt_dump_table_show(struct seq_file *m, void *unused) TTM_PL_TT); struct drm_printer p = drm_seq_file_printer(m); - man->func->debug(man, ); + ttm_resource_manager_debug(man, ); return 0; }
Re: [Intel-gfx] [PATCH 01/11] drm/radeon: use ttm_resource_manager_debug
On Mon, 2022-01-24 at 14:03 +0100, Christian König wrote: > Instead of calling the debug operation directly. > > Signed-off-by: Christian König > Reviewed-by: Huang Rui The first two patches seem unrelated to the series. Also is there a chance of a series cover-letter? Thanks, Thomas > --- > drivers/gpu/drm/radeon/radeon_ttm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c > b/drivers/gpu/drm/radeon/radeon_ttm.c > index 11b21d605584..0d1283cdc8fb 100644 > --- a/drivers/gpu/drm/radeon/radeon_ttm.c > +++ b/drivers/gpu/drm/radeon/radeon_ttm.c > @@ -802,7 +802,7 @@ static int radeon_mm_vram_dump_table_show(struct > seq_file *m, void *unused) > > TTM_PL_VRAM); > struct drm_printer p = drm_seq_file_printer(m); > > - man->func->debug(man, ); > + ttm_resource_manager_debug(man, ); > return 0; > } > > @@ -820,7 +820,7 @@ static int radeon_mm_gtt_dump_table_show(struct > seq_file *m, void *unused) > > TTM_PL_TT); > struct drm_printer p = drm_seq_file_printer(m); > > - man->func->debug(man, ); > + ttm_resource_manager_debug(man, ); > return 0; > } >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/overlay: Prevent divide by zero bugs in scaling
== Series Details == Series: drm/i915/overlay: Prevent divide by zero bugs in scaling URL : https://patchwork.freedesktop.org/series/99242/ State : success == Summary == CI Bug Log - changes from CI_DRM_11128 -> Patchwork_22079 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/index.html Participating hosts (47 -> 37) -- Missing(10): bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_22079 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: [PASS][2] -> [FAIL][3] ([i915#4547]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html * igt@i915_selftest@live@execlists: - fi-bsw-kefka: [PASS][4] -> [INCOMPLETE][5] ([i915#2940]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b: - fi-cfl-8109u: [PASS][6] -> [DMESG-WARN][7] ([i915#295]) +11 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html * igt@runner@aborted: - fi-bsw-kefka: NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/fi-bsw-kefka/igt@run...@aborted.html Possible fixes * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:[INCOMPLETE][9] ([i915#4785]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][11] ([i915#4269]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html Warnings * igt@runner@aborted: - fi-skl-6600u: [FAIL][13] ([i915#1436] / [i915#4312]) -> [FAIL][14] ([i915#4312]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/fi-skl-6600u/igt@run...@aborted.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/fi-skl-6600u/igt@run...@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547 [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785 Build changes - * Linux: CI_DRM_11128 -> Patchwork_22079 CI-20190529: 20190529 CI_DRM_11128: 49bb8f6f465751bc71103784fe7603409fee @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6330: f73008bac9a8db0779264b170f630483e9165764 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_22079: f8e4ab5e3cd4369d9b7cd1c36d192d4feda748cd @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f8e4ab5e3cd4 drm/i915/overlay: Prevent divide by zero bugs in scaling == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/index.html
Re: [Intel-gfx] [RFC PATCH 5/5] drm/i915/flat-CCS: handle creation and destruction of flat CCS bo's
On Mon, 2022-01-24 at 17:24 +0100, Thomas Hellström wrote: > Hi, Adrian > > On 1/21/22 23:22, Adrian Larumbe wrote: > > When a flat-CCS lmem-bound BO is evicted onto smem for the first > > time, a > > separate swap gem object is created to hold the contents of the CCS > > block. > > It is assumed that, for a flat-CCS bo to be migrated back onto > > lmem, it > > should've begun its life in lmem. > > > > It also handles destruction of the swap bo when the original TTM > > object > > reaches the end of its life. > > > > Signed-off-by: Adrian Larumbe > > > While allocating a separate object for the CCS data is certainly > possible, it poses some additional difficulties that have not been > addressed here. > > The CCS object needs to share the dma_resv of the original object. > That > is because the CCS object needs to be locked and validated when we > process it, and we > can only trylock within the ttm move callback which might therefore > fail > and isn't sufficient on swapin. We'd need to create some > i915_gem_object_create_region_locked() that wraps > ttm_bo_init_reserved(). Actually that would be a function to create with a reservation object shared from another object. /Thomas
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
On Mon, Jan 24, 2022 at 03:52:34PM +0200, Stanislav Lisovskiy wrote:
> In terms of async flip optimization we don't to allocate
> extra ddb space, so lets skip it.
>
> v2: - Extracted min ddb async flip check to separate function
> (Ville Syrjälä)
> - Used this function to prevent false positive WARN
> to be triggered(Ville Syrjälä)
>
> v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
> it more universal.
> - Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
> - Use rate = 0 instead of just setting extra = 0, thus
> letting other planes to use extra ddb and avoiding WARN
> (Ville Syrjälä)
>
> v4: - Renamed needs_min_ddb as s/needs/use/ to match
> the wm0 counterpart(Ville Syrjälä)
> - Added plane->async_flip check to use_min_ddb(now
> passing plane as a parameter to do that)(Ville Syrjälä)
> - Account for use_min_ddb also when calculating total data rate
> (Ville Syrjälä)
>
> v5:
> - Use for_each_intel_plane_on_crtc instead of for_each_intel_plane_id
> to get plane->async_flip check and account for all planes(Ville Syrjälä)
> - Fix line wrapping(Ville Syrjälä)
> - Set plane data rate conditionally, avoiding on redundant assignment
> (Ville Syrjälä)
> - Removed redundant whitespace(Ville Syrjälä)
> - Handle use_min_ddb case in skl_plane_relative_data_rate instead of
> icl_get_total_relative_data_rate(Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/intel_pm.c | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0bb4c941f950..bb147e5a77b6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4906,6 +4906,16 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc
> *crtc, u8 active_pipes)
> return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0;
> }
>
> +static bool use_min_ddb(const struct intel_crtc_state *crtc_state,
> + struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +
> + return DISPLAY_VER(i915) >= 13 &&
> +crtc_state->uapi.async_flip &&
> +plane->async_flip;
> +}
> +
> static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
>struct intel_plane *plane)
> {
> @@ -4934,6 +4944,14 @@ skl_plane_relative_data_rate(const struct
> intel_crtc_state *crtc_state,
> if (plane->id == PLANE_CURSOR)
> return 0;
>
> + /*
> + * We calculate extra ddb based on ratio plane rate/total data rate
> + * in case, in some cases we should not allocate extra ddb for the
> plane,
> + * so do not count its data rate, if this is the case.
> + */
> + if (use_min_ddb(crtc_state, plane))
> + return 0;
> +
> if (color_plane == 1 &&
> !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
> return 0;
Yeah this looks nice and simple. Only minor nit is that I'd probably
have put it after this ccs vs. planar related thing which is a more
static decision than the async flip optimization.
Reviewed-by: Ville Syrjälä
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH 2/7] drm/i915/guc: Add XE_LP registers for GuC error state capture.
Internal feedback is to exactly match the register dumps
output as it did in execlist, however it seems that the
register dump function in execlist targetting the GT subsystem
also includes non-GT registers like display-related ones that
GuC doesn't manage. So for that, I will have to break up
the execlist function into global-non-gt vs global-gt and then
call the former for both GuC and non-GuC cases (skipping latter
when GuC is doing the dump).
...alan
On Tue, 2022-01-18 at 02:03 -0800, Alan Previn wrote:
> Add device specific tables and register lists to cover different engines
> class types for GuC error state capture for XE_LP products.
>
> Also, add runtime allocation and freeing of extended register lists
> for registers that need steering identifiers that depend on
> the detected HW config.
>
> Signed-off-by: Alan Previn
> ---
> drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 2 +
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 208 +++---
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 4 +-
> 3 files changed, 186 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> index 20c537274e60..6adfb5c07bcf 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> @@ -19,20 +19,84 @@
> * NOTE: For engine-registers, GuC only needs the register offsets
> * from the engine-mmio-base
> */
> +#define COMMON_GEN12BASE_GLOBAL() \
> + {GEN12_FAULT_TLB_DATA0,0, 0, "GEN12_FAULT_TLB_DATA0"}, \
> + {GEN12_FAULT_TLB_DATA1,0, 0, "GEN12_FAULT_TLB_DATA1"}, \
> + {FORCEWAKE_MT, 0, 0, "FORCEWAKE_MT"}, \
> + {DERRMR, 0, 0, "DERRMR"}, \
> + {GEN12_AUX_ERR_DBG,0, 0, "GEN12_AUX_ERR_DBG"}, \
> + {GEN12_GAM_DONE, 0, 0, "GEN12_GAM_DONE"}, \
> + {GEN11_GUC_SG_INTR_ENABLE, 0, 0, "GEN11_GUC_SG_INTR_ENABLE"}, \
> + {GEN11_CRYPTO_RSVD_INTR_ENABLE, 0, 0, "GEN11_CRYPTO_RSVD_INTR_ENABLE"},
> \
> + {GEN11_GUNIT_CSME_INTR_ENABLE, 0, 0, "GEN11_GUNIT_CSME_INTR_ENABLE"}, \
> + {GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0, 0,
> "GEN11_GPM_WGBOXPERF_INTR_ENABLE"}, \
> + {GEN8_DE_MISC_IER, 0, 0, "GEN8_DE_MISC_IER"}, \
> + {GEN12_RING_FAULT_REG, 0, 0, "GEN12_RING_FAULT_REG"}
> +
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Lock dpt_obj around set_cache_level.
== Series Details == Series: drm/i915: Lock dpt_obj around set_cache_level. URL : https://patchwork.freedesktop.org/series/99245/ State : warning == Summary == $ dim checkpatch origin/drm-tip f8d0f6b03553 drm/i915: Lock dpt_obj around set_cache_level. -:8: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #8: <6> [184.578145] [IGT] kms_addfb_basic: starting subtest addfb25-framebuffer-vs-set-tiling total: 0 errors, 1 warnings, 0 checks, 12 lines checked
Re: [Intel-gfx] [PATCH 04/11] dma-buf: warn about dma_fence_array container rules v2
On Mon, 2022-01-24 at 14:03 +0100, Christian König wrote: > It's not allowed to nest another dma_fence container into a > dma_fence_array > or otherwise we can run into recursion. > > Warn about that when we create a dma_fence_array. > > v2: fix comment style and typo in the warning pointed out by Thomas > > Signed-off-by: Christian König > Reviewed-by: Daniel Vetter Reviewed-by: Thomas Hellström > --- > drivers/dma-buf/dma-fence-array.c | 14 ++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/dma-buf/dma-fence-array.c b/drivers/dma-buf/dma- > fence-array.c > index 3e07f961e2f3..cb1bacb5a42b 100644 > --- a/drivers/dma-buf/dma-fence-array.c > +++ b/drivers/dma-buf/dma-fence-array.c > @@ -176,6 +176,20 @@ struct dma_fence_array > *dma_fence_array_create(int num_fences, > > array->base.error = PENDING_ERROR; > > + /* > + * dma_fence_array objects should never contain any other > fence > + * containers or otherwise we run into recursion and > potential kernel > + * stack overflow on operations on the dma_fence_array. > + * > + * The correct way of handling this is to flatten out the > array by the > + * caller instead. > + * > + * Enforce this here by checking that we don't create a > dma_fence_array > + * with any container inside. > + */ > + while (num_fences--) > + WARN_ON(dma_fence_is_container(fences[num_fences])); > + > return array; > } > EXPORT_SYMBOL(dma_fence_array_create);
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: fix header file inclusion for might_alloc() (rev4)
== Series Details == Series: drm/i915: fix header file inclusion for might_alloc() (rev4) URL : https://patchwork.freedesktop.org/series/99215/ State : failure == Summary == Applying: drm/i915: fix header file inclusion for might_alloc() Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_vma_resource.c Falling back to patching base and 3-way merge... No changes -- Patch already applied.
[Intel-gfx] [PATCH 1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate
From: Ville Syrjälä
Use DISPLAY_VER rather than GRAPHICS_VER to determine
availability of display hardware features.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 44c1f98144b4..e2b8409f9174 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1463,8 +1463,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
-#define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
-#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \
+#define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
+#define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
IS_GEMINILAKE(dev_priv) || \
IS_KABYLAKE(dev_priv))
@@ -1476,9 +1476,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define SUPPORTS_TV(dev_priv)
(INTEL_INFO(dev_priv)->display.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv)
(INTEL_INFO(dev_priv)->display.has_hotplug)
-#define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2)
+#define HAS_FW_BLC(dev_priv) (DISPLAY_VER(dev_priv) > 2)
#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.fbc_mask != 0)
-#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv)
>= 7)
+#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv)
>= 7)
#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
@@ -1491,7 +1491,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
#define HAS_PSR_HW_TRACKING(dev_priv) \
(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
-#define HAS_PSR2_SEL_FETCH(dev_priv)(GRAPHICS_VER(dev_priv) >= 12)
+#define HAS_PSR2_SEL_FETCH(dev_priv)(DISPLAY_VER(dev_priv) >= 12)
#define HAS_TRANSCODER(dev_priv, trans)
((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
@@ -1502,7 +1502,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc)
-#define HAS_MSO(i915) (GRAPHICS_VER(i915) >= 12)
+#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
@@ -1535,7 +1535,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
-#define HAS_LSPCON(dev_priv) (IS_GRAPHICS_VER(dev_priv, 9, 10))
+#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
/* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
@@ -1549,7 +1549,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->display.pipe_mask != 0)
-#define HAS_VRR(i915) (GRAPHICS_VER(i915) >= 11)
+#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
#define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
@@ -1579,7 +1579,7 @@ i915_print_iommu_status(struct drm_i915_private *i915,
struct drm_printer *p);
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv)
{
- return GRAPHICS_VER(dev_priv) >= 6 && intel_vtd_active(dev_priv);
+ return DISPLAY_VER(dev_priv) >= 6 && intel_vtd_active(dev_priv);
}
static inline bool
--
2.34.1
[Intel-gfx] [PATCH 2/2] drm/i915: Introduce ilk_pch_pre_enable()
From: Ville Syrjälä
Complete the ilk pch modeset abstraction by adding ilk_pch_pre_enable().
I did the disable vs. post_disable split already for the disable
sequence, but the enable sequence was still left with the naked
ilk_fdi_pll_enable() call for some reason.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_pch_display.c | 14 ++
drivers/gpu/drm/i915/display/intel_pch_display.h | 2 ++
3 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 80bc52425e47..1c82cfc54bd4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1858,10 +1858,7 @@ static void ilk_crtc_enable(struct intel_atomic_state
*state,
intel_encoders_pre_enable(state, crtc);
if (new_crtc_state->has_pch_encoder) {
- /* Note: FDI PLL enabling _must_ be done before we enable the
-* cpu pipes, hence this is separate from all the other fdi/pch
-* enabling. */
- ilk_fdi_pll_enable(new_crtc_state);
+ ilk_pch_pre_enable(state, crtc);
} else {
assert_fdi_tx_disabled(dev_priv, pipe);
assert_fdi_rx_disabled(dev_priv, pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
b/drivers/gpu/drm/i915/display/intel_pch_display.c
index a55c4bfacd0d..0c528c612cb2 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -211,6 +211,20 @@ static void ilk_disable_pch_transcoder(struct intel_crtc
*crtc)
}
}
+void ilk_pch_pre_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ /*
+* Note: FDI PLL enabling _must_ be done before we enable the
+* cpu pipes, hence this is separate from all the other fdi/pch
+* enabling.
+*/
+ ilk_fdi_pll_enable(crtc_state);
+}
+
/*
* Enable PCH resources required for PCH ports:
* - PCH PLLs
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h
b/drivers/gpu/drm/i915/display/intel_pch_display.h
index 2c387fe3a467..f915fa4241d7 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.h
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
@@ -10,6 +10,8 @@ struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
+void ilk_pch_pre_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
void ilk_pch_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void ilk_pch_disable(struct intel_atomic_state *state,
--
2.34.1
Re: [Intel-gfx] [PATCH 06/11] dma-buf: warn about containers in dma_resv object
On 1/24/22 14:03, Christian König wrote: Drivers should not add containers as shared fences to the dma_resv object, instead each fence should be added individually. Signed-off-by: Christian König Reviewed-by: Daniel Vetter Reviewed-by: Thomas Hellström Is there any indication that this triggers on existing drivers? Thomas
Re: [Intel-gfx] [PATCH 2/3] drm/arm/komeda : change driver to use drm_writeback_connector.base pointer
This makes sense given the other patches in your series, but it seems as
yet no one has anything to say about this. I don't have anything
specific to comment on other than it seems to make the correct changes
to komeda given the rest.
Reviewed-by: Carsten Haitzler
On 1/11/22 10:18, Kandpal, Suraj wrote:
Making changes to komeda driver because we had to change
drm_writeback_connector.base into a pointer the reason for which is
expained in the Patch (drm: add writeback pointers to drm_connector).
Signed-off-by: Kandpal, Suraj
---
drivers/gpu/drm/arm/display/komeda/komeda_crtc.c | 2 +-
drivers/gpu/drm/arm/display/komeda/komeda_kms.h | 3 ++-
drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c | 9 +
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
index 59172acb9738..eb37f41c1790 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
@@ -265,7 +265,7 @@ komeda_crtc_do_flush(struct drm_crtc *crtc,
if (slave && has_bit(slave->id, kcrtc_st->affected_pipes))
komeda_pipeline_update(slave, old->state);
- conn_st = wb_conn ? wb_conn->base.base.state : NULL;
+ conn_st = wb_conn ? wb_conn->base.base->state : NULL;
if (conn_st && conn_st->writeback_job)
drm_writeback_queue_job(_conn->base, conn_st);
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h
index 456f3c435719..8d83883a1d99 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h
@@ -53,6 +53,7 @@ struct komeda_plane_state {
* struct komeda_wb_connector
*/
struct komeda_wb_connector {
+ struct drm_connector conn;
/** @base: _writeback_connector */
struct drm_writeback_connector base;
@@ -136,7 +137,7 @@ struct komeda_kms_dev {
static inline bool is_writeback_only(struct drm_crtc_state *st)
{
struct komeda_wb_connector *wb_conn = to_kcrtc(st->crtc)->wb_conn;
- struct drm_connector *conn = wb_conn ? _conn->base.base : NULL;
+ struct drm_connector *conn = wb_conn ? wb_conn->base.base : NULL;
return conn && (st->connector_mask == BIT(drm_connector_index(conn)));
}
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
b/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
index e465cc4879c9..0caaf483276d 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
@@ -51,7 +51,7 @@ komeda_wb_encoder_atomic_check(struct drm_encoder *encoder,
return -EINVAL;
}
- wb_layer = to_kconn(to_wb_conn(conn_st->connector))->wb_layer;
+ wb_layer =
to_kconn(drm_connector_to_writeback(conn_st->connector))->wb_layer;
/*
* No need for a full modested when the only connector changed is the
@@ -123,7 +123,7 @@ komeda_wb_connector_fill_modes(struct drm_connector
*connector,
static void komeda_wb_connector_destroy(struct drm_connector *connector)
{
drm_connector_cleanup(connector);
- kfree(to_kconn(to_wb_conn(connector)));
+ kfree(to_kconn(drm_connector_to_writeback(connector)));
}
static const struct drm_connector_funcs komeda_wb_connector_funcs = {
@@ -155,6 +155,7 @@ static int komeda_wb_connector_add(struct komeda_kms_dev
*kms,
kwb_conn->wb_layer = kcrtc->master->wb_layer;
wb_conn = _conn->base;
+ wb_conn->base = _conn->conn;
wb_conn->encoder.possible_crtcs = BIT(drm_crtc_index(>base));
formats = komeda_get_layer_fourcc_list(>fmt_tbl,
@@ -171,9 +172,9 @@ static int komeda_wb_connector_add(struct komeda_kms_dev
*kms,
return err;
}
- drm_connector_helper_add(_conn->base, _wb_conn_helper_funcs);
+ drm_connector_helper_add(wb_conn->base, _wb_conn_helper_funcs);
- info = _conn->base.base.display_info;
+ info = _conn->base.base->display_info;
info->bpc = __fls(kcrtc->master->improc->supported_color_depths);
info->color_formats = kcrtc->master->improc->supported_color_formats;
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Lock dpt_obj around set_cache_level.
== Series Details ==
Series: drm/i915: Lock dpt_obj around set_cache_level.
URL : https://patchwork.freedesktop.org/series/99245/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22080
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22080 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22080, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/index.html
Participating hosts (48 -> 43)
--
Missing(5): fi-hsw-4200u fi-bsw-cyan fi-icl-u2 fi-ctg-p8600 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22080:
### IGT changes ###
Possible regressions
* igt@gem_sync@basic-each:
- fi-skl-6600u: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-skl-6600u/igt@gem_s...@basic-each.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/fi-skl-6600u/igt@gem_s...@basic-each.html
* igt@kms_busy@basic@modeset:
- bat-adlp-4: NOTRUN -> [DMESG-WARN][3] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/bat-adlp-4/igt@kms_busy@ba...@modeset.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_busy@basic@flip:
- {bat-adlp-6}: NOTRUN -> [DMESG-WARN][4] +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/bat-adlp-6/igt@kms_busy@ba...@flip.html
Known issues
Here are the changes found in Patchwork_22080 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#109315]) +17
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u: [PASS][6] -> [FAIL][7] ([fdo#103375])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][8] ([i915#2722] / [i915#4312])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/fi-skl-6600u/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][9] ([i915#541]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
- fi-bsw-kefka: [DMESG-FAIL][11] ([i915#541]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][13] ([i915#3303]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
- bat-adlp-4: [DMESG-WARN][15] -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-adlp-4/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/bat-adlp-4/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html
- {bat-adlp-6}: [DMESG-WARN][17] -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-adlp-6/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/bat-adlp-6/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html
Warnings
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][19] -> [DMESG-FAIL][20] ([i915#4494])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it
Re: [Intel-gfx] [RFC PATCH 5/5] drm/i915/flat-CCS: handle creation and destruction of flat CCS bo's
Hi, Adrian
On 1/21/22 23:22, Adrian Larumbe wrote:
When a flat-CCS lmem-bound BO is evicted onto smem for the first time, a
separate swap gem object is created to hold the contents of the CCS block.
It is assumed that, for a flat-CCS bo to be migrated back onto lmem, it
should've begun its life in lmem.
It also handles destruction of the swap bo when the original TTM object
reaches the end of its life.
Signed-off-by: Adrian Larumbe
While allocating a separate object for the CCS data is certainly
possible, it poses some additional difficulties that have not been
addressed here.
The CCS object needs to share the dma_resv of the original object. That
is because the CCS object needs to be locked and validated when we process it,
and we
can only trylock within the ttm move callback which might therefore fail
and isn't sufficient on swapin. We'd need to create some
i915_gem_object_create_region_locked() that wraps ttm_bo_init_reserved().
Furthermore destruction also becomes complicated, as the main object
owns a refcount on the CCS object, but the CCS object also needs a
refcount on the dma_resv part of the main object which will create a
refcount loop requiring an additional dma_resv refcount for objects to
resolve, similar to how we've solved this for shared dma_resv shared with vms.
Also shouldn't we be destroying the CCS object when data is moved back into
lmem?
Anyway, when we've earlier discussed how to handle this, we've discussed a
solution where the struct ttm_tt was given an inflated size on creation to
accommodate also the CCS data at the end. That would waste some memory if we
ever were to migrate such an object to system while decompressing, but
otherwise greatly simplify the handling. Basically we'd only look at whether
the object is flat-CCS enabled in i915_ttm_tt_create() and inflate the ttm_tt
size.
This requires an additional size parameter to ttm_tt_init(), but I've once discussed this with Christian König, and he didn't seem to object at the time. (+CC Christian König).
Thanks,
Thomas
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 11 +++
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 78 +++-
2 files changed, 87 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 84cae740b4a5..24708d6bfd9c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -474,11 +474,22 @@ static int i915_ttm_shrink(struct drm_i915_gem_object
*obj, unsigned int flags)
static void i915_ttm_delete_mem_notify(struct ttm_buffer_object *bo)
{
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+ struct drm_i915_private *i915 =
+ container_of(bo->bdev, typeof(*i915), bdev);
if (likely(obj)) {
__i915_gem_object_pages_fini(obj);
i915_ttm_free_cached_io_rsgt(obj);
}
+
+ if (HAS_FLAT_CCS(i915) && obj->flat_css.enabled) {
+ struct drm_i915_gem_object *swap_obj = obj->flat_css.swap;
+
+ if (swap_obj) {
+ swap_obj->base.funcs->free(_obj->base);
+ obj->flat_css.swap = NULL;
+ }
+ }
}
static struct i915_refct_sgt *i915_ttm_tt_get_st(struct ttm_tt *ttm)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 1de306c03aaf..3479c4a37bd8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -162,6 +162,56 @@ int i915_ttm_move_notify(struct ttm_buffer_object *bo)
return 0;
}
+static int
+i915_ccs_handle_move(struct drm_i915_gem_object *obj,
+struct ttm_resource *dst_mem)
+{
+ struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
+ struct drm_i915_private *i915 = container_of(bo->bdev, typeof(*i915),
+bdev);
+ struct intel_memory_region *dst_reg;
+ size_t ccs_blk_size;
+ int ret;
+
+ dst_reg = i915_ttm_region(bo->bdev, dst_mem->mem_type);
+ ccs_blk_size = GET_CCS_SIZE(i915, obj->base.size);
+
+ if (dst_reg->type != INTEL_MEMORY_LOCAL &&
+ dst_reg->type != INTEL_MEMORY_SYSTEM) {
+ DRM_DEBUG_DRIVER("Wrong memory region when using flat CCS.\n");
+ return -EINVAL;
+ }
+
+ if (dst_reg->type == INTEL_MEMORY_LOCAL &&
+ (obj->flat_css.swap == NULL ||
!i915_gem_object_has_pages(obj->flat_css.swap))) {
+ /*
+* All BOs begin their life cycle in smem, even if meant to be
+* lmem-bound. Then, upon running the execbuf2 ioctl, get moved
+* onto lmem before first use. Therefore, migrating a flat-CCS
+* lmem-only buffer into lmem means a CCS swap buffer had
already
+* been allocated when first
Re: [Intel-gfx] [PATCH 08/11] dma-buf: add dma_fence_chain_contained helper
On 1/24/22 14:03, Christian König wrote:
It's a reoccurring pattern that we need to extract the fence
from a dma_fence_chain object. Add a helper for this.
Signed-off-by: Christian König
Reviewed-by: Thomas Hellström
---
drivers/dma-buf/dma-fence-chain.c | 6 ++
include/linux/dma-fence-chain.h | 15 +++
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/dma-buf/dma-fence-chain.c
b/drivers/dma-buf/dma-fence-chain.c
index 084c6927b735..06f8ef97c6e8 100644
--- a/drivers/dma-buf/dma-fence-chain.c
+++ b/drivers/dma-buf/dma-fence-chain.c
@@ -148,8 +148,7 @@ static bool dma_fence_chain_enable_signaling(struct
dma_fence *fence)
dma_fence_get(>base);
dma_fence_chain_for_each(fence, >base) {
- struct dma_fence_chain *chain = to_dma_fence_chain(fence);
- struct dma_fence *f = chain ? chain->fence : fence;
+ struct dma_fence *f = dma_fence_chain_contained(fence);
dma_fence_get(f);
if (!dma_fence_add_callback(f, >cb, dma_fence_chain_cb)) {
@@ -165,8 +164,7 @@ static bool dma_fence_chain_enable_signaling(struct
dma_fence *fence)
static bool dma_fence_chain_signaled(struct dma_fence *fence)
{
dma_fence_chain_for_each(fence, fence) {
- struct dma_fence_chain *chain = to_dma_fence_chain(fence);
- struct dma_fence *f = chain ? chain->fence : fence;
+ struct dma_fence *f = dma_fence_chain_contained(fence);
if (!dma_fence_is_signaled(f)) {
dma_fence_put(fence);
diff --git a/include/linux/dma-fence-chain.h b/include/linux/dma-fence-chain.h
index ee906b659694..10d51bcdf7b7 100644
--- a/include/linux/dma-fence-chain.h
+++ b/include/linux/dma-fence-chain.h
@@ -66,6 +66,21 @@ to_dma_fence_chain(struct dma_fence *fence)
return container_of(fence, struct dma_fence_chain, base);
}
+/**
+ * dma_fence_chain_contained - return the contained fence
+ * @fence: the fence to test
+ *
+ * If the fence is a dma_fence_chain the function returns the fence contained
+ * inside the chain object, otherwise it returns the fence itself.
+ */
+static inline struct dma_fence *
+dma_fence_chain_contained(struct dma_fence *fence)
+{
+ struct dma_fence_chain *chain = to_dma_fence_chain(fence);
+
+ return chain ? chain->fence : fence;
+}
+
/**
* dma_fence_chain_alloc
*
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg2: Add Wa_18018781329 (rev7)
On Sun, Jan 23, 2022 at 11:33:55PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/dg2: Add Wa_18018781329 (rev7)
> URL : https://patchwork.freedesktop.org/series/99128/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11120_full -> Patchwork_22072_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_22072_full absolutely need to
> be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_22072_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Participating hosts (10 -> 11)
> --
>
> Additional (1): shard-tglu
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_22072_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@i915_pm_sseu@full-enable:
> - shard-skl: NOTRUN -> [FAIL][1]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22072/shard-skl6/igt@i915_pm_s...@full-enable.html
https://gitlab.freedesktop.org/drm/intel/-/issues/3524 is back.
Patch applied to drm-intel-gt-next. Thanks Swathi for the review.
Matt
>
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@gem_ctx_persistence@smoketest:
> - {shard-tglu}: NOTRUN -> [INCOMPLETE][2]
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22072/shard-tglu-7/igt@gem_ctx_persiste...@smoketest.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_22072_full that come from known
> issues:
>
> ### CI changes ###
>
> Issues hit
>
> * boot:
> - shard-apl: ([PASS][3], [PASS][4], [PASS][5], [PASS][6],
> [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12],
> [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18],
> [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24],
> [PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30],
> [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36],
> [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42],
> [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48],
> [PASS][49], [PASS][50], [FAIL][51], [PASS][52]) ([i915#4386])
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl1/boot.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl1/boot.html
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl1/boot.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl1/boot.html
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl2/boot.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl2/boot.html
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl2/boot.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl2/boot.html
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl3/boot.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl3/boot.html
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl3/boot.html
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl4/boot.html
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl4/boot.html
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl4/boot.html
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl6/boot.html
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl6/boot.html
>[19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl6/boot.html
>[20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl6/boot.html
>[21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl7/boot.html
>[22]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl7/boot.html
>[23]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl7/boot.html
>[24]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl7/boot.html
>[25]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl8/boot.html
>[26]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl8/boot.html
>[27]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl8/boot.html
>[28]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22072/shard-apl2/boot.html
>[29]:
>
Re: [Intel-gfx] [PATCH V2 0/7] DRM kmap() fixes and kmap_local_page() conversions
On Mon, Jan 24, 2022 at 01:08:26PM +0100, Christian König wrote: > Am 24.01.22 um 02:54 schrieb ira.we...@intel.com: > > From: Ira Weiny > > > > Changes from V1: > > Use memcpy_to_page() where appropriate > > Rebased to latest > > > > The kmap() call may cause issues with work being done with persistent > > memory. > > For this and other reasons it is being deprecated. > > I'm really wondering how we should be able to implement the kernel mapping > without kmap in TTM. > > > This series starts by converting the last easy kmap() uses in the drm tree > > to > > kmap_local_page(). > > > > The final 2 patches fix bugs found while working on the ttm_bo_kmap_ttm() > > conversion. They are valid fixes but were found via code inspection not > > because of any actual bug so don't require a stable tag.[1] > > > > There is one more call to kmap() used in ttm_bo_kmap_ttm(). Unfortunately, > > fixing this is not straight forward so it is left to future work.[2] > > Patches #2, #4, #6 and #7 are Reviewed-by: Christian König > Christian, Would you prefer I send those 4 to you as a separate series? > > How to you now want to push those upstream? I can pick them up for the AMD > tree like Daniel suggested or you can push them through something else. You picking them up from this series is ok as well. Daniel will you take #1, #3, and #5? Thanks, Ira > > Regards, > Christian. > > > > > [1] > > https://lore.kernel.org/lkml/fb71af05-a889-8f6e-031b-426b58a64...@amd.com/ > > [2] > > https://lore.kernel.org/lkml/20211215210949.gw3538...@iweiny-desk2.sc.intel.com/ > > > > > > Ira Weiny (7): > > drm/i915: Replace kmap() with kmap_local_page() > > drm/amd: Replace kmap() with kmap_local_page() > > drm/gma: Remove calls to kmap() > > drm/radeon: Replace kmap() with kmap_local_page() > > drm/msm: Alter comment to use kmap_local_page() > > drm/amdgpu: Ensure kunmap is called on error > > drm/radeon: Ensure kunmap is called on error > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 > > drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 1 + > > drivers/gpu/drm/gma500/gma_display.c | 6 ++ > > drivers/gpu/drm/gma500/mmu.c | 8 > > drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 6 ++ > > drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 8 > > drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 4 ++-- > > drivers/gpu/drm/i915/gt/shmem_utils.c | 7 ++- > > drivers/gpu/drm/i915/i915_gem.c | 8 > > drivers/gpu/drm/i915/i915_gpu_error.c | 4 ++-- > > drivers/gpu/drm/msm/msm_gem_submit.c | 4 ++-- > > drivers/gpu/drm/radeon/radeon_ttm.c | 4 ++-- > > drivers/gpu/drm/radeon/radeon_uvd.c | 1 + > > 13 files changed, 32 insertions(+), 37 deletions(-) > > > > -- > > 2.31.1 > > >
[Intel-gfx] [PATCH 1/5] drm/i915: Skip dsc readout if the transcoder is disabled
From: Ville Syrjälä Tryingf to do readout when we don't even have a cpu transcoder is not a great idea. Don't do it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 80bc52425e47..e32a7a1e7ba0 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4380,13 +4380,13 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, active = true; } + if (!active) + goto out; + intel_dsc_get_config(pipe_config); if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config->dsc.compression_enable) intel_uncompressed_joiner_get_config(pipe_config); - if (!active) - goto out; - if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || DISPLAY_VER(dev_priv) >= 11) intel_get_transcoder_timings(crtc, pipe_config); -- 2.34.1
[Intel-gfx] [PATCH 2/5] drm/i915: Simplify intel_dsc_source_support()
From: Ville Syrjälä We can simplify the icl check in intel_dsc_source_support() by noting that the only case when DSC is not supported is when using transcoder A. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vdsc.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 9b05f93ed8bc..3faea903b9ae 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -341,19 +341,14 @@ bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - enum pipe pipe = crtc->pipe; if (!INTEL_INFO(i915)->display.has_dsc) return false; - /* On TGL, DSC is supported on all Pipes */ if (DISPLAY_VER(i915) >= 12) return true; - if (DISPLAY_VER(i915) >= 11 && - (pipe != PIPE_A || cpu_transcoder == TRANSCODER_EDP || -cpu_transcoder == TRANSCODER_DSI_0 || -cpu_transcoder == TRANSCODER_DSI_1)) + if (DISPLAY_VER(i915) >= 11 && cpu_transcoder != TRANSCODER_A) return true; return false; -- 2.34.1
[Intel-gfx] [PATCH 3/5] drm/i915: Use per-device debugs for bigjoiner stuff
From: Ville Syrjälä
Specify which device we're talking about when spewing
bigjoiner debugs.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 22
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e32a7a1e7ba0..c23c854f212f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7600,6 +7600,7 @@ static int intel_atomic_check_bigjoiner(struct
intel_atomic_state *state,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
struct intel_crtc *slave_crtc, *master_crtc;
@@ -7617,9 +7618,10 @@ static int intel_atomic_check_bigjoiner(struct
intel_atomic_state *state,
slave_crtc = intel_dsc_get_bigjoiner_secondary(crtc);
if (!slave_crtc) {
- DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
- "CRTC + 1 to be used, doesn't exist\n",
- crtc->base.base.id, crtc->base.name);
+ drm_dbg_kms(>drm,
+ "[CRTC:%d:%s] Big joiner configuration requires "
+ "CRTC + 1 to be used, doesn't exist\n",
+ crtc->base.base.id, crtc->base.name);
return -EINVAL;
}
@@ -7633,16 +7635,18 @@ static int intel_atomic_check_bigjoiner(struct
intel_atomic_state *state,
if (slave_crtc_state->uapi.enable)
goto claimed;
- DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
- slave_crtc->base.base.id, slave_crtc->base.name);
+ drm_dbg_kms(>drm,
+ "[CRTC:%d:%s] Used as slave for big joiner\n",
+ slave_crtc->base.base.id, slave_crtc->base.name);
return copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
claimed:
- DRM_DEBUG_KMS("[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
- "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
- slave_crtc->base.base.id, slave_crtc->base.name,
- master_crtc->base.base.id, master_crtc->base.name);
+ drm_dbg_kms(>drm,
+ "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
+ "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
+ slave_crtc->base.base.id, slave_crtc->base.name,
+ master_crtc->base.base.id, master_crtc->base.name);
return -EINVAL;
}
--
2.34.1
[Intel-gfx] [PATCH 5/5] drm/i915: Move dsc/joiner enable into hsw_crtc_enable()
From: Ville Syrjälä
Lift the dsc/joiner enable up from the wonky places where it
currently sits (ddi .pre_enable() or icl_ddi_bigjoiner_pre_enable())
into hsw_crtc_enable() where we write the other per-pipe stuff
as well. Makes the transcoder vs. pipe split less confusing.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 6 --
drivers/gpu/drm/i915/display/intel_display.c | 12 +---
2 files changed, 5 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 2f20abc5122d..5d1f7d6218c5 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2425,9 +2425,6 @@ static void tgl_ddi_pre_enable_dp(struct
intel_atomic_state *state,
intel_ddi_enable_fec(encoder, crtc_state);
intel_dsc_dp_pps_write(encoder, crtc_state);
-
- if (!crtc_state->bigjoiner)
- intel_dsc_enable(crtc_state);
}
static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -2493,9 +2490,6 @@ static void hsw_ddi_pre_enable_dp(struct
intel_atomic_state *state,
intel_ddi_enable_pipe_clock(encoder, crtc_state);
intel_dsc_dp_pps_write(encoder, crtc_state);
-
- if (!crtc_state->bigjoiner)
- intel_dsc_enable(crtc_state);
}
static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d2906434ab3f..13b1de03640d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1974,7 +1974,6 @@ static void hsw_set_frame_start_delay(const struct
intel_crtc_state *crtc_state)
static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
const struct intel_crtc_state
*crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *master_crtc_state;
struct intel_crtc *master_crtc;
struct drm_connector_state *conn_state;
@@ -2004,12 +2003,6 @@ static void icl_ddi_bigjoiner_pre_enable(struct
intel_atomic_state *state,
if (crtc_state->bigjoiner_slave)
intel_encoders_pre_enable(state, master_crtc);
-
- /* need to enable VDSC, which we skipped in pre-enable */
- intel_dsc_enable(crtc_state);
-
- if (DISPLAY_VER(dev_priv) >= 13)
- intel_uncompressed_joiner_enable(crtc_state);
}
static void hsw_configure_cpu_transcoder(const struct intel_crtc_state
*crtc_state)
@@ -2057,6 +2050,11 @@ static void hsw_crtc_enable(struct intel_atomic_state
*state,
icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
}
+ intel_dsc_enable(new_crtc_state);
+
+ if (DISPLAY_VER(dev_priv) >= 13)
+ intel_uncompressed_joiner_enable(new_crtc_state);
+
intel_set_pipe_src_size(new_crtc_state);
if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
bdw_set_pipemisc(new_crtc_state);
--
2.34.1
[Intel-gfx] [PATCH 4/5] drm/i915: Extract hsw_configure_cpu_transcoder()
From: Ville Syrjälä
Pull the transcoder specific modeset steps into a single place.
With bigoiner we need to keep in mind wheher we're dealing with
the transcoder or the pipe, and a slightly higher level split makes
that easier.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 38
1 file changed, 23 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c23c854f212f..d2906434ab3f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2012,6 +2012,27 @@ static void icl_ddi_bigjoiner_pre_enable(struct
intel_atomic_state *state,
intel_uncompressed_joiner_enable(crtc_state);
}
+static void hsw_configure_cpu_transcoder(const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ intel_set_transcoder_timings(crtc_state);
+
+ if (cpu_transcoder != TRANSCODER_EDP)
+ intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
+ crtc_state->pixel_multiplier - 1);
+
+ if (crtc_state->has_pch_encoder)
+ intel_cpu_transcoder_set_m_n(crtc_state,
+_state->fdi_m_n, NULL);
+
+ hsw_set_frame_start_delay(crtc_state);
+
+ hsw_set_transconf(crtc_state);
+}
+
static void hsw_crtc_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -2040,21 +2061,8 @@ static void hsw_crtc_enable(struct intel_atomic_state
*state,
if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
bdw_set_pipemisc(new_crtc_state);
- if (!new_crtc_state->bigjoiner_slave &&
!transcoder_is_dsi(cpu_transcoder)) {
- intel_set_transcoder_timings(new_crtc_state);
-
- if (cpu_transcoder != TRANSCODER_EDP)
- intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
- new_crtc_state->pixel_multiplier - 1);
-
- if (new_crtc_state->has_pch_encoder)
- intel_cpu_transcoder_set_m_n(new_crtc_state,
-_crtc_state->fdi_m_n,
NULL);
-
- hsw_set_frame_start_delay(new_crtc_state);
-
- hsw_set_transconf(new_crtc_state);
- }
+ if (!new_crtc_state->bigjoiner_slave &&
!transcoder_is_dsi(cpu_transcoder))
+ hsw_configure_cpu_transcoder(new_crtc_state);
crtc->active = true;
--
2.34.1
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/edid: Support type 7 timings
== Series Details == Series: drm/edid: Support type 7 timings URL : https://patchwork.freedesktop.org/series/99250/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22082_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22082_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22082_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 10) -- Missing(1): shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22082_full: ### IGT changes ### Possible regressions * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][1] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-apl1/igt@gem_userptr_bl...@input-checking.html Known issues Here are the changes found in Patchwork_22082_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@many-contexts: - shard-tglb: [PASS][2] -> [FAIL][3] ([i915#2410]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html * igt@gem_ctx_persistence@smoketest: - shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2896]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb3/igt@gem_ctx_persiste...@smoketest.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-tglb6/igt@gem_ctx_persiste...@smoketest.html * igt@gem_eio@in-flight-contexts-10ms: - shard-iclb: [PASS][6] -> [TIMEOUT][7] ([i915#3070]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb8/igt@gem_...@in-flight-contexts-10ms.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-iclb5/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_exec_balancer@parallel-balancer: - shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb2/igt@gem_exec_balan...@parallel-balancer.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-iclb3/igt@gem_exec_balan...@parallel-balancer.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][10] ([i915#2846]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-skl9/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: NOTRUN -> [FAIL][11] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-kbl4/igt@gem_exec_fair@basic-none-s...@rcs0.html - shard-tglb: NOTRUN -> [FAIL][12] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-tglb5/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-kbl3/igt@gem_exec_fair@basic-n...@vcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-kbl7/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][15] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-iclb4/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-tglb: [PASS][16] -> [FAIL][17] ([i915#2842]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-tglb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_lmem_swapping@basic: - shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-kbl7/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@smem-oom: - shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-skl8/igt@gem_lmem_swapp...@smem-oom.html * igt@gem_pread@exhaustion: - shard-kbl: NOTRUN -> [WARN][20] ([i915#2658]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-kbl1/igt@gem_pr...@exhaustion.html - shard-skl: NOTRUN -> [WARN][21]
[Intel-gfx] ✓ Fi.CI.BAT: success for Second round of i915_reg.h splitting (rev2)
== Series Details ==
Series: Second round of i915_reg.h splitting (rev2)
URL : https://patchwork.freedesktop.org/series/99079/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22094
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/index.html
Participating hosts (51 -> 45)
--
Additional (1): fi-pnv-d510
Missing(7): shard-tglu fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 shard-rkl
shard-dg1 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22094 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][1] ([fdo#109271]) +39 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live:
- fi-skl-6600u: NOTRUN -> [FAIL][2] ([i915#4547])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-skl-6600u/igt@i915_selft...@live.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][3] ([i915#2927] / [i915#4528])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][4] ([fdo#109271] / [i915#2403] /
[i915#4312])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-pnv-d510/igt@run...@aborted.html
- fi-skl-6600u: NOTRUN -> [FAIL][5] ([i915#1436] / [i915#4312])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-skl-6600u/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][6] ([i915#541]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
- fi-bsw-kefka: [DMESG-FAIL][8] ([i915#541]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][10] ([i915#4494]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][12] ([i915#4269]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
Warnings
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][14] -> [DMESG-FAIL][15] ([i915#4494])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-4770:[INCOMPLETE][16] ([i915#3303]) -> [INCOMPLETE][17]
([i915#4785])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Build changes
-
* Linux:
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate
== Series Details == Series: series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate URL : https://patchwork.freedesktop.org/series/99278/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22089_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22089_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22089_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 10) -- Missing(1): shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22089_full: ### IGT changes ### Possible regressions * igt@gem_create@create-massive: - shard-kbl: NOTRUN -> [DMESG-WARN][1] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-kbl1/igt@gem_cre...@create-massive.html - shard-skl: NOTRUN -> [DMESG-WARN][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-skl9/igt@gem_cre...@create-massive.html * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][3] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-apl6/igt@gem_userptr_bl...@input-checking.html * igt@kms_flip@flip-vs-modeset-vs-hang@a-edp1: - shard-tglb: [PASS][4] -> [INCOMPLETE][5] +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb3/igt@kms_flip@flip-vs-modeset-vs-h...@a-edp1.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-tglb7/igt@kms_flip@flip-vs-modeset-vs-h...@a-edp1.html Known issues Here are the changes found in Patchwork_22089_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-kbl: [PASS][6] -> [INCOMPLETE][7] ([i915#794]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-kbl6/igt@gem_ctx_isolation@preservation...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-kbl4/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_ctx_isolation@preservation-s3@vcs1: - shard-tglb: [PASS][8] -> [DMESG-WARN][9] ([i915#2411] / [i915#2867]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb2/igt@gem_ctx_isolation@preservation...@vcs1.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-tglb6/igt@gem_ctx_isolation@preservation...@vcs1.html * igt@gem_ctx_persistence@many-contexts: - shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2410]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-tglb7/igt@gem_ctx_persiste...@many-contexts.html * igt@gem_exec_balancer@parallel: - shard-iclb: [PASS][12] -> [SKIP][13] ([i915#4525]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb4/igt@gem_exec_balan...@parallel.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-iclb7/igt@gem_exec_balan...@parallel.html * igt@gem_exec_capture@pi@rcs0: - shard-skl: [PASS][14] -> [INCOMPLETE][15] ([i915#4547]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl7/igt@gem_exec_capture@p...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-skl10/igt@gem_exec_capture@p...@rcs0.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: NOTRUN -> [FAIL][16] ([i915#2846]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-kbl1/igt@gem_exec_f...@basic-deadline.html - shard-skl: NOTRUN -> [FAIL][17] ([i915#2846]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-skl8/igt@gem_exec_f...@basic-deadline.html - shard-glk: [PASS][18] -> [FAIL][19] ([i915#2846]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk9/igt@gem_exec_f...@basic-deadline.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-glk7/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-glk: [PASS][20] -> [FAIL][21] ([i915#2842]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk8/igt@gem_exec_fair@basic-none-sh...@rcs0.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-glk2/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-tglb: [PASS][22] ->
Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: Move dsc/joiner enable into hsw_crtc_enable()
On Tue, Jan 25, 2022 at 08:50:47AM +0200, Jani Nikula wrote:
> On Tue, 25 Jan 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Lift the dsc/joiner enable up from the wonky places where it
> > currently sits (ddi .pre_enable() or icl_ddi_bigjoiner_pre_enable())
> > into hsw_crtc_enable() where we write the other per-pipe stuff
> > as well. Makes the transcoder vs. pipe split less confusing.
> >
> > For DSI this results in slight reordering between the dsc/joiner
> > enable vs. transcoder timings setup, but I can't really think
> > why that should cause any issues since the transcoder isn't yet
> > enabled at that point.
> >
> > v2: Take care of dsi (Jani)
> >
> > Cc: Jani Nikula
> > Signed-off-by: Ville Syrjälä
>
> Reviewed-by: Jani Nikula
>
> One question inline.
>
> > ---
> > drivers/gpu/drm/i915/display/icl_dsi.c | 2 --
> > drivers/gpu/drm/i915/display/intel_ddi.c | 6 --
> > drivers/gpu/drm/i915/display/intel_display.c | 12 +---
> > 3 files changed, 5 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index 95f49535fa6e..16a611f7d659 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -1233,8 +1233,6 @@ static void gen11_dsi_pre_enable(struct
> > intel_atomic_state *state,
> >
> > intel_dsc_dsi_pps_write(encoder, pipe_config);
> >
> > - intel_dsc_enable(pipe_config);
> > -
> > /* step6c: configure transcoder timings */
> > gen11_dsi_set_transcoder_timings(encoder, pipe_config);
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 2f20abc5122d..5d1f7d6218c5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -2425,9 +2425,6 @@ static void tgl_ddi_pre_enable_dp(struct
> > intel_atomic_state *state,
> > intel_ddi_enable_fec(encoder, crtc_state);
> >
> > intel_dsc_dp_pps_write(encoder, crtc_state);
> > -
> > - if (!crtc_state->bigjoiner)
> > - intel_dsc_enable(crtc_state);
> > }
> >
> > static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
> > @@ -2493,9 +2490,6 @@ static void hsw_ddi_pre_enable_dp(struct
> > intel_atomic_state *state,
> > intel_ddi_enable_pipe_clock(encoder, crtc_state);
> >
> > intel_dsc_dp_pps_write(encoder, crtc_state);
> > -
> > - if (!crtc_state->bigjoiner)
> > - intel_dsc_enable(crtc_state);
> > }
> >
> > static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index d2906434ab3f..13b1de03640d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1974,7 +1974,6 @@ static void hsw_set_frame_start_delay(const struct
> > intel_crtc_state *crtc_state)
> > static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
> > const struct intel_crtc_state
> > *crtc_state)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > struct intel_crtc_state *master_crtc_state;
> > struct intel_crtc *master_crtc;
> > struct drm_connector_state *conn_state;
> > @@ -2004,12 +2003,6 @@ static void icl_ddi_bigjoiner_pre_enable(struct
> > intel_atomic_state *state,
> >
> > if (crtc_state->bigjoiner_slave)
> > intel_encoders_pre_enable(state, master_crtc);
> > -
> > - /* need to enable VDSC, which we skipped in pre-enable */
> > - intel_dsc_enable(crtc_state);
> > -
> > - if (DISPLAY_VER(dev_priv) >= 13)
> > - intel_uncompressed_joiner_enable(crtc_state);
> > }
> >
> > static void hsw_configure_cpu_transcoder(const struct intel_crtc_state
> > *crtc_state)
> > @@ -2057,6 +2050,11 @@ static void hsw_crtc_enable(struct
> > intel_atomic_state *state,
> > icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
> > }
> >
> > + intel_dsc_enable(new_crtc_state);
> > +
> > + if (DISPLAY_VER(dev_priv) >= 13)
> > + intel_uncompressed_joiner_enable(new_crtc_state);
> > +
>
> Should this call be moved inside intel_dsc_enable()? I mean it's not
> compression, but it's the same splitter/joiner/etc. block that handles
> all of this?
We probably want to restructure the code a bit more so that
it's not all pretending to be about dsc. Dunno if we should just have
some dss_enable() thing to configure everything about the
splitter/joiner stuff. Although maybe there are some conflicting
sequencing requirements for MSO, so maybe not all of it can go into
the same place? In which case I quess we should just have some kind
of joiner_enable() thing.
--
Ville Syrjälä
Intel
[Intel-gfx] ✗ Fi.CI.BAT: failure for Fix up request cancel (rev3)
== Series Details == Series: Fix up request cancel (rev3) URL : https://patchwork.freedesktop.org/series/99173/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11130 -> Patchwork_22095 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22095 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22095, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/index.html Participating hosts (39 -> 42) -- Additional (7): fi-kbl-soraka bat-dg1-6 bat-dg1-5 bat-adlp-4 bat-rpls-1 bat-jsl-2 bat-jsl-1 Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-hsw-4200u fi-pnv-d510 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22095: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gtt: - fi-bdw-5557u: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11130/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html * igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling: - bat-adlp-4: NOTRUN -> [DMESG-WARN][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-adlp-4/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html Known issues Here are the changes found in Patchwork_22095 that come from known issues: ### IGT changes ### Issues hit * igt@fbdev@info: - bat-dg1-6: NOTRUN -> [SKIP][4] ([i915#2582]) +4 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-6/igt@fb...@info.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_exec_gttfill@basic: - bat-dg1-6: NOTRUN -> [SKIP][6] ([i915#4086]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-6/igt@gem_exec_gttf...@basic.html - bat-dg1-5: NOTRUN -> [SKIP][7] ([i915#4086]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-5/igt@gem_exec_gttf...@basic.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - bat-adlp-4: NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-adlp-4/igt@gem_lmem_swapp...@basic.html - fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_mmap@basic: - bat-dg1-6: NOTRUN -> [SKIP][11] ([i915#4083]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-6/igt@gem_m...@basic.html - bat-dg1-5: NOTRUN -> [SKIP][12] ([i915#4083]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-5/igt@gem_m...@basic.html * igt@gem_tiled_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][13] ([i915#4077]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-5: NOTRUN -> [SKIP][14] ([i915#4077]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-5/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-5: NOTRUN -> [SKIP][15] ([i915#4079]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-5/igt@gem_tiled_pread_basic.html - bat-adlp-4: NOTRUN -> [SKIP][16] ([i915#3282]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-adlp-4/igt@gem_tiled_pread_basic.html - bat-dg1-6: NOTRUN -> [SKIP][17] ([i915#4079]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-6/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-5: NOTRUN -> [SKIP][18] ([i915#1155]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html - bat-dg1-6: NOTRUN -> [SKIP][19] ([i915#1155]) [19]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: make static read-only array page_count const
== Series Details == Series: drm/i915/selftests: make static read-only array page_count const URL : https://patchwork.freedesktop.org/series/99252/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22085_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22085_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22085_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 10) -- Missing(1): shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22085_full: ### IGT changes ### Possible regressions * igt@gem_create@create-massive: - shard-kbl: NOTRUN -> [DMESG-WARN][1] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-kbl1/igt@gem_cre...@create-massive.html * igt@gem_userptr_blits@input-checking: - shard-skl: NOTRUN -> [DMESG-WARN][2] +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-skl10/igt@gem_userptr_bl...@input-checking.html - shard-apl: NOTRUN -> [DMESG-WARN][3] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-apl7/igt@gem_userptr_bl...@input-checking.html Known issues Here are the changes found in Patchwork_22085_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@many-contexts: - shard-iclb: [PASS][4] -> [FAIL][5] ([i915#2410]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb6/igt@gem_ctx_persiste...@many-contexts.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-iclb3/igt@gem_ctx_persiste...@many-contexts.html - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2410]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-tglb3/igt@gem_ctx_persiste...@many-contexts.html * igt@gem_eio@in-flight-contexts-10ms: - shard-skl: [PASS][8] -> [TIMEOUT][9] ([i915#3063]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl7/igt@gem_...@in-flight-contexts-10ms.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-skl9/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_eio@in-flight-contexts-1us: - shard-iclb: [PASS][10] -> [TIMEOUT][11] ([i915#3070]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb7/igt@gem_...@in-flight-contexts-1us.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-iclb2/igt@gem_...@in-flight-contexts-1us.html * igt@gem_eio@unwedge-stress: - shard-iclb: [PASS][12] -> [TIMEOUT][13] ([i915#2481] / [i915#3070]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb7/igt@gem_...@unwedge-stress.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-iclb2/igt@gem_...@unwedge-stress.html * igt@gem_exec_capture@pi@vecs0: - shard-skl: NOTRUN -> [INCOMPLETE][14] ([i915#4547]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-skl2/igt@gem_exec_capture@p...@vecs0.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][15] ([i915#2846]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-skl1/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271]) +95 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-skl10/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-glk: [PASS][17] -> [FAIL][18] ([i915#2842]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk8/igt@gem_exec_fair@basic-none-sh...@rcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-glk2/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-tglb: NOTRUN -> [FAIL][19] ([i915#2842]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-tglb2/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: [PASS][20] -> [FAIL][21] ([i915#2842]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-kbl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html [21]:
Re: [Intel-gfx] [PATCH 5/5] drm/i915: Move dsc/joiner enable into hsw_crtc_enable()
On Mon, 24 Jan 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Lift the dsc/joiner enable up from the wonky places where it
> currently sits (ddi .pre_enable() or icl_ddi_bigjoiner_pre_enable())
> into hsw_crtc_enable() where we write the other per-pipe stuff
> as well. Makes the transcoder vs. pipe split less confusing.
>
What about the enable call in DSI?
BR,
Jani.
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 --
> drivers/gpu/drm/i915/display/intel_display.c | 12 +---
> 2 files changed, 5 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 2f20abc5122d..5d1f7d6218c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2425,9 +2425,6 @@ static void tgl_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> intel_ddi_enable_fec(encoder, crtc_state);
>
> intel_dsc_dp_pps_write(encoder, crtc_state);
> -
> - if (!crtc_state->bigjoiner)
> - intel_dsc_enable(crtc_state);
> }
>
> static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
> @@ -2493,9 +2490,6 @@ static void hsw_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> intel_ddi_enable_pipe_clock(encoder, crtc_state);
>
> intel_dsc_dp_pps_write(encoder, crtc_state);
> -
> - if (!crtc_state->bigjoiner)
> - intel_dsc_enable(crtc_state);
> }
>
> static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d2906434ab3f..13b1de03640d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1974,7 +1974,6 @@ static void hsw_set_frame_start_delay(const struct
> intel_crtc_state *crtc_state)
> static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
>const struct intel_crtc_state
> *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc_state *master_crtc_state;
> struct intel_crtc *master_crtc;
> struct drm_connector_state *conn_state;
> @@ -2004,12 +2003,6 @@ static void icl_ddi_bigjoiner_pre_enable(struct
> intel_atomic_state *state,
>
> if (crtc_state->bigjoiner_slave)
> intel_encoders_pre_enable(state, master_crtc);
> -
> - /* need to enable VDSC, which we skipped in pre-enable */
> - intel_dsc_enable(crtc_state);
> -
> - if (DISPLAY_VER(dev_priv) >= 13)
> - intel_uncompressed_joiner_enable(crtc_state);
> }
>
> static void hsw_configure_cpu_transcoder(const struct intel_crtc_state
> *crtc_state)
> @@ -2057,6 +2050,11 @@ static void hsw_crtc_enable(struct intel_atomic_state
> *state,
> icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
> }
>
> + intel_dsc_enable(new_crtc_state);
> +
> + if (DISPLAY_VER(dev_priv) >= 13)
> + intel_uncompressed_joiner_enable(new_crtc_state);
> +
> intel_set_pipe_src_size(new_crtc_state);
> if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> bdw_set_pipemisc(new_crtc_state);
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 1/2] drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference
On Mon, 24 Jan 2022, Umesh Nerlige Ramappa
wrote:
> All timestamps returned by GuC for GuC PMU busyness are captured from
> GUC PM TIMESTAMP. Since this timestamp does not tick when GuC goes idle,
> kmd uses RING_TIMESTAMP to measure busyness of an engine with an active
> context. In further stress testing, the MMIO read of the RING_TIMESTAMP
> is seen to cause a rare hang. Resolve the issue by using gt specific
> timestamp from PM which is in sync with the GuC PM timestamp.
>
> Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to
> pmu")
> Signed-off-by: Umesh Nerlige Ramappa
> Reviewed-by: Alan Previn
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 5 ++
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 56 ++-
> drivers/gpu/drm/i915/i915_reg.h | 3 +-
> 3 files changed, 50 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index d59bbf49d1c2..697d9d66acef 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -215,6 +215,11 @@ struct intel_guc {
>* context usage for overflows.
>*/
> struct delayed_work work;
> +
> + /**
> + * @shift: Right shift value for the gpm timestamp
> + */
> + u32 shift;
> } timestamp;
>
> #ifdef CONFIG_DRM_I915_SELFTEST
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 1331ff91c5b0..66760f5df0c1 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1150,23 +1150,51 @@ static void guc_update_engine_gt_clks(struct
> intel_engine_cs *engine)
> }
> }
>
> -static void guc_update_pm_timestamp(struct intel_guc *guc,
> - struct intel_engine_cs *engine,
> - ktime_t *now)
> +static u32 gpm_timestamp_shift(struct intel_gt *gt)
> {
> - u32 gt_stamp_now, gt_stamp_hi;
> + intel_wakeref_t wakeref;
> + u32 reg, shift;
> +
> + with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> + reg = intel_uncore_read(gt->uncore, RPM_CONFIG0);
> +
> + shift = (reg & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
> + GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT;
> +
> + return 3 - shift;
> +}
> +
> +static u64 gpm_timestamp(struct intel_gt *gt)
> +{
> + u32 lo, hi, old_hi, loop = 0;
> +
> + hi = intel_uncore_read(gt->uncore, MISC_STATUS1);
> + do {
> + lo = intel_uncore_read(gt->uncore, MISC_STATUS0);
> + old_hi = hi;
> + hi = intel_uncore_read(gt->uncore, MISC_STATUS1);
> + } while (old_hi != hi && loop++ < 2);
> +
> + return ((u64)hi << 32) | lo;
> +}
See intel_uncore_read64_2x32().
> +
> +static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)
> +{
> + struct intel_gt *gt = guc_to_gt(guc);
> + u32 gt_stamp_lo, gt_stamp_hi;
> + u64 gpm_ts;
>
> lockdep_assert_held(>timestamp.lock);
>
> gt_stamp_hi = upper_32_bits(guc->timestamp.gt_stamp);
> - gt_stamp_now = intel_uncore_read(engine->uncore,
> - RING_TIMESTAMP(engine->mmio_base));
> + gpm_ts = gpm_timestamp(gt) >> guc->timestamp.shift;
> + gt_stamp_lo = lower_32_bits(gpm_ts);
> *now = ktime_get();
>
> - if (gt_stamp_now < lower_32_bits(guc->timestamp.gt_stamp))
> + if (gt_stamp_lo < lower_32_bits(guc->timestamp.gt_stamp))
> gt_stamp_hi++;
>
> - guc->timestamp.gt_stamp = ((u64)gt_stamp_hi << 32) | gt_stamp_now;
> + guc->timestamp.gt_stamp = ((u64)gt_stamp_hi << 32) | gt_stamp_lo;
> }
>
> /*
> @@ -1210,7 +1238,7 @@ static ktime_t guc_engine_busyness(struct
> intel_engine_cs *engine, ktime_t *now)
> stats_saved = *stats;
> gt_stamp_saved = guc->timestamp.gt_stamp;
> guc_update_engine_gt_clks(engine);
> - guc_update_pm_timestamp(guc, engine, now);
> + guc_update_pm_timestamp(guc, now);
> intel_gt_pm_put_async(gt);
> if (i915_reset_count(gpu_error) != reset_count) {
> *stats = stats_saved;
> @@ -1242,8 +1270,8 @@ static void __reset_guc_busyness_stats(struct intel_guc
> *guc)
>
> spin_lock_irqsave(>timestamp.lock, flags);
>
> + guc_update_pm_timestamp(guc, );
> for_each_engine(engine, gt, id) {
> - guc_update_pm_timestamp(guc, engine, );
> guc_update_engine_gt_clks(engine);
> engine->stats.guc.prev_total = 0;
> }
> @@ -1260,10 +1288,11 @@ static void __update_guc_busyness_stats(struct
> intel_guc *guc)
> ktime_t unused;
>
> spin_lock_irqsave(>timestamp.lock, flags);
> - for_each_engine(engine, gt, id) {
Re: [Intel-gfx] [PATCH 1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate
On Mon, 24 Jan 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use DISPLAY_VER rather than GRAPHICS_VER to determine
> availability of display hardware features.
>
> Signed-off-by: Ville Syrjälä
On both patches,
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_drv.h | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 44c1f98144b4..e2b8409f9174 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1463,8 +1463,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
> (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
>
> -#define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
> -#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \
> +#define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
> +#define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
> IS_GEMINILAKE(dev_priv) || \
> IS_KABYLAKE(dev_priv))
>
> @@ -1476,9 +1476,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define SUPPORTS_TV(dev_priv)
> (INTEL_INFO(dev_priv)->display.supports_tv)
> #define I915_HAS_HOTPLUG(dev_priv)
> (INTEL_INFO(dev_priv)->display.has_hotplug)
>
> -#define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2)
> +#define HAS_FW_BLC(dev_priv) (DISPLAY_VER(dev_priv) > 2)
> #define HAS_FBC(dev_priv)(INTEL_INFO(dev_priv)->display.fbc_mask != 0)
> -#define HAS_CUR_FBC(dev_priv)(!HAS_GMCH(dev_priv) &&
> GRAPHICS_VER(dev_priv) >= 7)
> +#define HAS_CUR_FBC(dev_priv)(!HAS_GMCH(dev_priv) &&
> DISPLAY_VER(dev_priv) >= 7)
>
> #define HAS_IPS(dev_priv)(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
>
> @@ -1491,7 +1491,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
> #define HAS_PSR_HW_TRACKING(dev_priv) \
> (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
> -#define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12)
> +#define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12)
> #define HAS_TRANSCODER(dev_priv, trans)
> ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
>
> #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
> @@ -1502,7 +1502,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_DMC(dev_priv)(INTEL_INFO(dev_priv)->display.has_dmc)
>
> -#define HAS_MSO(i915)(GRAPHICS_VER(i915) >= 12)
> +#define HAS_MSO(i915)(DISPLAY_VER(i915) >= 12)
>
> #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
> #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
> @@ -1535,7 +1535,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
>
> -#define HAS_LSPCON(dev_priv) (IS_GRAPHICS_VER(dev_priv, 9, 10))
> +#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
>
> /* DPF == dynamic parity feature */
> #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
> @@ -1549,7 +1549,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->display.pipe_mask != 0)
>
> -#define HAS_VRR(i915)(GRAPHICS_VER(i915) >= 11)
> +#define HAS_VRR(i915)(DISPLAY_VER(i915) >= 11)
>
> #define HAS_ASYNC_FLIPS(i915)(DISPLAY_VER(i915) >= 5)
>
> @@ -1579,7 +1579,7 @@ i915_print_iommu_status(struct drm_i915_private *i915,
> struct drm_printer *p);
>
> static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
> *dev_priv)
> {
> - return GRAPHICS_VER(dev_priv) >= 6 && intel_vtd_active(dev_priv);
> + return DISPLAY_VER(dev_priv) >= 6 && intel_vtd_active(dev_priv);
> }
>
> static inline bool
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Fix up request cancel (rev3)
== Series Details == Series: Fix up request cancel (rev3) URL : https://patchwork.freedesktop.org/series/99173/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
