Hi Dave & Daniel,
Here's another drm-intel-next-fixes pull request.
One Cc stable CSC plane index fix, then MST PLL fix and smaller
null/oob/leak fixes.
Regards, Joonas
***
drm-intel-next-fixes-2023-04-20-1:
Active port PLL MST fix for second stream, CSC plane index fix,
null and oob array
On 20.04.2023 01:00, fei.y...@intel.com wrote:
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by Media tile update the whole
cache line even for partial writes. This creates a coherency
problem for cacheable memory if both CPU and GPU are writing data
to
On 20.04.2023 01:00, fei.y...@intel.com wrote:
From: Fei Yang
This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes
On Tue, 2023-04-11 at 22:14 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Some cleanups around mostly PSR/related registers.
>
> v2: Improve the mask bit docs and rebase due to
> intel_psr_regs.h
For the whole set:
Reviewed-by: Jouni Högander
>
> Ville Syrjälä (8):
>
Hi Dave and Daniel,
this is this week's PR for drm-misc-fixes.
Best regards
Thomas
drm-misc-fixes-2023-04-20-2:
Short summary of fixes pull:
* nouveau: fix dma-resv timeout
* rockchip: fix suspend/resume
* sched: fix timeout handling
The following changes since commit
On 19/04/2023 23:10, Dixit, Ashutosh wrote:
On Wed, 19 Apr 2023 06:21:27 -0700, Tvrtko Ursulin wrote:
Hi Tvrtko,
On 10/04/2023 23:35, Ashutosh Dixit wrote:
Instead of erroring out when GuC reset is in progress, block waiting for
GuC reset to complete which is a more reasonable uapi
://download.01.org/0day-ci/archive/20230420/202304201512.cllnzi0u-...@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
ay-dc-link-link_validation.c:warning:variable-link-set-but-not-used
|-- alpha-randconfig-r001-20230420
| |--
drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used
| |--
drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warni
From: Fei Yang
On MTL, LLC is not shared between GT and CPU, set has_llc=0.
Signed-off-by: Fei Yang
Reviewed-by: Andi Shyti
Reviewed-by: Andrzej Hajda
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git
== Series Details ==
Series: drm/i915/mtl: Set has_llc=0
URL : https://patchwork.freedesktop.org/series/116747/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13033 -> Patchwork_116747v1
Summary
---
**SUCCESS**
No
On Tue, 18 Apr 2023, Rodrigo Vivi wrote:
> On Mon, Apr 17, 2023 at 06:37:41PM +0300, Jani Nikula wrote:
>> An error-valued pointer can handle all in one without the wrapper
>> struct.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/display/intel_crt.c | 18
On 4/20/2023 1:21 PM, Tejas Upadhyay wrote:
WA 18018781329 is applicable now across all MTL
steppings.
Cc: Matt Roper
Signed-off-by: Tejas Upadhyay
Acked-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 +---
1 file changed, 13 insertions(+), 7
LGTM.
Reviewed-by: Ankit Nautiyal
On 4/6/2023 7:16 PM, Jani Nikula wrote:
The operator precedence between << and & is wrong, leading to the high
byte being completely ignored. For example, with the 6.4 format, 32
becomes 0 and 24 becomes 8. Fix it, and remove the slightly confusing
and
On 19/04/2023 15:32, Rob Clark wrote:
On Wed, Apr 19, 2023 at 6:16 AM Tvrtko Ursulin
wrote:
On 18/04/2023 18:18, Rob Clark wrote:
On Mon, Apr 17, 2023 at 8:56 AM Tvrtko Ursulin
wrote:
From: Tvrtko Ursulin
For drivers who only wish to show one memory region called 'system,
and only
We have multiple bugs that requires this and it can be picked up
irrespective of this series. I have sent a trybot patch for this and
once that passes, I will push this one.
https://patchwork.freedesktop.org/series/116746/
Nirmoy
On 4/20/2023 1:00 AM, fei.y...@intel.com wrote:
From: Fei
> From: Alex Williamson
> Sent: Wednesday, April 19, 2023 2:39 AM
>
> On Tue, 18 Apr 2023 09:57:32 -0300
> Jason Gunthorpe wrote:
>
> > On Mon, Apr 17, 2023 at 02:06:42PM -0600, Alex Williamson wrote:
> > > On Mon, 17 Apr 2023 16:31:56 -0300
> > > Jason Gunthorpe wrote:
> > >
> > > > On Mon,
On 20/04/2023 11:13, Andrzej Hajda wrote:
On 20.04.2023 01:00, fei.y...@intel.com wrote:
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy
for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far
On Thu, 20 Apr 2023 12:10:20 +
"Liu, Yi L" wrote:
> > From: Alex Williamson
> > Sent: Wednesday, April 19, 2023 2:39 AM
> >
> > On Tue, 18 Apr 2023 09:57:32 -0300
> > Jason Gunthorpe wrote:
> >
> > > On Mon, Apr 17, 2023 at 02:06:42PM -0600, Alex Williamson wrote:
> > > > On Mon, 17
On Wed, 2023-04-19 at 00:29 -0700, Lucas De Marchi wrote:
> On Wed, Apr 19, 2023 at 10:16:22AM +0300, Jani Nikula wrote:
> > On Tue, 18 Apr 2023, Lucas De Marchi wrote:
> > > On Tue, Apr 18, 2023 at 11:30:18PM -0700, Lucas De Marchi wrote:
> > > > On Tue, Apr 18, 2023 at 09:43:37AM -0700, Jose
WA 18018781329 is applicable now across all MTL
steppings.
Cc: Matt Roper
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
Hi Fei,
> To comply with the design that buffer objects shall have immutable
> cache setting through out their life cycle, {set, get}_caching ioctl's
> are no longer supported from MTL onward. With that change caching
> policy can only be set at object creation time. The current code
> applies a
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by Media tile update the whole
cache line even for partial writes. This creates a coherency
problem for cacheable memory if both CPU and GPU are writing data
to different locations within a single cache line.
== Series Details ==
Series: drm/i915/mtl: Add workaround 14018778641
URL : https://patchwork.freedesktop.org/series/116750/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13033 -> Patchwork_116750v1
Summary
---
On Wed, 19 Apr 2023, Ville Syrjälä wrote:
> On Wed, Apr 19, 2023 at 02:54:49PM +0300, Jani Nikula wrote:
>> The declaration was removed earlier, but got accidentally resurrected in
>> i915xx_wm.[ch] refactoring. Remove harder.
>
> i9xx_wm
I was going to fix that while pushing, but got distracted
On Tue, 18 Apr 2023, "Teres Alexis, Alan Previn"
wrote:
> On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
>> From: Alexander Usyskin
>>
>> GSC Proxy component is used for communication between the
>> Intel graphics driver and MEI driver.
>
>
>
>> diff --git
://download.01.org/0day-ci/archive/20230420/202304201909.d57x63j5-...@intel.com/config)
compiler: ia64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
On Wed, Apr 19, 2023 at 06:34:00PM +0300, Jani Nikula wrote:
> On Tue, 18 Apr 2023, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Define and use the bitmasks for the x/y components
> > of the ilk+ panel filter window pos/size registers.
>
> This reduces the field sizes by 3-4 bits. Maybe
On 20/04/2023 12:39, Andi Shyti wrote:
Hi Fei,
To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation
On 19/04/2023 15:38, Rob Clark wrote:
On Wed, Apr 19, 2023 at 7:06 AM Tvrtko Ursulin
wrote:
On 18/04/2023 17:08, Rob Clark wrote:
On Tue, Apr 18, 2023 at 7:58 AM Tvrtko Ursulin
wrote:
On 18/04/2023 15:39, Rob Clark wrote:
On Mon, Apr 17, 2023 at 8:56 AM Tvrtko Ursulin
wrote:
From:
Hi Fei,
On Wed, Apr 19, 2023 at 04:00:50PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> The series includes patches needed to enable MTL.
> Also add new extension for GEM_CREATE uAPI to let
> user space set cache policy for buffer objects.
>
> v2: addressing review comments and
This is a important fix and can be pushed without depending on this series.
I will send this out to mailing list separately for CI.
Regards,
Nirmoy
On 4/20/2023 1:00 AM, fei.y...@intel.com wrote:
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by
Finally, we can enable TC ports for Meteorlake.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index
LGTM.
Reviewed-by: Ankit Nautiyal
On 4/6/2023 7:16 PM, Jani Nikula wrote:
The macro values just don't match the specs. Fix them.
Fixes: 1482ec00be4a ("drm: Add missing DP DSC extended capability definitions.")
Cc: Vinod Govindapillai
Cc: Stanislav Lisovskiy
Signed-off-by: Jani Nikula
---
DP1.4 and DP20 voltage swing sequence for C20 phy.
Bspec: 65449, 67636, 67610
Signed-off-by: Mika Kahola
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++
.../drm/i915/display/intel_ddi_buf_trans.c| 53
Add register writes to enable powering up Type-C subsystem i.e. TCSS.
For MeteorLake we need to request TCSS to power up and check the TCSS
power state after 500 us.
In addition, for PICA we need to set/clear the Type-C PHY ownnership
bit when Type-C device is connected/disconnected.
From: Anusha Srivatsa
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Signed-off-by: Anusha Srivatsa
Signed-off-by: Jose Roberto de Souza
Signed-off-by: Mika
From: Imre Deak
The HPD live status for MTL has to be read from different set of
registers. MTL deserves a new function for this purpose
and cannot reuse the existing HPD live status detection
Signed-off-by: Anusha Srivatsa
Signed-off-by: Imre Deak
Signed-off-by: Mika Kahola
---
As we already do with C10 chip, let's dump the pll
hw state for C20 as well.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
3 files
Readout hw state for Thunderbolt.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
3 files changed, 32 insertions(+), 2
From: Gustavo Sousa
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
BSpec: 50064
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/i915_irq.c | 5 -
1 file changed, 4
Enabling and disabling sequence for Thunderbolt PLL.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 135 ++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 7 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
3 files changed, 138
Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
On 20.04.2023 01:00, fei.y...@intel.com wrote:
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. In
Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
The PLL settings are based on table, not for algorithmic alternative.
For DP 1.4 only MPLLB is in use.
Once register settings are done, we read back C20 HW state.
BSpec: 64568
Signed-off-by: Mika Kahola
Signed-off-by: Arun R Murthy
Calculate port clock with C20 phy.
BSpec: 64568
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 45 +++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++
Add support for C20 phy for Type-C connections. C20 phy differs from
C10 and hence we need to separately handle this case.
Signed-off-by: Mika Kahola
Anusha Srivatsa (1):
drm/i915/mtl: Pin assignment for TypeC
Gustavo Sousa (1):
drm/i915/mtl: Define mask for DDI AUX interrupts
Imre Deak
C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
4 lane support for c20.
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
Signed-off-by: Bhanuprakash Modem
Signed-off-by: Imre Deak
Instead of erroring out when GuC reset is in progress, block waiting for
GuC reset to complete which is a more reasonable uapi behavior.
v2: Avoid race between wake_up_all and waiting for wakeup (Rodrigo)
v3: Remove timeout when blocked (Tvrtko)
Signed-off-by: Ashutosh Dixit
Reviewed-by:
On dGfx, the PL1 power limit being enabled and set to a low value results
in a low GPU operating freq. It also negates the freq raise operation which
is done before GuC firmware load. As a result GuC firmware load can time
out. Such timeouts were seen in the GL #8062 bug below (where the PL1 power
== Series Details ==
Series: drm/i915/mtl: workaround coherency issue for Media
URL : https://patchwork.freedesktop.org/series/116751/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13034 -> Patchwork_116751v1
Summary
On Thu, Apr 20, 2023 at 09:19:09AM -0400, Souza, Jose wrote:
> On Wed, 2023-04-19 at 00:29 -0700, Lucas De Marchi wrote:
> > On Wed, Apr 19, 2023 at 10:16:22AM +0300, Jani Nikula wrote:
> > > On Tue, 18 Apr 2023, Lucas De Marchi wrote:
> > > > On Tue, Apr 18, 2023 at 11:30:18PM -0700, Lucas De
On Fri, 2023-03-17 at 17:58 -0700, Radhakrishna Sripada wrote:
> Communicating QGV points restriction to PUnit happens via PM Demand
> instead of the Pcode mailbox in the previous platforms. GV point
> restriction is handled by the PM demand code.
>
> Signed-off-by: Radhakrishna Sripada
> ---
On Thu, Apr 20, 2023 at 08:57:24AM +0100, Tvrtko Ursulin wrote:
>
> On 19/04/2023 23:10, Dixit, Ashutosh wrote:
> > On Wed, 19 Apr 2023 06:21:27 -0700, Tvrtko Ursulin wrote:
> > >
> >
> > Hi Tvrtko,
> >
> > > On 10/04/2023 23:35, Ashutosh Dixit wrote:
> > > > Instead of erroring out when GuC
== Series Details ==
Series: drm/i915/mtl: Set has_llc=0
URL : https://patchwork.freedesktop.org/series/116747/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13033_full -> Patchwork_116747v1_full
Summary
---
== Series Details ==
Series: drm/i915/mtl: Add workaround 14018778641
URL : https://patchwork.freedesktop.org/series/116750/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13033_full -> Patchwork_116750v1_full
Summary
== Series Details ==
Series: drm/i915: Initialize dkl_phy spin lock from display code path (rev4)
URL : https://patchwork.freedesktop.org/series/116325/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13034 -> Patchwork_116325v4
== Series Details ==
Series: drm/i915/guc: Disable PL1 power limit when loading GuC firmware
URL : https://patchwork.freedesktop.org/series/116768/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
drm/i915: Initialize dkl_phy spin lock from display code path
Start moving the initialization of display locks from
i915_driver_early_probe().
Display locks should be initialized from display-only code paths.
It was also agreed that if a variable is only used in one file, it
should be
On Thu, 2023-04-20 at 09:35 -0700, Lucas De Marchi wrote:
> On Thu, Apr 20, 2023 at 08:36:37AM -0700, Jose Souza wrote:
> > On Thu, 2023-04-20 at 11:27 -0400, Rodrigo Vivi wrote:
> > > On Thu, Apr 20, 2023 at 09:19:09AM -0400, Souza, Jose wrote:
> > > > On Wed, 2023-04-19 at 00:29 -0700, Lucas De
> On 20/04/2023 12:39, Andi Shyti wrote:
>> Hi Fei,
>>
>>> To comply with the design that buffer objects shall have immutable
>>> cache setting through out their life cycle, {set, get}_caching ioctl's
>>> are no longer supported from MTL onward. With that change caching
>>> policy can only be set
v6: Update Patch 3 to remove the timeout when blocked
v1-v5: Please see individual patches for revision history
Ashutosh Dixit (3):
drm/i915/hwmon: Get mutex and rpm ref just once in hwm_power_max_write
drm/i915/guc: Disable PL1 power limit when loading GuC firmware
drm/i915/hwmon: Block
In preparation for follow-on patches, refactor hwm_power_max_write to take
hwmon_lock and runtime pm wakeref at start of the function and release them
at the end, therefore acquiring these just once each.
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
== Series Details ==
Series: drm/i915/mtl: Add support for C20 phy
URL : https://patchwork.freedesktop.org/series/116755/
State : warning
== Summary ==
Error: dim checkpatch failed
46e88ddde94d drm/i915/mtl: C20 PLL programming
-:155: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
== Series Details ==
Series: drm/i915/mtl: Add support for C20 phy
URL : https://patchwork.freedesktop.org/series/116755/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Thu, 2023-04-20 at 11:27 -0400, Rodrigo Vivi wrote:
> On Thu, Apr 20, 2023 at 09:19:09AM -0400, Souza, Jose wrote:
> > On Wed, 2023-04-19 at 00:29 -0700, Lucas De Marchi wrote:
> > > On Wed, Apr 19, 2023 at 10:16:22AM +0300, Jani Nikula wrote:
> > > > On Tue, 18 Apr 2023, Lucas De Marchi
On Wed, Apr 19, 2023 at 03:13:08PM -0700, Dixit, Ashutosh wrote:
> On Wed, 19 Apr 2023 12:40:44 -0700, Rodrigo Vivi wrote:
> >
>
> Hi Rodrigo,
>
> > On Tue, Apr 18, 2023 at 10:23:50AM -0700, Dixit, Ashutosh wrote:
> > > On Mon, 17 Apr 2023 22:35:58 -0700, Rodrigo Vivi wrote:
> > > >
> > >
> > >
On Thu, Apr 20, 2023 at 08:36:37AM -0700, Jose Souza wrote:
On Thu, 2023-04-20 at 11:27 -0400, Rodrigo Vivi wrote:
On Thu, Apr 20, 2023 at 09:19:09AM -0400, Souza, Jose wrote:
> On Wed, 2023-04-19 at 00:29 -0700, Lucas De Marchi wrote:
> > On Wed, Apr 19, 2023 at 10:16:22AM +0300, Jani Nikula
== Series Details ==
Series: drm/i915/guc: Disable PL1 power limit when loading GuC firmware
URL : https://patchwork.freedesktop.org/series/116768/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13034 -> Patchwork_116768v1
== Series Details ==
Series: drm/i915/mtl: Add support for C20 phy
URL : https://patchwork.freedesktop.org/series/116755/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13034 -> Patchwork_116755v1
Summary
---
On Thu, 20 Apr 2023 08:43:52 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Thu, Apr 20, 2023 at 08:57:24AM +0100, Tvrtko Ursulin wrote:
> >
> > On 19/04/2023 23:10, Dixit, Ashutosh wrote:
> > > On Wed, 19 Apr 2023 06:21:27 -0700, Tvrtko Ursulin wrote:
> > > >
> > >
> > > Hi Tvrtko,
> > >
> > > >
Hi Fei,
> >>> To comply with the design that buffer objects shall have immutable
> >>> cache setting through out their life cycle, {set, get}_caching ioctl's
> >>> are no longer supported from MTL onward. With that change caching
> >>> policy can only be set at object creation time. The current
On Wed, Apr 19, 2023 at 04:00:54PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> This patch implements Wa_22016122933.
>
> In MTL, memory writes initiated by Media tile update the whole
> cache line even for partial writes. This creates a coherency
> problem for cacheable memory if both
On Thu, Apr 20, 2023 at 11:13:52PM +0200, Andi Shyti wrote:
> From: Madhumitha Tolakanahalli Pradeep
>
>
> On MTL, GT can no longer allocate on LLC - only the CPU can.
> This, along with addition of support for L4 cache calls for
> a MOCS/PAT table update.
> Also the PAT index registers are
On 4/17/2023 10:56 AM, Teres Alexis, Alan Previn wrote:
On Mon, 2023-04-10 at 09:10 -0700, Ceraolo Spurio, Daniele wrote:
alan:snip
+int
+intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc,
+struct intel_context *ce,
+
i guess we are settled with this patch...
On Thu, 2023-04-20 at 15:04 -0700, Ceraolo Spurio, Daniele wrote:
> On 4/18/2023 11:57 PM, Teres Alexis, Alan Previn wrote:
> > On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
> > > From: Alexander Usyskin
> > >
> > > Add GSC proxy
On Thu, Mar 16, 2023 at 01:25:48PM -0700, Radhakrishna Sripada wrote:
From: Vinay Belgaumkar
If BIOS enables/disables C6, i915 should do the same. Also, retain
this value across driver reloads. This is needed only for MTL as
of now due to an existing bug in OA which needs C6 disabled for
it to
== Series Details ==
Series: series starting with [1/2] drm/i915/mtl: Add the missing CPU transcoder
mask in intel_device_info
URL : https://patchwork.freedesktop.org/series/116781/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13035 -> Patchwork_116781v1
I think we are also bottom-ing on the opens fo this patch too:
On Thu, 2023-04-20 at 13:21 -0700, Ceraolo Spurio, Daniele wrote:
> On 4/20/2023 11:49 AM, Teres Alexis, Alan Previn wrote:
> > On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
> > > The GSC notifies us of a proxy
== Series Details ==
Series: drm/i915/mtl: workaround coherency issue for Media (rev2)
URL : https://patchwork.freedesktop.org/series/116751/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13035 -> Patchwork_116751v2
== Series Details ==
Series: drm/i915/mtl: Define MOCS and PAT tables for MTL (rev9)
URL : https://patchwork.freedesktop.org/series/115980/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13035 -> Patchwork_115980v9
Summary
On Fri, Mar 31, 2023 at 02:02:40PM +0100, Tvrtko Ursulin wrote:
On 30/03/2023 19:31, Umesh Nerlige Ramappa wrote:
+ Joonas for comments on this
On Thu, Mar 30, 2023 at 02:38:03PM +0100, Tvrtko Ursulin wrote:
On 30/03/2023 01:41, Umesh Nerlige Ramappa wrote:
MTL introduces separate GTs for
On 4/20/2023 11:49 AM, Teres Alexis, Alan Previn wrote:
On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
The GSC notifies us of a proxy request via the HECI2 interrupt. The
alan:snip
@@ -256,6 +262,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
u32 irqs =
On Wed, Apr 19, 2023 at 04:00:52PM -0700, fei.y...@intel.com wrote:
> From: Madhumitha Tolakanahalli Pradeep
>
>
> On MTL, GT can no longer allocate on LLC - only the CPU can.
> This, along with addition of support for L4 cache calls for
> a MOCS/PAT table update.
> Also the PAT index registers
On Wed, Apr 19, 2023 at 04:00:55PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> The design is to keep Buffer Object's caching policy immutable through
> out its life cycle. This patch ends the support for set caching ioctl
> from MTL onward. While doing that we also set BO's to be 1-way
On Thu, Apr 20, 2023 at 02:23:22PM -0700, Matt Roper wrote:
> On Thu, Apr 20, 2023 at 11:13:52PM +0200, Andi Shyti wrote:
> > From: Madhumitha Tolakanahalli Pradeep
> >
> >
> > On MTL, GT can no longer allocate on LLC - only the CPU can.
> > This, along with addition of support for L4 cache
From: Stanislav Lisovskiy
We try to verify pll registers in sw state for slave crtc with the hw state.
However in case of bigjoiner we don't calculate those at all, so this
verification
will then always fail.
So we should either skip the verification for Bigjoiner slave crtc or copy sw
state
CPU transcoder mask is used to iterate over the available
CPU transcoders in the macro for_each_cpu_transcoder().
The macro is broken on MTL and got highlighted when audio
state was being tracked for each transcoder added in [1].
Add the missing CPU transcoder mask which is similar to ADL-P
mask
On Thu, Apr 20, 2023 at 01:05:27PM -0700, Umesh Nerlige Ramappa wrote:
> On Thu, Mar 16, 2023 at 01:25:48PM -0700, Radhakrishna Sripada wrote:
> > From: Vinay Belgaumkar
> >
> > If BIOS enables/disables C6, i915 should do the same. Also, retain
> > this value across driver reloads. This is
On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
> The GSC notifies us of a proxy request via the HECI2 interrupt. The
alan:snip
> @@ -256,6 +262,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
> u32 irqs = GT_RENDER_USER_INTERRUPT;
> u32 guc_mask =
On Wed, Apr 19, 2023 at 04:00:53PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> PTE encode functions are platform dependent. This patch implements
> PTE functions for MTL, and ensures the correct PTE encode function
> is used by calling pte_encode function pointer instead of the
>
== Series Details ==
Series: drm/i915/mtl: workaround coherency issue for Media
URL : https://patchwork.freedesktop.org/series/116751/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13034_full -> Patchwork_116751v1_full
On Wed, Apr 19, 2023 at 04:00:56PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> This patch is a preparation for replacing enum i915_cache_level with PAT
> index. Caching policy for buffer objects is set through the PAT index in
> PTE, the old i915_cache_level is not sufficient to
From: Madhumitha Tolakanahalli Pradeep
On MTL, GT can no longer allocate on LLC - only the CPU can.
This, along with addition of support for L4 cache calls for
a MOCS/PAT table update.
Also the PAT index registers are multicasted for primary GT,
and there is an address jump from index 7 to 8.
== Series Details ==
Series: drm/i915/mtl: Add support for C20 phy
URL : https://patchwork.freedesktop.org/series/116755/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13034_full -> Patchwork_116755v1_full
Summary
---
== Series Details ==
Series: drm/i915/mtl: Define MOCS and PAT tables for MTL (rev9)
URL : https://patchwork.freedesktop.org/series/115980/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Thu, Apr 20, 2023 at 04:51:23PM +0530, Tejas Upadhyay wrote:
> WA 18018781329 is applicable now across all MTL
> steppings.
>
> Cc: Matt Roper
> Signed-off-by: Tejas Upadhyay
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 +---
> 1 file changed, 13 insertions(+), 7
== Series Details ==
Series: drm/i915/guc: Disable PL1 power limit when loading GuC firmware
URL : https://patchwork.freedesktop.org/series/116768/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13034_full -> Patchwork_116768v1_full
On Thu, Apr 20, 2023 at 01:38:59PM +0200, Nirmoy Das wrote:
> From: Fei Yang
>
> This patch implements Wa_22016122933.
>
> In MTL, memory writes initiated by Media tile update the whole
> cache line even for partial writes. This creates a coherency
> problem for cacheable memory if both CPU and
On 4/18/2023 11:57 PM, Teres Alexis, Alan Previn wrote:
On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
From: Alexander Usyskin
Add GSC proxy driver. It to allows messaging between GSC component
on Intel on board graphics card and CSE device.
alan:nit: isn't "Intel
== Series Details ==
Series: series starting with [1/2] drm/i915/mtl: Add the missing CPU transcoder
mask in intel_device_info
URL : https://patchwork.freedesktop.org/series/116781/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit
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