== Series Details ==
Series: Fix modeset locking issue in HDCP MST
URL : https://patchwork.freedesktop.org/series/117615/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13131 -> Patchwork_117615v1
Summary
---
== Series Details ==
Series: Fix modeset locking issue in HDCP MST
URL : https://patchwork.freedesktop.org/series/117615/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13131_full -> Patchwork_117615v1_full
Summary
---
Add a work queue in the intel_wakeref structure to be used exclusively
by the wake reference mechanism. This is needed in order to avoid
using the system workqueue and relying on flush_scheduled_work().
Cc: Tetsuo Handa
Cc: Tvrtko Ursulin
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Luca
Instead of using a global workqueue for the SW fence selftest,
allocate a separate one temporarily only while running the test.
Cc: Tetsuo Handa
Cc: Tvrtko Ursulin
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Luca Coelho
---
drivers/gpu/drm/i915/selftests/i915_sw_fence.c | 16
In order to avoid flush_scheduled_work() usage, add a dedicated
workqueue in the drm_i915_private structure. In this way, we don't
need to use the system queue anymore.
This change is mostly mechanical and based on Tetsuo's original
patch[1].
Link:
Hi,
This series implements internal workqueues in the i915 driver in order
to avoid using the system queue. We add one generic workqueue in the
drm_i915_private structure, one specific for wake references and one
in a self-test.
This is based on Tetsuo's work[1] and is required to get rid of
Hi,
Here's the first drm-misc-next PR for 6.5
Please note that I'll be off for about a month starting next week, and
Thomas has kindly agreed to fill in.
Thanks!
Maxime
drm-misc-next-2023-05-11:
drm-misc-next for 6.5:
UAPI Changes:
Cross-subsystem Changes:
- arch: Consolidate
Core
On Wed, 2023-04-26 at 16:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> To avoid annoying spec lookups let's define more PS_CTRL
> bits in the header.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h | 11 +++
> 1 file changed, 11 insertions(+)
>
>
A friendly ping to merge this PR. The patches appear to be missing from
drm-fixes.
Am 26.04.23 um 07:59 schrieb Maarten Lankhorst:
Hi Dave, Daniel,
drm-misc-fixes pull request for rc1. drm-misc-next-fixes coming up.. next
~Maarten
drm-misc-fixes-2023-04-26:
drm-misc-fixes for v6.4-rc1:
-
On 4/26/23 17:03, Yi Liu wrote:
This defines KVM_DEV_VFIO_FILE* and make alias with KVM_DEV_VFIO_GROUP*.
Old userspace uses KVM_DEV_VFIO_GROUP* works as well.
Reviewed-by: Jason Gunthorpe
Reviewed-by: Kevin Tian
Tested-by: Terrence Xu
Tested-by: Nicolin Chen
Tested-by: Matthew Rosato
On 10.5.2023 16.15, Jani Nikula wrote:
On Tue, 09 May 2023, Juha-Pekka Heikkila wrote:
Add Tile4 type ccs modifiers with aux buffer needed for MTL
Please send this Cc: dri-devel too.
Sure, I'll resend shortly. Here I just didn't want to spam dri-devel
since from original set this patch is
On Thu, 11 May 2023, Suraj Kandpal wrote:
> Pass all the parameter in intel_encoder->enable()
> to intel_hdcp_enable as we need intel_atomic_state
> later down to get acquire_ctx.
You're passing connector, not encoder, though.
BR,
Jani.
>
> Cc: Jani Nikula
> Cc: Ankit Nautiyal
>
== Series Details ==
Series: series starting with [1/2] drm/i915/mtl: Extend Wa_16014892111 to MTL
URL : https://patchwork.freedesktop.org/series/117607/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13131_full -> Patchwork_117607v1_full
CHV_FUSE_GT (0x182168) is purely about GT fuses, therefore belongs in
intel_gt_regs.h, is in the gcfgmmio unit, but is technically in the VLV
display base area.
Use the 0x182168 MMIO address directly to drop dependency on
VLV_DISPLAY_BASE and thus display/intel_display_reg_defs.h in
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, May 11, 2023 1:27 PM
> To: Kandpal, Suraj ; intel-
> g...@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ; Kandpal, Suraj
>
> Subject: Re: [PATCH 1/2] drm/i915/hdcp: add intel_atomic_state argument to
> hdcp_enable function
>
Pass all the parameter in intel_encoder->enable()
to intel_hdcp_enable as we need intel_atomic_state
later down to get acquire_ctx.
Cc: Jani Nikula
Cc: Ankit Nautiyal
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_ddi.c| 4 +---
Since topology state is being added to drm_atomic_state now all
drm_modeset_lock required are being taken from core this raises
an issue when we try to loop over connector and assign vcpi id to
our streams as we did not have atomic state to derive acquire_ctx
from hence we fill in stream info if
On Tue, 20 Dec 2022, Imre Deak wrote:
> On Tue, Dec 20, 2022 at 02:40:47PM +0200, Jani Nikula wrote:
>> On Tue, 20 Dec 2022, Maarten Lankhorst
>> wrote:
>> > We enable the DP aux channel during probe, but may free the connector
>> > soon afterwards. Ensure the DP aux display power put is
On 10/05/2023 19:46, Tejun Heo wrote:
Hello,
On Wed, May 10, 2023 at 04:59:01PM +0200, Maarten Lankhorst wrote:
The misc controller is not granular enough. A single computer may have any
number of
graphics cards, some of them with multiple regions of vram inside a single card.
Extending
On Tue, 10 Jan 2023, Rodrigo Vivi wrote:
> On Tue, Jan 10, 2023 at 11:59:02AM +0100, Maarten Lankhorst wrote:
>> enum i915_drm_suspend_mode suspend_mode is only used in
>> intel_display_power, while we only care about whether we perform a
>> s2idle. Remove it and use a simple bool.
>>
>>
Hey,
On 2023-05-10 20:46, Tejun Heo wrote:
> Hello,
>
> On Wed, May 10, 2023 at 04:59:01PM +0200, Maarten Lankhorst wrote:
>> The misc controller is not granular enough. A single computer may have any
>> number of
>> graphics cards, some of them with multiple regions of vram inside a single
>>
Add Tile4 ccs modifiers w/ auxbuffer handling
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_fb.c | 42 ++-
.../drm/i915/display/skl_universal_plane.c| 22 +-
2 files changed, 61 insertions(+), 3 deletions(-)
Add Tile4 type ccs modifiers with aux buffer needed for MTL
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Signed-off-by: Juha-Pekka Heikkila
---
include/uapi/drm/drm_fourcc.h | 43 +++
1 file changed, 43 insertions(+)
diff --git
== Series Details ==
Series: Fix modeset locking issue in HDCP MST (rev2)
URL : https://patchwork.freedesktop.org/series/117615/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13133 -> Patchwork_117615v2
Summary
---
On Thu, 11 May 2023, Ville Syrjälä wrote:
> On Thu, May 11, 2023 at 12:04:27PM +0300, Jani Nikula wrote:
>> CHV_FUSE_GT (0x182168) is purely about GT fuses, therefore belongs in
>> intel_gt_regs.h, is in the gcfgmmio unit, but is technically in the VLV
>> display base area.
>>
>> Use the
== Series Details ==
Series: series starting with [1/2] drm/fourcc: define Intel Meteorlake related
ccs modifiers
URL : https://patchwork.freedesktop.org/series/117625/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13134 -> Patchwork_117625v1
== Series Details ==
Series: Fix modeset locking issue in HDCP MST (rev2)
URL : https://patchwork.freedesktop.org/series/117615/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Thu, May 11, 2023 at 10:29:01AM +0300, Luca Coelho wrote:
> On Wed, 2023-04-26 at 16:50 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > To avoid annoying spec lookups let's define more PS_CTRL
> > bits in the header.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> >
On Thu, May 11, 2023 at 03:31:16PM +0300, Jani Nikula wrote:
> On Thu, 11 May 2023, Ville Syrjälä wrote:
> > On Thu, May 11, 2023 at 12:04:27PM +0300, Jani Nikula wrote:
> >> CHV_FUSE_GT (0x182168) is purely about GT fuses, therefore belongs in
> >> intel_gt_regs.h, is in the gcfgmmio unit, but
On Thu, 11 May 2023, Ville Syrjälä wrote:
> On Thu, May 11, 2023 at 03:31:16PM +0300, Jani Nikula wrote:
>> On Thu, 11 May 2023, Ville Syrjälä wrote:
>> > On Thu, May 11, 2023 at 12:04:27PM +0300, Jani Nikula wrote:
>> >> CHV_FUSE_GT (0x182168) is purely about GT fuses, therefore belongs in
>>
> -Original Message-
> From: Nikula, Jani
> Sent: Thursday, May 11, 2023 2:26 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Teres Alexis, Alan Previn
> ; Kandpal, Suraj
> ; Shankar, Uma
> Subject: [PATCH] drm/i915/hdcp: drop display/ prefix from include
>
> The
On Thu, May 11, 2023 at 12:04:27PM +0300, Jani Nikula wrote:
> CHV_FUSE_GT (0x182168) is purely about GT fuses, therefore belongs in
> intel_gt_regs.h, is in the gcfgmmio unit, but is technically in the VLV
> display base area.
>
> Use the 0x182168 MMIO address directly to drop dependency on
>
Hi Dave & Daniel,
Here goes drm-intel-fixes for v6.4-rc2.
Important fix to taint kernel when force_probe is used, two display
fixes (null deref/div-by-zero) and a GuC error capture register list
correction.
Regards, Joonas
PS. Again had to remove one commit with incorrect Fixes: tag so check
On Thu, 2023-05-11 at 14:54 +0300, Ville Syrjälä wrote:
> On Thu, May 11, 2023 at 10:29:01AM +0300, Luca Coelho wrote:
> > On Wed, 2023-04-26 at 16:50 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > To avoid annoying spec lookups let's define more PS_CTRL
> > > bits in the
== Series Details ==
Series: drm/i915: implement internal workqueues
URL : https://patchwork.freedesktop.org/series/117618/
State : warning
== Summary ==
Error: dim checkpatch failed
501007ed8e45 drm/i915: add a dedicated workqueue inside drm_i915_private
-:622: CHECK:COMPARISON_TO_NULL:
== Series Details ==
Series: drm/i915: implement internal workqueues
URL : https://patchwork.freedesktop.org/series/117618/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On 5/11/2023 11:27 AM, Suraj Kandpal wrote:
Since topology state is being added to drm_atomic_state now all
drm_modeset_lock required are being taken from core this raises
an issue when we try to loop over connector and assign vcpi id to
our streams as we did not have atomic state to derive
HDCP MST scenario sees modeset locking issue ever since
topology_state was added to drm_atomic_state and all modeset
locks were being taken for us causing a locking issue to occur
when we iterate over connectors to assign vcpi id, the fix
being to pass acquire_ctx to drm_modeset_lock
--v2
-call
== Series Details ==
Series: drm/i915: implement internal workqueues
URL : https://patchwork.freedesktop.org/series/117618/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13132 -> Patchwork_117618v1
Summary
---
Hi Dave, Daniel,
Next pull request, with the previous one included too:
drm-misc-fixes-2023-05-11:
drm-misc-fixes for v6.4-rc2:
- More DSC macro fixes.
- Small mipi-dsi fix.
- Scheduler timeout handling fix.
---
drm-misc-fixes for v6.4-rc1:
- Fix DSC macros.
- Fix VESA format for simplefb.
-
== Series Details ==
Series: drm/i915/gt: drop dependency on VLV_DISPLAY_BASE
URL : https://patchwork.freedesktop.org/series/117620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13133 -> Patchwork_117620v1
Summary
---
On 09/05/2023 18:12, Yang, Fei wrote:
> On 09/05/2023 00:48, fei.y...@intel.com wrote:
>> From: Fei Yang
>>
>> Currently the KMD is using enum i915_cache_level to set caching
policy for
>> buffer objects. This is flaky because the PAT index which really
controls
>> the caching
== Series Details ==
Series: drm/i915/hdcp: drop display/ prefix from include
URL : https://patchwork.freedesktop.org/series/117619/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13133_full -> Patchwork_117619v1_full
== Series Details ==
Series: series starting with [1/2] drm/fourcc: define Intel Meteorlake related
ccs modifiers
URL : https://patchwork.freedesktop.org/series/117625/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
== Series Details ==
Series: series starting with [1/2] drm/fourcc: define Intel Meteorlake related
ccs modifiers
URL : https://patchwork.freedesktop.org/series/117625/
State : warning
== Summary ==
Error: dim checkpatch failed
1e7c30956aac drm/fourcc: define Intel Meteorlake related ccs
The display prefix is unnecessary within the display sub-directory.
Cc: Alan Previn
Cc: Suraj Kandpal
Cc: Uma Shankar
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
== Series Details ==
Series: drm/i915/hdcp: drop display/ prefix from include
URL : https://patchwork.freedesktop.org/series/117619/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13133 -> Patchwork_117619v1
Summary
---
== Series Details ==
Series: drm/i915: implement internal workqueues
URL : https://patchwork.freedesktop.org/series/117618/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13132_full -> Patchwork_117618v1_full
Summary
On Thu, May 11, 2023 at 06:21:53PM +0300, Jani Nikula wrote:
> CHV_FUSE_GT (0x182168) is purely about GT fuses, therefore belongs in
> intel_gt_regs.h, is in the gcfgmmio unit, but is technically in the VLV
> display base area.
>
> Add VLV_GUNIT_BASE to drop dependency on VLV_DISPLAY_BASE and
On Fri, 05 May 2023 17:58:16 -0700, Umesh Nerlige Ramappa wrote:
>
One drive-by comment:
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index 12b2f3169abf..284e5c5b97bb 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@
On Wed, May 10, 2023 at 01:31:31PM +0300, Imre Deak wrote:
> If the output on a DP-alt link with its sink disconnected is kept
> enabled for too long (about 20 sec), then some IOM/TCSS firmware timeout
> will cause havoc on the PCI bus, at least for other GFX devices on it
> which will stop
On Thu, May 11, 2023 at 01:37:13PM +0300, Juha-Pekka Heikkila wrote:
> Add Tile4 type ccs modifiers with aux buffer needed for MTL
>
Bspec: 49251, 49252, 49253
> Cc: dri-de...@lists.freedesktop.org
> Cc: Jani Nikula
Reviewed-by: Matt Atwood
> Signed-off-by: Juha-Pekka Heikkila
> ---
>
== Series Details ==
Series: drm/i915: Init DDI ports based on port_mask
URL : https://patchwork.freedesktop.org/series/117641/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13138 -> Patchwork_117641v1
Summary
---
On Thu, May 11, 2023 at 01:37:14PM +0300, Juha-Pekka Heikkila wrote:
> Add Tile4 ccs modifiers w/ auxbuffer handling
Commit message should include the workarounds implemented
Wa_14017240301.
>
Bspec: 49251, 49252, 49253
with white space revisions, and commit message update:
Reviewed-by: Matt
== Series Details ==
Series: drm/i915/gt: drop dependency on VLV_DISPLAY_BASE (rev2)
URL : https://patchwork.freedesktop.org/series/117620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13138 -> Patchwork_117620v2
Summary
== Series Details ==
Series: drm/i915: Init DDI ports based on port_mask
URL : https://patchwork.freedesktop.org/series/117641/
State : warning
== Summary ==
Error: dim checkpatch failed
7fa5a06bde61 drm/i915: Remove bogus DDI-F from hsw/bdw output init
6ce69347aa4f drm/i915: Introduce device
== Series Details ==
Series: drm/i915: Init DDI ports based on port_mask
URL : https://patchwork.freedesktop.org/series/117641/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Hey,
On 2023-05-11 12:14, Tvrtko Ursulin wrote:
>
> On 10/05/2023 19:46, Tejun Heo wrote:
>> Hello,
>>
>> On Wed, May 10, 2023 at 04:59:01PM +0200, Maarten Lankhorst wrote:
>>> The misc controller is not granular enough. A single computer may have any
>>> number of
>>> graphics cards, some of
On Thu, May 11, 2023 at 03:46:14PM +0300, Jani Nikula wrote:
> On Thu, 11 May 2023, Ville Syrjälä wrote:
> > On Thu, May 11, 2023 at 03:31:16PM +0300, Jani Nikula wrote:
> >> On Thu, 11 May 2023, Ville Syrjälä wrote:
> >> > On Thu, May 11, 2023 at 12:04:27PM +0300, Jani Nikula wrote:
> >> >>
From: Ville Syrjälä
Declare the available DVO/SDVO/HDMI/DP/DDI ports in the
device info. The other outputs (LVDS/TV/DSI/VGA) are left
out since for most of them we don't consider them as "ports".
DSI we should probably perhaps include somehow in the device
info. Just not sure how. Or we just
From: Ville Syrjälä
Sprinkle in some BUILD_BUG_ON()s to make sure some of
the bitmasks used in the device info have enough bits.
Do we have a better place for this sort of stuff?
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_device_info.c | 4
1 file changed, 4
From: Ville Syrjälä
HSW/BDW don't have DDI-F so don't go looking for one.
Seems to have been accidentally left behind when the
skl+ stuff got split out in commit 097d9e902068
("drm/i915/display: remove strap checks from gen 9").
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Sprinkle some asserts to catch any mishaps in the port_mask
vs. output init.
For DDI/DP/HDMI/SDVO I decided that we want to bail out for
an invalid port since those are the encoder types where
we might want consider driving the whole thing from the VBT
child device list, and
From: Ville Syrjälä
The SDVO code already warns when the port in question doesn't
actually support SDVO. Let's make that also bail the encoder
registration like the generic assert_port_valid() we added.
And add a similar thing for g4x HDMI, mainly because on g4x
itsefl port D only supports DP
From: Ville Syrjälä
Instead of listing every platform's possible DDI outputs
in intel_setup_outputs() just loop over the new port_mask
to achieve the same thing.
HSW/BDW were left as is since they still look at the straps
as well.
DSI is still a mess. For now just check for the relevant
From: Ville Syrjälä
Make HSW/BDW use port_mask for output probing as well.
To achieve that the strap checks are moved into
intel_ddi_init() itself. Or should we move them to the
runtime port_mask init instead? Maybe not since the hardware
is still there, just not connected to anything.
From: Ville Syrjälä
Introduce port_mask into the device info and utilize it
it initalize DDI ports instead of hand rolling each
intel_ddi_init() call per platform+port.
This is an intermediate step towards initializing
DDI/DP/HDMI/DSI ports purely based on VBT information.
Ville Syrjälä (7):
On Wed, May 10, 2023 at 05:10:22PM +0300, Imre Deak wrote:
> On Wed, May 10, 2023 at 05:03:17PM +0300, Ville Syrjälä wrote:
> > On Wed, May 10, 2023 at 01:31:30PM +0300, Imre Deak wrote:
> > > Call the TypeC port flush_work and cleanup handlers without the modeset
> > > locks held. These don't
On Thu, 11 May 2023, "Kandpal, Suraj" wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Thursday, May 11, 2023 2:26 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani ; Teres Alexis, Alan Previn
>> ; Kandpal, Suraj
>> ; Shankar, Uma
>> Subject: [PATCH]
CHV_FUSE_GT (0x182168) is purely about GT fuses, therefore belongs in
intel_gt_regs.h, is in the gcfgmmio unit, but is technically in the VLV
display base area.
Add VLV_GUNIT_BASE to drop dependency on VLV_DISPLAY_BASE and thus
display/intel_display_reg_defs.h in intel_gt_regs.h.
v2: Add
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: aabe491169befbe5481144acf575a0260939764a Add linux-next specific
files for 20230511
Warning reports:
https://lore.kernel.org/oe-kbuild-all/202304140707.coh337ux-...@intel.com
Warning
Quoting Radhakrishna Sripada (2023-05-10 19:35:51)
>The dg2 workaround which is used for performance tuning
>is needed for Meteorlake.
>
>Bspec: 68331
>Cc: Matt Roper
>Cc: Gustavo Sousa
>Signed-off-by: Radhakrishna Sripada
The workaround for MTL seems to be necessary only prior to B0
Quoting Radhakrishna Sripada (2023-05-10 19:35:52)
>MTL reuses the tuning parameters for DG2. Extend the dg2
>performance tuning parameters to MTL.
>
>Bspec: 68331
>Cc: Matt Roper
>Cc: Gustavo Sousa
>Signed-off-by: Radhakrishna Sripada
Commit cebc13de7e70 ("drm/i915: Whitelist
Hi Fei,
Pushed to drm-intel-gt-next.
There was a "pinky" promise that Tvrtko asked you (and I feel
involved, as well) to make. Let's make sure to follow up on that.
Andi
On Tue, May 09, 2023 at 09:51:58AM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> This patch set was posted at
>
== Series Details ==
Series: series starting with [1/2] drm/fourcc: define Intel Meteorlake related
ccs modifiers
URL : https://patchwork.freedesktop.org/series/117625/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13134_full -> Patchwork_117625v1_full
On Wed, 10 May 2023 11:36:06 -0700, Ashutosh Dixit wrote:
>
> Loading i915 on UBSAN enabled kernels (CONFIG_UBSAN/CONFIG_UBSAN_BOOL)
> causes the following warning:
>
> UBSAN: invalid-load in drivers/gpu/drm/i915/gt/uc/intel_uc.c:558:2
> load of value 255 is not a valid value for type '_Bool'
== Series Details ==
Series: drm/i915/gt: drop dependency on VLV_DISPLAY_BASE
URL : https://patchwork.freedesktop.org/series/117620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13133_full -> Patchwork_117620v1_full
== Series Details ==
Series: Fix modeset locking issue in HDCP MST (rev2)
URL : https://patchwork.freedesktop.org/series/117615/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13133_full -> Patchwork_117615v2_full
Summary
== Series Details ==
Series: drm/i915/gt: Add workaround 14016712196
URL : https://patchwork.freedesktop.org/series/117661/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
DESCEND objtool
INSTALL libsubcmd_headers
CC [M]
== Series Details ==
Series: drm/i915/pxp: Add MTL PXP Support (rev12)
URL : https://patchwork.freedesktop.org/series/112647/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13139_full -> Patchwork_112647v12_full
Summary
Wa_14016712196 implementation for mtl
Bspec: 72197
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 38
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index
MTL uses the peak BW of a QGV point to lock the required QGV
point instead of the QGV index. Instead of passing the deratedbw
of the selected bw_info, return the index to the selected
bw_info so that either deratedbw or peakbw can be used based on
the platform.
v2: use idx to store index returned
Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 235 +---
1 file changed, 130 insertions(+), 105
>From MTL onwards, we need to find the best QGV point based on
the required data rate and pass the peak BW of that point to
the punit to lock the corresponding QGV point.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 87 -
While configuring pmdemand parameters, there could be
intel_get_crtc_new_encoder call where encoders could be 0. To avoid
invoking drm_warn in such cases, use a parameter to indicate drm_warn
should be suppressed.
v2: checkpatch warning fixes
Signed-off-by: Vinod Govindapillai
---
From: Mika Kahola
Display14 introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case
Enable PXP with MTL-GSC-CS: add the has_pxp into device info
and increase the debugfs teardown timeouts to align with
new GSC-CS + firmware specs.
Now that we have 3 places that are selecting pxp timeouts
based on tee vs gsccs back-end, let's add a helper.
Signed-off-by: Alan Previn
pmdemand support patches for MTL
SAGV configuration support for MTL
v2: added one missing patch in the previous version
v3: chekcpatch warning fixes
update index handling for the icl/tgl QGV point handling
program pmdemand code simplified
v4: update to debufs and pipe values pmdemand
Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.
Bspec: 64631
Signed-off-by: Vinod Govindapillai
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
>From MTL onwwards, pcode locks the QGV point based on peak BW of
the intended QGV point passed by the driver. So the peak BW
calculation must match the value expected by the pcode. Update
the calculations as per the Bspec.
v2: use DIV_ROUND_* macro for the calculations (Ville)
Bspec: 64636
In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.
v2: use DIV_ROUND_CLOSEST() for the peakBW calculation
Bspec: 64636
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 8 ++--
On Fri, 05 May 2023 17:58:15 -0700, Umesh Nerlige Ramappa wrote:
>
> From: Tvrtko Ursulin
>
> Reserve some bits in the counter config namespace which will carry the
> tile id and prepare the code to handle this.
>
> No per tile counters have been added yet.
>
> v2:
> - Fix checkpatch issues
> -
On Mon, May 08, 2023, Yan Zhao wrote:
> On Thu, May 04, 2023 at 10:17:20AM +0800, Yan Zhao wrote:
> > On Wed, May 03, 2023 at 04:16:10PM -0700, Sean Christopherson wrote:
> > > Finally getting back to this series...
> > >
> > > On Thu, Mar 23, 2023, Yan Zhao wrote:
> > > > On Fri, Mar 17, 2023 at
Hello
Thanks for the comments. Pls see some inline replies..
On Thu, 2023-04-27 at 17:24 -0300, Gustavo Sousa wrote:
> Quoting Vinod Govindapillai (2023-04-27 12:00:15)
> > From: Mika Kahola
> >
> > Display14 introduces a new way to instruct the PUnit with
> > power and bandwidth requirements
== Series Details ==
Series: drm/i915/guc: Fix confused register capture list creation
URL : https://patchwork.freedesktop.org/series/117655/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
From: John Harrison
The GuC has a completely separate engine class enum when referring to
register capture lists, which combines render and compute. The driver
was using the 'normal' GuC specific engine class enum instead. That
meant that it thought it was defining a capture list for compute
pmu_needs_timer() keeps the timer running even when GT is parked,
ostensibly to sample requested/actual frequencies. However
frequency_sample() has the following:
/* Report 0/0 (actual/requested) frequency while parked. */
if (!intel_gt_pm_get_if_awake(gt))
return;
> > Hi Sean,
> > After more thoughts, do you think checking KVM internal memslot is
> > necessary?
>
> I don't think it's necessary per se, but I also can't think of any reason to
> allow
> it.
>
> > slot = gfn_to_memslot(kvm, gfn);
> > if (!slot || slot->id >= KVM_USER_MEM_SLOTS) {
> >
== Series Details ==
Series: drm/i915/pxp: Add MTL PXP Support (rev12)
URL : https://patchwork.freedesktop.org/series/112647/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13139 -> Patchwork_112647v12
Summary
---
== Series Details ==
Series: drm/i915/guc: Fix confused register capture list creation
URL : https://patchwork.freedesktop.org/series/117655/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13140 -> Patchwork_117655v1
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