On 8/22/2023 11:32 AM, Suraj Kandpal wrote:
Add function to read any PPS register based on the
intel_dsc_pps enum provided. Add a function which will call the
new pps read function and place it in crtc state. Only PPS0 and
PPS1 are readout the rest of the registers will be read in upcoming
== Series Details ==
Series: Add DSC PPS readout (rev9)
URL : https://patchwork.freedesktop.org/series/120456/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13542_full -> Patchwork_120456v9_full
Summary
---
Up until now all dp hdcp specific function derived the aux
from dig_port which gave the aux of the primary port but with
DPMST when a MST hub comes into picture the monitor becomes remote
and what we need is a corresponding aux which is also remote.
These set of patches aim to fix up just that.
Update intel_hdcp_shim funcs specifically read_2_2_message,
write_2_2_message and config_stream_type to use intel_connector
argument instead of intel_digital_port as this will help in getting
correct aux later for dp mst scenarios also already hdcp funcs
derive digital_port from connector and then
We were propagating dig_port info to dp hdcp2 specific functions.
Let us clean that up and send intel_connector in the following
functions: intel_dp_hdcp2_wait_for_msg, get_receiver_id_list_rx_info,
intel_dp_hdcp2_read_rx_status.
This optimises mst scenarios where aux ends up being remote and not
Up until now we were sending the base aux stored in dig_port which
is not correct as this causes an issue when monitor is connected via
a DPMST hub causing it to be remote hence we end up seeing AUX
failures so let's send the remote aux in case of DPMST.
Signed-off-by: Suraj Kandpal
Reviewed-by:
For dpmst hdcp scenario increase the message timeout based
on the number of ports connected as each port needs to be
validated and each will take the prescribed amount of time
for the respective msg_id and total timeout will be
original_timeout * num_ports.
--v2
-Add justification for Adjusting
Assume 8bpc is supported if Sink claims DSC support.
Also consider bpc constraint coming from EDID while computing
input BPC for DSC.
Ankit Nautiyal (2):
drm/display/dp: Default 8 bpc support when DSC is supported
drivers/drm/i915: Honor limits->max_bpp while computing DSC max input
bpp
As per DP v1.4, a DP DSC Sink device shall support 8bpc in DPCD 6Ah.
Apparently some panels that do support DSC, are not setting the bit for
8bpc.
So always assume 8bpc support by DSC decoder, when DSC is claimed to be
supported.
Signed-off-by: Ankit Nautiyal
---
Edid specific BPC constraints are stored in limits->max_bpp. Honor these
limits while computing the input bpp for DSC.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
== Series Details ==
Series: drm/i915/mtl: Adding DeviceID for Arrowlake-S under MTL
URL : https://patchwork.freedesktop.org/series/122754/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13549_full -> Patchwork_122754v1_full
On Fri, 2023-08-18 at 14:27 +0300, Jani Nikula wrote:
> unbind_fence_ops can be const and placed in rodata.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/i915_vma_resource.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
== Series Details ==
Series: Add DSC PPS readout (rev10)
URL : https://patchwork.freedesktop.org/series/120456/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
== Series Details ==
Series: Add DSC PPS readout (rev10)
URL : https://patchwork.freedesktop.org/series/120456/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
== Series Details ==
Series: HDCP MST aux issue fix (rev3)
URL : https://patchwork.freedesktop.org/series/122267/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
== Series Details ==
Series: HDCP MST aux issue fix (rev3)
URL : https://patchwork.freedesktop.org/series/122267/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
On 22/08/23 22:52, Christian König wrote:
Am 21.08.23 um 13:16 schrieb Christian König:
Am 21.08.23 um 12:14 schrieb Arunpravin Paneer Selvam:
The way now contiguous requests are implemented such that
the size rounded up to power of 2 and the corresponding order
block picked from the
== Series Details ==
Series: HDCP MST aux issue fix (rev3)
URL : https://patchwork.freedesktop.org/series/122267/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13549 -> Patchwork_122267v3
Summary
---
**SUCCESS**
Add function to read any PPS register based on the
intel_dsc_pps enum provided. Add a function which will call the
new pps read function and place it in crtc state. Only PPS0 and
PPS1 are readout the rest of the registers will be read in upcoming
patches.
--v2
-Changes in read function as PPS
On Tue, 22 Aug 2023, Alex Hung wrote:
> On 2023-08-22 06:01, Jani Nikula wrote:
>> Over the past years I've been trying to unify the override and firmware
>> EDID handling as well as EDID property updates. It won't work if drivers
>> do their own random things.
> Let's check how to replace these
== Series Details ==
Series: drivers: gpu: drm: i915: intel_huc: fix formatting warnings
URL : https://patchwork.freedesktop.org/series/122746/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13549_full -> Patchwork_122746v1_full
== Series Details ==
Series: Add DSC PPS readout (rev11)
URL : https://patchwork.freedesktop.org/series/120456/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
On Wed, 23 Aug 2023, Suraj Kandpal wrote:
> Add function to read any PPS register based on the
> intel_dsc_pps enum provided. Add a function which will call the
> new pps read function and place it in crtc state. Only PPS0 and
> PPS1 are readout the rest of the registers will be read in upcoming
== Series Details ==
Series: series starting with [CI,1/2] drm: Add an HPD poll helper to reschedule
the poll work (rev2)
URL : https://patchwork.freedesktop.org/series/122736/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13549_full -> Patchwork_122736v2_full
== Series Details ==
Series: Add DSC PPS readout (rev11)
URL : https://patchwork.freedesktop.org/series/120456/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13551 -> Patchwork_120456v11
Summary
---
**SUCCESS**
== Series Details ==
Series: gpu: drm: i915: fix documentation style
URL : https://patchwork.freedesktop.org/series/122747/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13549_full -> Patchwork_122747v1_full
Summary
== Series Details ==
Series: Add DSC PPS readout (rev10)
URL : https://patchwork.freedesktop.org/series/120456/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13551 -> Patchwork_120456v10
Summary
---
**FAILURE**
On Tue, 22 Aug 2023, Suraj Kandpal wrote:
> Add function to read any PPS register based on the
> intel_dsc_pps enum provided. Add a function which will call the
> new pps read function and place it in crtc state. Only PPS0 and
> PPS1 are readout the rest of the registers will be read in upcoming
== Series Details ==
Series: drm/amd/display: stop using drm_edid_override_connector_update() (rev2)
URL : https://patchwork.freedesktop.org/series/122739/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13549_full -> Patchwork_122739v2_full
Up until now we only verified one or two of the dsc pps
params like bits_per_component and bits_per_pixel this
patch series aim to readout almost all PPS param and get
them compared.
Along with that some work on making a common function to
read and write PPS param regiters is also done.
--v2
We have a function that gets us the total of the vdsc engines being
used but not the no. of vdsc instances being used by each pipe.
--v6
-Change function to static
--v7
-Shorten name to intel_dsc_get_vdsc_per_pipe
Signed-off-by: Suraj Kandpal
Reviewed-by: Ankit Nautiyal
---
This patch refactors dsc register related macros that prepares
the values to be written in the register. The current bit shifting
looks bad and going forward will not serve our purpose to readout
dsc register field values the change was suggested by Jani Nikula.
Cc: Jani Nikula
Signed-off-by:
In intel_vdsc_get_config we only read the primary dsc engine register
and not take into account if the other dsc engine is in use and if
both registers have the same value or not this patche fixes that by
adding a check.
--v3
-Remove superfluos new line [Jani]
-Fix register naming [Jani]
--v5
With the dsc config being readout and filled in crtc_state add
macros and use them to compare current and previous PPS param in
DSC.
--v2
-Remove version check [Jani]
-Remove dupe macro for dsc pipe compare and use the existing ones
[Jani]
Signed-off-by: Suraj Kandpal
Reviewed-by: Ankit
Now that we have macros that can fetch dsc register values based
on pipe and pps parameters we can go ahead and remove all the
unused register.
Signed-off-by: Suraj Kandpal
Reviewed-by: Ankit Nautiyal
---
.../gpu/drm/i915/display/intel_vdsc_regs.h| 251 ++
1 file changed,
Add function to read any PPS register based on the
intel_dsc_pps enum provided. Add a function which will call the
new pps read function and place it in crtc state. Only PPS0 and
PPS1 are readout the rest of the registers will be read in upcoming
patches.
--v2
-Changes in read function as PPS
Now that we have a function that reads any PPS register based
on intel_dsc_pps enum provided lets create a function that can
write on any PPS.
--v2
-Changes need as PPS enum was dropped
-Remove duplicated code in intel_dsc_write_pps_reg [Jani]
--v3
-Use dsc_split instead of num_vdsc_instances
We have setup both the read and write functions so we can
move ahead and fill in all the readout state from PPS register
into the crtc_state so we can send it for comparision.
--v2
-Shorten comment to just PPSX rather than having the whole
"Readout PPSX register" [Jani]
-Remove pps_temp
On Tuesday, August 8th, 2023 at 17:04, James Zhu wrote:
> I have a MR for libdrm to support drm nodes type up to 2^MINORBITS
> nodes which can work with these patches,
>
> https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/305
FWIW, this MR has been merged, so in theory this kernel patch
On Wednesday, August 23rd, 2023 at 12:53, Simon Ser wrote:
> On Tuesday, August 8th, 2023 at 17:04, James Zhu jam...@amd.com wrote:
>
> > I have a MR for libdrm to support drm nodes type up to 2^MINORBITS
> > nodes which can work with these patches,
> >
> >
On Tue, Aug 22, 2023 at 11:53:24AM -0700, John Harrison wrote:
> On 8/11/2023 11:20, Zhanjun Dong wrote:
> > This attempts to avoid circular locking dependency between flush delayed
> > work and intel_gt_reset.
> > When intel_gt_reset was called, task will hold a lock.
> > To cacel delayed work
On Wed, Aug 23, 2023 at 10:07:19AM -0700, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli
>
> Add Display Power Well for LNL platform, mostly it is same as MTL
> platform so reused the code
>
> Changes are:
> 1. AUX_CH_CTL and AUX_CH_DATA1 are different from MTL so added extra
>logic
From: Gustavo Sousa
That macro became unused with commit 323286c81245 ("drm/i915: Move the
power domain->well mappings to intel_display_power_map.c").
Signed-off-by: Gustavo Sousa
Reviewed-by: Matt Roper
Signed-off-by: Matt Roper
Link:
Cross posting this to the i915 and xe mailing lists. The basic platform
enabling for Lunar Lake is already applied in xe[1]. This patch series
adds the display support, that will be driven by i915.
A few notes from the series:
1. This is based on drm-xe-next branch since this is where it
From: Gustavo Sousa
It is possible to generalize the "disable" value for the transmitters to
be a bit mask based on the port width and the port reversal boolean,
with a small exception for DP-alt mode with "x1" port width.
Simplify the code by using such a mask and a for-loop instead of using
From: Luca Coelho
This function doesn't really return the pin assignment mask, but the
max lane count derived from that. So rename the function to
mtl_tc_port_get_max_lane_count() to better reflect what it really does.
Signed-off-by: Luca Coelho
Reviewed-by: Suraj Kandpal
Reviewed-by: Lucas
From: Balasubramani Vivekanandan
Add IS_LUNARLAKE in the compat-i915-headers. That macro, to be used by
the xe driver, checks for the platform, whereas the macro on the i915
side is always false.
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h |
From: Stanislav Lisovskiy
BSpec clearly instructs us to use plane scale factor when calculating
relative data rate to be used when allocating DDB blocks for each plane.
For some reason we use scale factor for data_rate calculation, which is
used for BW calculations, however we are not using it
From: Gustavo Sousa
Display must not enable or disable transmitters for not-owned PHY lanes.
BSpec: 64539
Reviewed-by: Mika Kahola
Signed-off-by: Gustavo Sousa
Signed-off-by: Matt Roper
Link:
https://patchwork.freedesktop.org/patch/msgid/20230814131331.69516-4-gustavo.so...@intel.com
From: Balasubramani Vivekanandan
Add Lunar Lake platform definitions for i915 display. The support for
LNL will be added to the xe driver, with i915 only driving the display
side. Therefore define IS_LUNARLAKE to 0 to disable it when building the
i915 module.
Signed-off-by: Balasubramani
Follow the convention of checking the last platform first and reword the
comment to convey there are more platforms than just DG1.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/soc/intel_pch.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git
From: Gustavo Sousa
There are more parts of C10/C20 programming that need to take owned
lanes into account. Define the function intel_cx0_get_owned_lane_mask()
and use it. There will be new users of that function in upcoming
changes.
BSpec: 64539
Reviewed-by: Mika Kahola
Signed-off-by: Gustavo
From: Gustavo Sousa
According to the BSpec, voltage swing programming should be done for
owned PHY lanes. Do not program a not-owned PHY lane.
BSpec: 74103, 74104
Reviewed-by: Mika Kahola
Signed-off-by: Gustavo Sousa
Signed-off-by: Matt Roper
Link:
From: Matt Roper
FBC is no longer limited by pipe.
Bspec: 68881, 68904
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_fbc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h
From: Ravi Kumar Vodapalli
Add Display Power Well for LNL platform, mostly it is same as MTL
platform so reused the code
Changes are:
1. AUX_CH_CTL and AUX_CH_DATA1 are different from MTL so added extra
logic xelpdp_aux_power_well_ops functions.
2. PGPICA1 contains type-C capable port slices
From: Clint Taylor
If a particular pipe is disabled by fuse also remove the FBC for that
pipe.
Bspec: 69464
Cc: Anusha Srivatsa
Cc: Gustavo Sousa
Signed-off-by: Clint Taylor
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display_device.c | 3 +++
1 file changed, 3
From: Stanislav Lisovskiy
We now start calculating relative plane data rate for sursor plane as
well, as instructed by BSpec and also treat cursor plane same way as
other planes, when doing allocation, i.e not using fixed allocation for
cursor anymore.
Signed-off-by: Stanislav Lisovskiy
From: Matt Roper
Xe2_LPD supports DC5, DC6, and DC9 (DC3CO no longer exists). The
overall programming and requirements to enter DC states are similar to
those of Xe_LPD+ although AUX transactions do not require DC5/DC6 exit
as they did previously.
Bspec: 68851, 68857, 68886, 69115
Cc: Anusha
From: Clint Taylor
Do not read DE_RRMR register after display version 20. This register
contains display state information during GFX state dumps.
Bspec: 69456
Cc: Anusha Srivatsa
Cc: Gustavo Sousa
Signed-off-by: Clint Taylor
Signed-off-by: Lucas De Marchi
---
LNL's south display uses the same table as MTP. Check for LNL's fake PCH
to make it consistent with the other checks.
The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in
other cases, uses the same as the previous platform.
Bspec: 68971, 20124
Cc: Anusha Srivatsa
From: Ravi Kumar Vodapalli
Add CDCLK initialization sequence changes and CDCLK set frequency
sequence for LNL platform.
CDCLK frequency change sequence is different for LNL compared to MTL
when a change in mdclk/cdclk ratio is observed. Below are changes to be
made:
1. In MBUS_CTL register
From: Luca Coelho
It is irrelevant for the caller that the max lane count is being
derived from a FIA register, so having "fia" in the function name is
irrelevant. Rename the function accordingly.
Signed-off-by: Luca Coelho
Reviewed-by: Lucas De Marchi
Link:
From: Gustavo Sousa
LNL has south display on the same SoC. As such, define a new fake PCH
entry for it.
Signed-off-by: Gustavo Sousa
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/soc/intel_pch.c | 5 -
drivers/gpu/drm/i915/soc/intel_pch.h | 2 ++
2 files changed, 6
From: Gustavo Sousa
Differently from previous version, Xe2_LPD groups all port AUX interrupt
bits into PICA interrupt registers.
BSpec: 68958, 69697
Signed-off-by: Gustavo Sousa
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 4 +++-
From: Stanislav Lisovskiy
Add a new Lunar Lake CDCLK table from BSpec and also a helper function
in order to be able to find lowest possible CDCLK, which has required
MDCLK for the correspodent pixel rate.
Bspec: 68861
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Lucas De Marchi
---
From: Luca Coelho
This function is only used locally, so make it static and remove the
definition from the header file.
Signed-off-by: Luca Coelho
Reviewed-by: Suraj Kandpal
Link: https://lore.kernel.org/r/2023072121.369227-3-luciano.coe...@intel.com
---
From: Gustavo Sousa
Hotplug setup for Xe2_LPD differs from Xe_LPD+ by the fact that the
extra programming for hotplug inversion and DDI HPD filter duration is
not necessary anymore. As mtp_hpd_irq_setup() is reasonably small,
prefer to fork it into a new function for Xe2_LPD instead of adding a
From: Stanislav Lisovskiy
In Lunar Lake we now separate MDCLK from CDLCK, which used to be before
always 2 times CDCLK. Now we might afford lower CDCLK, while having
higher memory clock, so improving bandwidth and power consumption at the
same time. This is prep work required to enable that.
Xe2_LPD also needs workaround 15010685871.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index
Bits to enable/disable and check state for D2D moved from
XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL. Make the functions
mtl_ddi_disable_d2d() and mtl_ddi_enable_d2d generic to work with
multiple reg location and bitfield layout.
Signed-off-by: Lucas De Marchi
---
From: Ravi Kumar Vodapalli
Add support to check c10 phy link rate for LNL in
intel_c10_phy_check_hdmi_link_rate() function.
BSpec: 68862
Signed-off-by: Ravi Kumar Vodapalli
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 ---
1 file changed, 8
From: Luca Coelho
Starting from display version 20, we need to read the pin assignment
from the IOM TCSS_DDI_STATUS register instead of reading it from the
FIA.
We use the pin assignment to decide the maximum lane count. So, to
support this change, add a new lnl_tc_port_get_max_lane_count()
From: Clint Taylor
Display Ver 20 moved the D2D Enable bit to DDI_BUF_CTL(DDI_CTL_DE)
register. We used multiple variables for HDMI and DisplayPort copies of
this register. Consolidate the various locations to use
intel_digital_port saved_port_bits.
Cc: Anusha Srivatsa
Cc: Gustavo Sousa
Cc:
From: Stanislav Lisovskiy
Previously we always updated DBuf MBUS CTL and DBUF CTL regs after
CDCLK has been changed(CDCLK_CTL), however for Xe2-LPD we can't do like
that anymore. According to BSpec, we have to first update DBuf regs and
then write CDCLK regs, when CDCLK is decreased, which we do
From: Luca Coelho
This makes the code a bit more symmetric and readable, especially when
we start adding more display version-specific alternatives.
Signed-off-by: Luca Coelho
Link: https://lore.kernel.org/r/2023072121.369227-4-luciano.coe...@intel.com
---
From: Matt Roper
Since Xe2LPD technically has FlatCCS, it doesn't have AuxCCS registers
like PLANE_AUX_DIST. However we currently have HAS_FLAT_CCS hardcoded
to 0 since compression isn't ready; we need to make sure this doesn't
cause the display code to go back to trying to write this register.
From: Ravi Kumar Vodapalli
Add PLL Table for Lunar Lake platform.
BSpec: 68862
Cc: Clint Taylor
Cc: Anusha Srivatsa
Signed-off-by: Ravi Kumar Vodapalli
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 411 ++-
1 file changed, 406
From: Balasubramani Vivekanandan
Enable the display support for LUNARLAKE
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/xe_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 7fb00ea410a6..f723e19e8ca5
Some registers for DDI A/B moved to PICA and now follow the same format
as the ones for the PORT_TC ports. The wrapper here deals with 2 issues:
- Share the implementation between xe2lpd and previous
platforms: there are minor layout changes, it's mostly the
register
From: Stanislav Lisovskiy
According to BSpec we need to write the MBUS CTL and DBUF CTL both for
increasing CDCLK case (pre plane) and for decreasing CDCLK case (post
plane). Make sure those updates are in place for Xe2-LPD.
Since the mbus update is not only on pre-enable anymore, also rename
From: Stanislav Lisovskiy
mdclk_cdclk_ratio is a part of dbuf_state and if it changes, it requires
hw to be poked, so we must serialize the global state in that case.
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 19
From: Stanislav Lisovskiy
When we change MDCLK/CDCLK the BSpec now instructs us to write a ratio
between MDCLK/CDCLK to MBUS CTL and DBUF CTL registers during that
change.
Previsouly DBuf state and CDCLK were not anyhow coupled together. Now
at compute stage when we know which CDCLK/MDCLK we
From: Stanislav Lisovskiy
Introduce correspondent definitions and for choosing between CD2X CDCLK
and PLL CDCLK as a source.
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 14 --
drivers/gpu/drm/i915/i915_reg.h
From: Gustavo Sousa
The location of aux channels registers for Xe2 display changed w.r.t.
the previous version.
BSpec: 69010
Signed-off-by: Gustavo Sousa
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 43 -
1 file changed, 42
From: Juha-Pekka Heikkilä
Enable odd size and panning for planar yuv formats.
Cc: Suraj Kandpal
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8
1 file changed, 8 insertions(+)
diff --git
== Series Details ==
Series: HDCP MST aux issue fix (rev3)
URL : https://patchwork.freedesktop.org/series/122267/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13549_full -> Patchwork_122267v3_full
Summary
---
== Series Details ==
Series: Enable Lunar Lake display
URL : https://patchwork.freedesktop.org/series/122799/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/122799/revisions/1/mbox/ not
applied
Applying: drm/i915: Start using plane scale factor
The following changes since commit 0e048b061bde79ad735c7b7b5161ee1bd3400150:
Merge branch 'for-upstream' of https://github.com/CirrusLogic/linux-firmware
(2023-08-14 13:03:41 -0400)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware mtl_gsc_1655
for you
From: Nirmoy Das
Set copy engine arbitration into round robin mode
for part of Wa_16018031267 / Wa_16018063123 mitigation.
Signed-off-by: Nirmoy Das
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
From: Nirmoy Das
Apply WABB blit for Wa_16018031267 / Wa_16018063123.
Additionally, update the lrc selftest to exercise the new
WABB changes.
Signed-off-by: Jonathan Cavitt
Co-developed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +
Apply Wa_16018031267 / Wa_16018063123. This necessitates submitting a
fastcolor blit as WABB and setting the copy engine arbitration to
round-robin mode.
Signed-off-by: Nirmoy Das
Signed-off-by: Jonathan Cavitt
CC: Joonas Lahtinen
CC: Rodrigo Vivi
CC: Tomasz Mistat
CC: Gregory F Germano
On Wed, Aug 23, 2023 at 10:07:14AM -0700, Lucas De Marchi wrote:
> Bits to enable/disable and check state for D2D moved from
> XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL. Make the functions
As of Xe2, DDI_BUF_CTL is now renamed to "DDI_CTL_DE" in the spec, so
you might want to toss a mention of the new
Apply Wa_16018031267 / Wa_16018063123. This necessitates submitting a
fastcolor blit as WABB and setting the copy engine arbitration to
round-robin mode.
v2:
- Rename old platform check in second patch to match
declaration in first patch.
- Refactor second patch name to match first patch.
From: Nirmoy Das
Set copy engine arbitration into round robin mode
for part of Wa_16018031267 / Wa_16018063123 mitigation.
Signed-off-by: Nirmoy Das
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
From: Nirmoy Das
Apply WABB blit for Wa_16018031267 / Wa_16018063123.
Additionally, update the lrc selftest to exercise the new
WABB changes.
Signed-off-by: Jonathan Cavitt
Co-developed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +
On Wed, Aug 23, 2023 at 10:07:16AM -0700, Lucas De Marchi wrote:
> Some registers for DDI A/B moved to PICA and now follow the same format
> as the ones for the PORT_TC ports. The wrapper here deals with 2 issues:
>
> - Share the implementation between xe2lpd and previous
>
On Wed, Aug 23, 2023 at 10:07:18AM -0700, Lucas De Marchi wrote:
> From: Clint Taylor
>
> Do not read DE_RRMR register after display version 20. This register
> contains display state information during GFX state dumps.
>
> Bspec: 69456
> Cc: Anusha Srivatsa
> Cc: Gustavo Sousa
>
On Mon, Aug 21, 2023 at 11:27:29AM +0200, Maxime Ripard wrote:
> On Tue, Aug 15, 2023 at 11:12:46AM +0300, Jani Nikula wrote:
> > On Mon, 14 Aug 2023, Imre Deak wrote:
> > > On Sun, Aug 13, 2023 at 03:41:30PM +0200, Linux regression tracking
> > > (Thorsten Leemhuis) wrote:
> > > Hi,
> > >
> >
On Wed, Aug 23, 2023 at 12:44:56PM -0700, Matt Roper wrote:
> On Wed, Aug 23, 2023 at 10:07:19AM -0700, Lucas De Marchi wrote:
> > From: Ravi Kumar Vodapalli
> >
> > Add Display Power Well for LNL platform, mostly it is same as MTL
> > platform so reused the code
> >
> > Changes are:
> > 1.
On Wed, Aug 23, 2023 at 10:07:21AM -0700, Lucas De Marchi wrote:
> From: Matt Roper
>
> FBC is no longer limited by pipe.
It looks like we lost the part of this patch that adds this to the
xe2_lpd_display device info structure.
Matt
>
> Bspec: 68881, 68904
> Signed-off-by: Matt Roper
>
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