[Intel-gfx] [PATCH] drm/i915: fix tiling limits for i915 class hw v2

Current code is definitely crap: Largest pitch allowed spills into the TILING_Y bit of the fence registers ... :( I've rewritten the limits check under the assumption that 3rd gen hw has a 3d pitch limit of 8kb (like 2nd gen). This is supported by an otherwise totally misleading XXX comment.

[Intel-gfx] [PATCH] strange args for intel_calculate_wm in pineview function

Hi Jesse, This is something I've stumbled upon while crawling through code. Passing a fifo line size instead of a latency is surely not what's ment to happen. Can you please take a look? I think the below patch makes somewhat sense. Yours, Daniel --- drivers/gpu/drm/i915/intel_display.c |4