Re: [Intel-gfx] [PATCH] drm/i915: add timeout to FBC disable waits
On Fri, 21 May 2010 09:40:45 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: FBC disable on 965 can take long enough to trigger latency checks in the kernel so be sure to timeout after a reasonable period. Fixes https://bugzilla.kernel.org/show_bug.cgi?id=15015. Tested-by: James Ettle theholyet...@googlemail.com Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org Applied. Thanks! pgpcubqORQBZ9.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [2.6.34, patch] i915: fix lock imbalance on error path...
On Mon, 17 May 2010 14:23:52 +0100, Daniel J Blueman daniel.blue...@gmail.com wrote: While investigating Intel i5 Arrandale GPU lockups with -rc4, I noticed a lock imbalance. Signed-off-by: Daniel J Blueman daniel.blue...@gmail.com Applied. Thanks! pgpI2j3wFbsWY.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [intel-gfx][PATCH] intel: add a new interface drm_intel_bo_alloc_direct
On Tue, 25 May 2010 13:06:50 +0800, Xiang, Haihao haihao.xi...@intel.com wrote: This interface is the same as drm_intel_bo_alloc except the allocated size isn't rounded up, so it bypasses the cache bucket. The size of the BO created by drm_intel_bo_alloc for a 1920x800,4:2:0 YUV planar surface is 4M, it is about 2.2M if using drm_intel_bo_alloc_direct. You could just init a cache bucket of that size, and get BO caching with no overhead and no new interfaces. pgp4WjQmD35yH.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gen4: Extra CRT hotplug paranoia
On Mon, 24 May 2010 16:46:29 -0400, Adam Jackson a...@redhat.com wrote: Disable the CRT plug interrupt while doing the force cycle, explicitly clear any CRT interrupt we may have generated, and restore when done. Should mitigate interrupt storms from hotplug detection. Nice, I've been hoping someone would write a patch like this. Probably for TV, too. pgpwiD9u5Jf4S.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Return the error code from init_hws()
Otherwise we indicate success in the event of failure and this will lead to an eventual OOPS. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index aacd798..e0e29ae 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4640,7 +4640,7 @@ err_unpin: err_unref: drm_gem_object_unreference(obj); err: - return 0; + return ret; } static void -- 1.7.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] agp/intel: Restrict GTT mapping to valid range on i915 and i945
On Tue, 18 May 2010 12:24:51 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: References: Bug 15733 - Crash when accessing nonexistent GTT entries in i915 https://bugzilla.kernel.org/show_bug.cgi?id=15733 On G33 and above, the size of the GTT space is determined by the GMCH control register. Prior to this revision, the size is determined by the size of the aperture. So we must careful to map and fill the appropriate range depending on chipset. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Applied. Thanks! pgp7jk0C7CyRd.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] agp/intel: Restrict GTT mapping to valid range on i915 and i945
On Tue, 18 May 2010 12:24:51 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: References: Bug 15733 - Crash when accessing nonexistent GTT entries in i915 https://bugzilla.kernel.org/show_bug.cgi?id=15733 On G33 and above, the size of the GTT space is determined by the GMCH control register. Prior to this revision, the size is determined by the size of the aperture. So we must careful to map and fill the appropriate range depending on chipset. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk I'll only forgive you for sending me a non-compiling patch because you figured out a bug that I didn't. Applied. :P pgpwiS8cGl4fX.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Kill dangerous pending-flip debugging
On Sat, 15 May 2010 09:31:17 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: On Sat, 15 May 2010 09:57:03 +0100 Chris Wilson ch...@chris-wilson.co.uk wrote: We can, by virtue of a vblank interrupt firing in the middle of setting up the unpin work (i.e. after we set the unpin_work field and before we write to the ringbuffer) enter intel_finish_page_flip() prior to receiving the pending flip notification. Therefore we can expect to hit intel_finish_page_flip() under normal circumstances without a pending flip and even without installing the pending_flip_obj. This is exacerbated by aperture thrashing whilst binding the framebuffer References: Bug 28079 - glresize causes kernel panic in intel_finish_page_flip. https://bugs.freedesktop.org/show_bug.cgi?id=28079 Yeah, that's true. Good catch. Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org Applied. Thanks! pgpeDKnpHC3y0.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/dp: Add DPCD data to debug output
On Thu, 13 May 2010 14:45:43 -0400, Adam Jackson a...@redhat.com wrote: Signed-off-by: Adam Jackson a...@redhat.com --- drivers/gpu/drm/i915/intel_dp.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 78a75e8..a1a6785 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1216,6 +1216,8 @@ intel_dp_detect(struct drm_connector *connector) if (dp_priv-dpcd[0] != 0) status = connector_status_connected; } + DRM_DEBUG_KMS(DPCD: %hx%hx%hx%hx\n, dp_priv-dpcd[0], + dp_priv-dpcd[1], dp_priv-dpcd[2], dp_priv-dpcd[3]); return status; Applied these. Thanks! pgpcFjy53zR1j.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix HDMI mode select for Cougarpoint PCH
On Wed, 12 May 2010 11:02:14 +0800, Zhenyu Wang zhen...@linux.intel.com wrote: For real HDMI sink, CPT HDMI port has to set 'HDMI' mode flag in order to make HDMI audio work correctly. This is required patch for drm/i915 to enable HDMI audio on CPT PCH, ALSA patch is at http://mailman.alsa-project.org/pipermail/alsa-devel/2010-May/027601.html Tested-by: Fengguang Wu fengguang...@intel.com Signed-off-by: Zhenyu Wang zhen...@linux.intel.com Applied. Thanks! pgpYSSnNOhaua.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH] agp/intel: Fix cache control for Sandybridge
Sandybridge GTT has new cache control bits in PTE, which controls
graphics page cache in LLC or LLC/MLC. This one trys to setup a
new gtt driver for Gen6, and using new type mask function for that.
And this sets cache control to always LLC only by default on Gen6.
As this gtt memory cache control bits are internal to intel hw,
so I don't add new flags in agp_backend.h but add them only in
intel_gtt.c. So drm/i915 stuff needs to know these new flags too.
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/char/agp/intel-agp.c|4 +-
drivers/char/agp/intel-agp.h|6 +++
drivers/char/agp/intel-gtt.c| 96 +++---
drivers/gpu/drm/i915/i915_drv.h | 10
4 files changed, 106 insertions(+), 10 deletions(-)
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index d836a71..5bbc7be 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -816,9 +816,9 @@ static const struct intel_driver_description {
{ PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB,
PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
HD Graphics, NULL, intel_i965_driver },
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB,
PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG,
- Sandybridge, NULL, intel_i965_driver },
+ Sandybridge, NULL, intel_gen6_driver },
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB,
PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG,
- Sandybridge, NULL, intel_i965_driver },
+ Sandybridge, NULL, intel_gen6_driver },
{ 0, 0, NULL, NULL, NULL }
};
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 2547465..c05e3e5 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -60,6 +60,12 @@
#define I810_PTE_LOCAL 0x0002
#define I810_PTE_VALID 0x0001
#define I830_PTE_SYSTEM_CACHED 0x0006
+/* GT PTE cache control fields */
+#define GEN6_PTE_UNCACHED 0x0002
+#define GEN6_PTE_LLC 0x0004
+#define GEN6_PTE_LLC_MLC 0x0006
+#define GEN6_PTE_GFDT 0x0008
+
#define I810_SMRAM_MISCC 0x70
#define I810_GFX_MEM_WIN_SIZE 0x0001
#define I810_GFX_MEM_WIN_32M 0x0001
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index e8ea682..1a255a1 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -45,6 +45,33 @@ static struct gatt_mask intel_i810_masks[] =
.type = INTEL_AGP_CACHED_MEMORY}
};
+#define INTEL_AGP_UNCACHED_MEMORY 0
+#define INTEL_AGP_CACHED_MEMORY_LLC1
+#define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2
+#define INTEL_AGP_CACHED_MEMORY_LLC_MLC3
+#define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4
+
+/* Don't try to pollute agp_backend.h...
+ * AGP_USER_CACHED_MEMORY default to LLC only */
+#define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2)
+#define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4)
+/* bit flag for GFDT type */
+#define AGP_USER_CACHED_MEMORY_GFDT (1 3)
+
+static struct gatt_mask intel_gen6_masks[] =
+{
+ {.mask = I810_PTE_VALID | GEN6_PTE_UNCACHED,
+.type = INTEL_AGP_UNCACHED_MEMORY },
+ {.mask = I810_PTE_VALID | GEN6_PTE_LLC,
+.type = INTEL_AGP_CACHED_MEMORY_LLC },
+ {.mask = I810_PTE_VALID | GEN6_PTE_LLC | GEN6_PTE_GFDT,
+.type = INTEL_AGP_CACHED_MEMORY_LLC_GFDT },
+ {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC,
+.type = INTEL_AGP_CACHED_MEMORY_LLC_MLC },
+ {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC | GEN6_PTE_GFDT,
+.type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT },
+};
+
static struct _intel_private {
struct pci_dev *pcidev; /* device one */
u8 __iomem *registers;
@@ -171,13 +198,6 @@ static void intel_agp_insert_sg_entries(struct agp_memory
*mem,
off_t pg_start, int mask_type)
{
int i, j;
- u32 cache_bits = 0;
-
- if (agp_bridge-dev-device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||
- agp_bridge-dev-device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
- {
- cache_bits = I830_PTE_SYSTEM_CACHED;
- }
for (i = 0, j = pg_start; i mem-page_count; i++, j++) {
writel(agp_bridge-driver-mask_memory(agp_bridge,
@@ -310,6 +330,22 @@ static int intel_i830_type_to_mask_type(struct
agp_bridge_data *bridge,
return 0;
}
+static int intel_gen6_type_to_mask_type(struct agp_bridge_data *bridge,
+ int type)
+{
+ unsigned int type_mask = type ~AGP_USER_CACHED_MEMORY_GFDT;
+ unsigned int gfdt = type AGP_USER_CACHED_MEMORY_GFDT;
+
+ if (type_mask == AGP_USER_UNCACHED_MEMORY)
+ return INTEL_AGP_UNCACHED_MEMORY;
+ else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC)
+ return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT :
+
