introduce a new API to exec on BSD ring buffer.
This is needed by H.264 VLD decoding.
Signed-off-by: Xiang Hai hao
Signed-off-by: Zou Nan hai
---
include/drm/i915_drm.h|5 -
intel/intel_bufmgr.c | 13 +
intel/intel_bufmgr.h |3 +++
intel/intel_bufmgr_gem.
On Tue, Jun 01, 2010 at 05:17:45PM +0800, Xiang, Haihao wrote:
> On Fri, 2010-05-28 at 22:04 +0800, Daniel Vetter wrote:
> > On Tue, May 25, 2010 at 01:06:50PM +0800, Xiang, Haihao wrote:
> > > This interface is the same as drm_intel_bo_alloc except the allocated
> > > size isn't rounded up, so it
On Mon, 31 May 2010 13:58:47 +0800, Zou Nan hai wrote:
> add HAS_BSD check to i915_getparam for user space program
> to query if BSD ring buffer is supported.
>
> Signed-off-by: Zou Nan hai
Applied. Thanks!
pgpaivAJcj1GF.pgp
Description: PGP signature
Another question would be to know if i915 is the correct module for the Intel
HD Graphics from a Clarkdale i3 proc?
Thanks
XabiX
De : Xavier de Almeida
À : intel-gfx@lists.freedesktop.org
Envoyé le : Lun 31 mai 2010, 21h 08min 15s
Objet : [Intel-gfx] Does xf8
On Fri, 2010-05-28 at 22:04 +0800, Daniel Vetter wrote:
> On Tue, May 25, 2010 at 01:06:50PM +0800, Xiang, Haihao wrote:
> > This interface is the same as drm_intel_bo_alloc except the allocated
> > size isn't rounded up, so it bypasses the cache bucket.
> >
> > The size of the BO created by drm_i
From: Zhao Yakui
The non-8 BPC can be used for the eDP output device that is
connected through DP-A or DP-D on PCH. In such case we should
set the PIPECONF dither correctly.
Signed-off-by: Zhao Yakui
Tested-by: Jan-Hendrik Zab
Signed-off-by: Zhenyu Wang
---
drivers/gpu/drm/i915/intel_display
