[Intel-gfx] patches on my 'for-anholt' branch
Eric, I've queued some patches on my 'for-anholt' branch of drm-intel tree. The first and second ones are resent patch for fixing eDP through PCH DP port. And following patches are watermark fixes that recently investigated by Yakui. The last one is FBC enabling patch for Ironlake, after Yakui fixed flicker issue with origin FBC enabling patch by programming the cursor wm properly from an Ironlake sighting. Thanks. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/7] drm/i915: Fix watermark calculation in self-refresh mode
From: Zhao Yakui yakui.z...@intel.com
For self-refresh mode WM calculation's line time should use
mode's htotal instead of hdisplay. surface width is the hdisplay
for display plane and 64 for cursor plane.
Signed-off-by: Zhao Yakui yakui.z...@intel.com
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h |3 +-
drivers/gpu/drm/i915/intel_display.c | 42 -
2 files changed, 27 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9ed8ecd..70b6da1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -176,7 +176,8 @@ struct drm_i915_display_funcs {
int (*get_display_clock_speed)(struct drm_device *dev);
int (*get_fifo_size)(struct drm_device *dev, int plane);
void (*update_wm)(struct drm_device *dev, int planea_clock,
- int planeb_clock, int sr_hdisplay, int pixel_size);
+ int planeb_clock, int sr_hdisplay, int sr_htotal,
+ int pixel_size);
/* clock updates for mode set */
/* cursor updates */
/* render clock increase/decrease */
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c757019..2c3377e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2808,7 +2808,8 @@ static int i830_get_fifo_size(struct drm_device *dev, int
plane)
}
static void pineview_update_wm(struct drm_device *dev, int planea_clock,
- int planeb_clock, int sr_hdisplay, int pixel_size)
+ int planeb_clock, int sr_hdisplay, int unused,
+ int pixel_size)
{
struct drm_i915_private *dev_priv = dev-dev_private;
u32 reg;
@@ -2873,7 +2874,8 @@ static void pineview_update_wm(struct drm_device *dev,
int planea_clock,
}
static void g4x_update_wm(struct drm_device *dev, int planea_clock,
- int planeb_clock, int sr_hdisplay, int pixel_size)
+ int planeb_clock, int sr_hdisplay, int sr_htotal,
+ int pixel_size)
{
struct drm_i915_private *dev_priv = dev-dev_private;
int total_size, cacheline_size;
@@ -2916,11 +2918,11 @@ static void g4x_update_wm(struct drm_device *dev, int
planea_clock,
static const int sr_latency_ns = 12000;
sr_clock = planea_clock ? planea_clock : planeb_clock;
- line_time_us = ((sr_hdisplay * 1000) / sr_clock);
+ line_time_us = ((sr_htotal * 1000) / sr_clock);
/* Use ns/us then divide to preserve precision */
- sr_entries = (((sr_latency_ns / line_time_us) + 1) *
- pixel_size * sr_hdisplay) / 1000;
+ sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
+ pixel_size * sr_hdisplay;
sr_entries = roundup(sr_entries / cacheline_size, 1);
DRM_DEBUG(self-refresh entries: %d\n, sr_entries);
I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
@@ -2947,7 +2949,8 @@ static void g4x_update_wm(struct drm_device *dev, int
planea_clock,
}
static void i965_update_wm(struct drm_device *dev, int planea_clock,
- int planeb_clock, int sr_hdisplay, int pixel_size)
+ int planeb_clock, int sr_hdisplay, int sr_htotal,
+ int pixel_size)
{
struct drm_i915_private *dev_priv = dev-dev_private;
unsigned long line_time_us;
@@ -2959,11 +2962,11 @@ static void i965_update_wm(struct drm_device *dev, int
planea_clock,
static const int sr_latency_ns = 12000;
sr_clock = planea_clock ? planea_clock : planeb_clock;
- line_time_us = ((sr_hdisplay * 1000) / sr_clock);
+ line_time_us = ((sr_htotal * 1000) / sr_clock);
/* Use ns/us then divide to preserve precision */
- sr_entries = (((sr_latency_ns / line_time_us) + 1) *
- pixel_size * sr_hdisplay) / 1000;
+ sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
+ pixel_size * sr_hdisplay;
sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
DRM_DEBUG(self-refresh entries: %d\n, sr_entries);
srwm = I945_FIFO_SIZE - sr_entries;
@@ -2987,7 +2990,8 @@ static void i965_update_wm(struct drm_device *dev, int
planea_clock,
}
static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
- int planeb_clock, int sr_hdisplay, int pixel_size)
+ int planeb_clock, int sr_hdisplay, int sr_htotal,
+ int pixel_size)
{
struct drm_i915_private *dev_priv =
[Intel-gfx] [PATCH 5/7] drm/i915: Apply self-refresh watermark calculation for cursor plane
From: Zhao Yakui yakui.z...@intel.com
In SR mode cursor plane watermark calculation uses same formula
like display plane. This one fixes the case for 965G and G45.
Signed-off-by: Zhao Yakui yakui.z...@intel.com
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h |3 ++
drivers/gpu/drm/i915/intel_display.c | 44 +-
2 files changed, 46 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cf41c96..7c55212 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2119,6 +2119,9 @@
#define PINEVIEW_CURSOR_DFT_WM 0
#define PINEVIEW_CURSOR_GUARD_WM 5
+#define I965_CURSOR_FIFO 64
+#define I965_CURSOR_MAX_WM 32
+#define I965_CURSOR_DFT_WM 8
/* define the Watermark register on Ironlake */
#define WM0_PIPEA_ILK 0x45100
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 43e3710..190f311 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2538,6 +2538,20 @@ static struct intel_watermark_params g4x_wm_info = {
2,
G4X_FIFO_LINE_SIZE,
};
+static struct intel_watermark_params g4x_cursor_wm_info = {
+ I965_CURSOR_FIFO,
+ I965_CURSOR_MAX_WM,
+ I965_CURSOR_DFT_WM,
+ 2,
+ G4X_FIFO_LINE_SIZE,
+};
+static struct intel_watermark_params i965_cursor_wm_info = {
+ I965_CURSOR_FIFO,
+ I965_CURSOR_MAX_WM,
+ I965_CURSOR_DFT_WM,
+ 2,
+ I915_FIFO_LINE_SIZE,
+};
static struct intel_watermark_params i945_wm_info = {
I945_FIFO_SIZE,
I915_MAX_WM,
@@ -2924,7 +2938,18 @@ static void g4x_update_wm(struct drm_device *dev, int
planea_clock,
sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
pixel_size * sr_hdisplay;
sr_entries = roundup(sr_entries / cacheline_size, 1);
- DRM_DEBUG(self-refresh entries: %d\n, sr_entries);
+
+ entries_required = (((sr_latency_ns / line_time_us) +
+1000) / 1000) * pixel_size * 64;
+ entries_required = roundup(entries_required /
+ g4x_cursor_wm_info.cacheline_size,
1);
+ cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
+
+ if (cursor_sr g4x_cursor_wm_info.max_wm)
+ cursor_sr = g4x_cursor_wm_info.max_wm;
+ DRM_DEBUG_KMS(self-refresh watermark: display plane %d
+ cursor %d\n, sr_entries, cursor_sr);
+
I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
} else {
/* Turn off self refresh if both pipes are enabled */
@@ -2955,6 +2980,7 @@ static void i965_update_wm(struct drm_device *dev, int
planea_clock,
struct drm_i915_private *dev_priv = dev-dev_private;
unsigned long line_time_us;
int sr_clock, sr_entries, srwm = 1;
+ int cursor_sr = 16;
/* Calc sr entries for one plane configs */
if (sr_hdisplay (!planea_clock || !planeb_clock)) {
@@ -2973,6 +2999,20 @@ static void i965_update_wm(struct drm_device *dev, int
planea_clock,
if (srwm 0)
srwm = 1;
srwm = 0x1ff;
+
+ sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
+pixel_size * 64;
+ sr_entries = roundup(sr_entries /
+i965_cursor_wm_info.cacheline_size, 1);
+ cursor_sr = i965_cursor_wm_info.fifo_size -
+ (sr_entries + i965_cursor_wm_info.guard_size);
+
+ if (cursor_sr i965_cursor_wm_info.max_wm)
+ cursor_sr = i965_cursor_wm_info.max_wm;
+
+ DRM_DEBUG_KMS(self-refresh watermark: display plane %d
+ cursor %d\n, srwm, cursor_sr);
+
I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
} else {
/* Turn off self refresh if both pipes are enabled */
@@ -2987,6 +3027,8 @@ static void i965_update_wm(struct drm_device *dev, int
planea_clock,
I915_WRITE(DSPFW1, (srwm DSPFW_SR_SHIFT) | (8 16) | (8 8) |
(8 0));
I915_WRITE(DSPFW2, (8 8) | (8 0));
+ /* update cursor SR watermark */
+ I915_WRITE(DSPFW3, (cursor_sr DSPFW_CURSOR_SR_SHIFT));
}
static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
--
1.7.0.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/7] drm/i915: Calculate cursor watermark under non-SR state for Ironlake
From: Zhao Yakui yakui.z...@intel.com
The hardware team suggest that the large buffer method should be
used to calculate the cursor watermark under non-SR state as well,
which is to avoid the flicker when FBC is enabled on Ironlake.
Signed-off-by: Zhao Yakui yakui.z...@intel.com
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h |3 ++
drivers/gpu/drm/i915/intel_display.c | 56 --
2 files changed, 56 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7c55212..99b430a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2149,6 +2149,9 @@
#define ILK_DISPLAY_FIFO 128
#define ILK_DISPLAY_MAXWM 64
#define ILK_DISPLAY_DFTWM 8
+#define ILK_CURSOR_FIFO32
+#define ILK_CURSOR_MAXWM 16
+#define ILK_CURSOR_DFTWM 8
#define ILK_DISPLAY_SR_FIFO512
#define ILK_DISPLAY_MAX_SRWM 0x1ff
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 190f311..ad8b07b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2589,6 +2589,14 @@ static struct intel_watermark_params
ironlake_display_wm_info = {
ILK_FIFO_LINE_SIZE
};
+static struct intel_watermark_params ironlake_cursor_wm_info = {
+ ILK_CURSOR_FIFO,
+ ILK_CURSOR_MAXWM,
+ ILK_CURSOR_DFTWM,
+ 2,
+ ILK_FIFO_LINE_SIZE
+};
+
static struct intel_watermark_params ironlake_display_srwm_info = {
ILK_DISPLAY_SR_FIFO,
ILK_DISPLAY_MAX_SRWM,
@@ -3139,6 +3147,7 @@ static void i830_update_wm(struct drm_device *dev, int
planea_clock, int unused,
}
#define ILK_LP0_PLANE_LATENCY 700
+#define ILK_LP0_CURSOR_LATENCY 1300
static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
int planeb_clock, int sr_hdisplay, int sr_htotal,
@@ -3150,6 +3159,21 @@ static void ironlake_update_wm(struct drm_device *dev,
int planea_clock,
unsigned long line_time_us;
int sr_clock, entries_required;
u32 reg_value;
+ int line_count;
+ int planea_htotal = 0, planeb_htotal = 0;
+ struct drm_crtc *crtc;
+ struct intel_crtc *intel_crtc;
+
+ /* Need htotal for all active display plane */
+ list_for_each_entry(crtc, dev-mode_config.crtc_list, head) {
+ intel_crtc = to_intel_crtc(crtc);
+ if (crtc-enabled) {
+ if (intel_crtc-plane == 0)
+ planea_htotal = crtc-mode.htotal;
+ else
+ planeb_htotal = crtc-mode.htotal;
+ }
+ }
/* Calculate and update the watermark for plane A */
if (planea_clock) {
@@ -3163,7 +3187,20 @@ static void ironlake_update_wm(struct drm_device *dev,
int planea_clock,
if (planea_wm (int)ironlake_display_wm_info.max_wm)
planea_wm = ironlake_display_wm_info.max_wm;
- cursora_wm = 16;
+ /* Use the large buffer method to calculate cursor watermark */
+ line_time_us = (planea_htotal * 1000) / planea_clock;
+
+ /* Use ns/us then divide to preserve precision */
+ line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) /
1000;
+
+ /* calculate the cursor watermark for cursor A */
+ entries_required = line_count * 64 * pixel_size;
+ entries_required = DIV_ROUND_UP(entries_required,
+
ironlake_cursor_wm_info.cacheline_size);
+ cursora_wm = entries_required +
ironlake_cursor_wm_info.guard_size;
+ if (cursora_wm ironlake_cursor_wm_info.max_wm)
+ cursora_wm = ironlake_cursor_wm_info.max_wm;
+
reg_value = I915_READ(WM0_PIPEA_ILK);
reg_value = ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
reg_value |= (planea_wm WM0_PIPE_PLANE_SHIFT) |
@@ -3184,7 +3221,20 @@ static void ironlake_update_wm(struct drm_device *dev,
int planea_clock,
if (planeb_wm (int)ironlake_display_wm_info.max_wm)
planeb_wm = ironlake_display_wm_info.max_wm;
- cursorb_wm = 16;
+ /* Use the large buffer method to calculate cursor watermark */
+ line_time_us = (planeb_htotal * 1000) / planeb_clock;
+
+ /* Use ns/us then divide to preserve precision */
+ line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) /
1000;
+
+ /* calculate the cursor watermark for cursor B */
+ entries_required = line_count * 64 * pixel_size;
+ entries_required = DIV_ROUND_UP(entries_required,
+
[Intel-gfx] [PATCH 7/7] drm/i915: Add frame buffer compression support on Ironlake mobile
From: Zhao Yakui yakui.z...@intel.com
About 0.2W power can be saved on one HP laptop.
Signed-off-by: Zhao Yakui yakui.z...@intel.com
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/gpu/drm/i915/i915_dma.c |9 ++--
drivers/gpu/drm/i915/i915_drv.c |2 +-
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_reg.h | 19 +++
drivers/gpu/drm/i915/i915_suspend.c |9 +++-
drivers/gpu/drm/i915/intel_display.c | 93 +-
6 files changed, 125 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 84ce956..293978d 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1254,7 +1254,7 @@ static void i915_setup_compression(struct drm_device
*dev, int size)
drm_mm_put_block(compressed_fb);
}
- if (!IS_GM45(dev)) {
+ if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) {
compressed_llb = drm_mm_search_free(dev_priv-vram, 4096,
4096, 0);
if (!compressed_llb) {
@@ -1280,8 +1280,9 @@ static void i915_setup_compression(struct drm_device
*dev, int size)
intel_disable_fbc(dev);
dev_priv-compressed_fb = compressed_fb;
-
- if (IS_GM45(dev)) {
+ if (IS_IRONLAKE_M(dev))
+ I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb-start);
+ else if (IS_GM45(dev)) {
I915_WRITE(DPFC_CB_BASE, compressed_fb-start);
} else {
I915_WRITE(FBC_CFB_BASE, cfb_base);
@@ -1289,7 +1290,7 @@ static void i915_setup_compression(struct drm_device
*dev, int size)
dev_priv-compressed_llb = compressed_llb;
}
- DRM_DEBUG(FBC base 0x%08lx, ll base 0x%08lx, size %dM\n, cfb_base,
+ DRM_DEBUG_KMS(FBC base 0x%08lx, ll base 0x%08lx, size %dM\n, cfb_base,
ll_base, size 20);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 423dc90..f4729d6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -134,7 +134,7 @@ static const struct intel_device_info intel_ironlake_d_info
= {
static const struct intel_device_info intel_ironlake_m_info = {
.is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
- .need_gfx_hws = 1, .has_rc6 = 1,
+ .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
.has_hotplug = 1,
};
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 70b6da1..c38e00a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1040,6 +1040,7 @@ extern void intel_modeset_cleanup(struct drm_device *dev);
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
extern void i8xx_disable_fbc(struct drm_device *dev);
extern void g4x_disable_fbc(struct drm_device *dev);
+extern void ironlake_disable_fbc(struct drm_device *dev);
extern void intel_disable_fbc(struct drm_device *dev);
extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
extern bool intel_fbc_enabled(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 99b430a..6906b45 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -462,6 +462,21 @@
#define DPFC_CHICKEN 0x3224
#define DPFC_HT_MODIFY (131)
+/* Framebuffer compression for Ironlake */
+#define ILK_DPFC_CB_BASE 0x43200
+#define ILK_DPFC_CONTROL 0x43208
+/* The bit 28-8 is reserved */
+#define DPFC_RESERVED(0x1F00)
+#define ILK_DPFC_RECOMP_CTL0x4320c
+#define ILK_DPFC_STATUS0x43210
+#define ILK_DPFC_FENCE_YOFF0x43218
+#define ILK_DPFC_CHICKEN 0x43224
+#define ILK_FBC_RT_BASE0x2128
+#define ILK_FBC_RT_VALID (10)
+
+#define ILK_DISPLAY_CHICKEN1 0x42000
+#define ILK_FBCQ_DIS (122)
+
/*
* GPIO regs
*/
@@ -2450,6 +2465,10 @@
#define ILK_VSDPFD_FULL (121)
#define ILK_DSPCLK_GATE0x42020
#define ILK_DPARB_CLK_GATE(15)
+/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
+#define ILK_CLK_FBC (17)
+#define ILK_DPFC_DIS1(18)
+#define ILK_DPFC_DIS2(19)
#define DISP_ARB_CTL 0x45000
#define DISP_TILE_SURFACE_SWIZZLING (113)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c
b/drivers/gpu/drm/i915/i915_suspend.c
index 60a5800..6e20252 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -602,7 +602,9 @@ void i915_save_display(struct drm_device *dev)
/* Only save FBC state on the platform that supports FBC */
if (I915_HAS_FBC(dev)) {
- if (IS_GM45(dev)) {
+ if (IS_IRONLAKE_M(dev)) {
+
[Intel-gfx] [PATCH 4/7] drm/i915: Fix fifo size for self-refresh watermark on 965G
From: Zhao Yakui yakui.z...@intel.com
The total self-refresh fifo entry size for display plane is 512
instead of 128 for 965G. Also fix WM value mask for 965G.
About 1.0W power can be saved on one T61 laptop after the self-refresh
watermark is configured correctly.
Signed-off-by: Zhao Yakui yakui.z...@intel.com
Signed-off-by: Zhenyu wang zhen...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h |3 ++-
drivers/gpu/drm/i915/intel_display.c |4 ++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 64b0a3a..cf41c96 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2099,7 +2099,8 @@
#define I830_FIFO_LINE_SIZE32
#define G4X_FIFO_SIZE 127
-#define I945_FIFO_SIZE 127 /* 945 965 */
+#define I965_FIFO_SIZE 512
+#define I945_FIFO_SIZE 127
#define I915_FIFO_SIZE 95
#define I855GM_FIFO_SIZE 127 /* In cachelines */
#define I830_FIFO_SIZE 95
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2c3377e..43e3710 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2969,10 +2969,10 @@ static void i965_update_wm(struct drm_device *dev, int
planea_clock,
pixel_size * sr_hdisplay;
sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
DRM_DEBUG(self-refresh entries: %d\n, sr_entries);
- srwm = I945_FIFO_SIZE - sr_entries;
+ srwm = I965_FIFO_SIZE - sr_entries;
if (srwm 0)
srwm = 1;
- srwm = 0x3f;
+ srwm = 0x1ff;
I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
} else {
/* Turn off self refresh if both pipes are enabled */
--
1.7.0.4
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[Intel-gfx] [PATCH] drm/i915: Turn on 945 self-refresh only if single CRTC is active
Enable self-refresh on 945 when just one CRTC is activated.
Otherwise user would get display flicker with dual display.
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=27667
Signed-off-by: Li Peng peng...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 12 +++-
1 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 88a1ab7..04c18a2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4469,6 +4469,7 @@ static void intel_idle_update(struct work_struct *work)
struct drm_device *dev = dev_priv-dev;
struct drm_crtc *crtc;
struct intel_crtc *intel_crtc;
+ int enabled = 0;
if (!i915_powersave)
return;
@@ -4477,21 +4478,22 @@ static void intel_idle_update(struct work_struct *work)
i915_update_gfx_val(dev_priv);
- if (IS_I945G(dev) || IS_I945GM(dev)) {
- DRM_DEBUG_DRIVER(enable memory self refresh on 945\n);
- I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
- }
-
list_for_each_entry(crtc, dev-mode_config.crtc_list, head) {
/* Skip inactive CRTCs */
if (!crtc-fb)
continue;
+ enabled++;
intel_crtc = to_intel_crtc(crtc);
if (!intel_crtc-busy)
intel_decrease_pllclock(crtc);
}
+ if ((enabled == 1) (IS_I945G(dev) || IS_I945GM(dev))) {
+ DRM_DEBUG_DRIVER(enable memory self refresh on 945\n);
+ I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
+ }
+
mutex_unlock(dev-struct_mutex);
}
--
1.6.6.1
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Re: [Intel-gfx] [PATCH 1/7 resend] drm/i915: Add the support of eDP on DP-D for Ibex/CPT
On Sat, 12 Jun 2010 14:32:21 +0800, Zhenyu Wang zhen...@linux.intel.com wrote:
From: Zhao Yakui yakui.z...@intel.com
This one adds support for eDP that connected on PCH DP-D port
instead of CPU DP-A port, and only DP-D port could be used for eDP.
https://bugs.freedesktop.org/show_bug.cgi?id=27220
Signed-off-by: Zhao Yakui yakui.z...@intel.com
Tested-by: Jan-Hendrik Zab j...@jhz.name
Tested-by: Templar temp...@rshc.de
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
[snip]
static void
-intel_dp_compute_m_n(int bytes_per_pixel,
+intel_dp_compute_m_n(int bpp,
int nlanes,
int pixel_clock,
int link_clock,
struct intel_dp_m_n *m_n)
{
m_n-tu = 64;
- m_n-gmch_m = pixel_clock * bytes_per_pixel;
+ m_n-gmch_m = (pixel_clock * bpp) 3;
m_n-gmch_n = link_clock * nlanes;
intel_reduce_ratio(m_n-gmch_m, m_n-gmch_n);
m_n-link_m = pixel_clock;
This rounds the gmch_m down. Is this correct? And how close to overflow
is pixel_clock today?
-ickle
--
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] [PATCH] fix some intel_ring_begin size
Fix some intel_ring_begin size parameter.
Signed-off-by: Zou Nan hai nanhai@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index cea4f1a..9421d1c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -406,7 +406,7 @@ bsd_ring_add_request(struct drm_device *dev,
{
u32 seqno;
seqno = intel_ring_get_seqno(dev, ring);
- intel_ring_begin(dev, ring, 4);
+ intel_ring_begin(dev, ring, 16);
intel_ring_emit(dev, ring, MI_STORE_DWORD_INDEX);
intel_ring_emit(dev, ring,
I915_GEM_HWS_INDEX MI_STORE_DWORD_INDEX_SHIFT);
@@ -456,7 +456,7 @@ bsd_ring_dispatch_gem_execbuffer(struct drm_device *dev,
{
uint32_t exec_start;
exec_start = (uint32_t) exec_offset + exec-batch_start_offset;
- intel_ring_begin(dev, ring, 2);
+ intel_ring_begin(dev, ring, 8);
intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START |
(2 6) | MI_BATCH_NON_SECURE_I965);
intel_ring_emit(dev, ring, exec_start);
@@ -492,14 +492,14 @@ render_ring_dispatch_gem_execbuffer(struct drm_device
*dev,
}
if (IS_I830(dev) || IS_845G(dev)) {
- intel_ring_begin(dev, ring, 4);
+ intel_ring_begin(dev, ring, 16);
intel_ring_emit(dev, ring, MI_BATCH_BUFFER);
intel_ring_emit(dev, ring,
exec_start | MI_BATCH_NON_SECURE);
intel_ring_emit(dev, ring, exec_start + exec_len - 4);
intel_ring_emit(dev, ring, 0);
} else {
- intel_ring_begin(dev, ring, 4);
+ intel_ring_begin(dev, ring, 16);
if (IS_I965G(dev)) {
intel_ring_emit(dev, ring,
MI_BATCH_BUFFER_START | (2 6)
--
1.7.1
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[Intel-gfx] Fwd: brightness
* * *hello linux intel team!!* ** * * *i have an hp pavilion dv1000 laptop* *and i have problems to get my brightness darker* *its full of ilumination * *fn f7 and fn f8 buttons work* *but in windows xp intel has an application to make less or more brighter the display* *the gnome brightness manager doesnt work in arch linux* *can you help me?* * Linux 2.6.33-ARCH #1 SMP PREEMPT Thu May 13 12:06:25 CEST 2010 i686 Intel(R) Pentium(R) M processor 1.60GHz GenuineIntel GNU/Linux * *I HAVE tried these methods but i havent been successfull in them He intentado estos metodos para poderle bajar mas el brillo: * Usar xbacklight -set 50% no funciona: No display has backlight capabilities ... * Gnome Brightness Aplet muestra sello rojo y no funciona * /proc/acpi/video/GFX0 theres only 0 bytes files there * xrandr Method --output ... --SET BACKLIGHT ... lspci 00:00.0 Host bridge: Intel Corporation Mobile 915GM/PM/GMS/910GML Express Processor to DRAM Controller (rev 03) 00:02.0 VGA compatible controller: Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller (rev 03) 00:02.1 Display controller: Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller (rev 03) 00:1d.0 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1 (rev 03) 00:1d.1 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2 (rev 03) 00:1d.2 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3 (rev 03) 00:1d.3 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4 (rev 03) 00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 03) 00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev d3) 00:1e.2 Multimedia audio controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Audio Controller (rev 03) 00:1e.3 Modem: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Modem Controller (rev 03) 00:1f.0 ISA bridge: Intel Corporation 82801FBM (ICH6M) LPC Interface Bridge (rev 03) 00:1f.1 IDE interface: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) IDE Controller (rev 03) 00:1f.3 SMBus: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller (rev 03) 06:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) 06:06.0 Network controller: Intel Corporation PRO/Wireless 2200BG [Calexico2] Network Connection (rev 05) 06:09.0 CardBus bridge: Texas Instruments PCIxx21/x515 Cardbus Controller 06:09.2 FireWire (IEEE 1394): Texas Instruments OHCI Compliant IEEE 1394 Host Controller 06:09.3 Mass storage controller: Texas Instruments PCIxx21 Integrated FlashMedia Controller 06:09.4 SD Host controller: Texas Instruments PCI6411/6421/6611/6621/7411/7421/7611/7621 Secure Digital Controller *Lic. Jesús Alberto Guzmán Inzunza Linux registered user #429629 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/7 resend] drm/i915: Add the support of eDP on DP-D for Ibex/CPT
On Sat, 2010-06-12 at 16:28 +0800, Chris Wilson wrote:
On Sat, 12 Jun 2010 14:32:21 +0800, Zhenyu Wang zhen...@linux.intel.com
wrote:
From: Zhao Yakui yakui.z...@intel.com
This one adds support for eDP that connected on PCH DP-D port
instead of CPU DP-A port, and only DP-D port could be used for eDP.
https://bugs.freedesktop.org/show_bug.cgi?id=27220
Signed-off-by: Zhao Yakui yakui.z...@intel.com
Tested-by: Jan-Hendrik Zab j...@jhz.name
Tested-by: Templar temp...@rshc.de
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
[snip]
static void
-intel_dp_compute_m_n(int bytes_per_pixel,
+intel_dp_compute_m_n(int bpp,
int nlanes,
int pixel_clock,
int link_clock,
struct intel_dp_m_n *m_n)
{
m_n-tu = 64;
- m_n-gmch_m = pixel_clock * bytes_per_pixel;
+ m_n-gmch_m = (pixel_clock * bpp) 3;
m_n-gmch_n = link_clock * nlanes;
intel_reduce_ratio(m_n-gmch_m, m_n-gmch_n);
m_n-link_m = pixel_clock;
This rounds the gmch_m down. Is this correct? And how close to overflow
is pixel_clock today?
The bpp is the abbreviation of bits per pixel and this is not round
down. It is only to convert the bits per second to bytes per second,
which will be used to calculation the DP M/N .
-ickle
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