[Intel-gfx] [PATCH] drm/i915: Enable aspect/centering panel fitting for Ironlake.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h |2 +
drivers/gpu/drm/i915/intel_display.c | 16 +++
drivers/gpu/drm/i915/intel_lvds.c| 70 --
3 files changed, 75 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 57d24f8..0e7bf85 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -599,6 +599,8 @@ typedef struct drm_i915_private {
struct sdvo_device_mapping sdvo_mappings[2];
/* indicate whether the LVDS_BORDER should be enabled or not */
unsigned int lvds_border_bits;
+ /* Panel fitter placement and size for Ironlake+ */
+ u32 pch_pf_pos, pch_pf_size;
struct drm_crtc *plane_to_crtc_mapping[2];
struct drm_crtc *pipe_to_crtc_mapping[2];
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d56184c..d476752 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1918,15 +1918,13 @@ static int ironlake_crtc_dpms(struct drm_crtc *crtc,
int mode)
/* Enable panel fitting for LVDS */
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
- temp = I915_READ(pf_ctl_reg);
- I915_WRITE(pf_ctl_reg, temp | PF_ENABLE |
PF_FILTER_MED_3x3);
-
- /* currently full aspect */
- I915_WRITE(pf_win_pos, 0);
-
- I915_WRITE(pf_win_size,
- (dev_priv-panel_fixed_mode-hdisplay 16)
|
- (dev_priv-panel_fixed_mode-vdisplay));
+ if (dev_priv-pch_pf_size) {
+ temp = I915_READ(pf_ctl_reg);
+ I915_WRITE(pf_ctl_reg, temp | PF_ENABLE |
PF_FILTER_MED_3x3);
+ I915_WRITE(pf_win_pos, dev_priv-pch_pf_pos);
+ I915_WRITE(pf_win_size, dev_priv-pch_pf_size);
+ } else
+ I915_WRITE(pf_ctl_reg, temp ~PF_ENABLE);
}
/* Enable CPU pipe */
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index 6b399e0..56d233d 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -215,6 +215,68 @@ static inline u32 panel_fitter_scaling(u32 source, u32
target)
return (FACTOR * ratio + FACTOR/2) / FACTOR;
}
+static bool
+intel_pch_lvds_mode_fixup(struct intel_lvds *intel_lvds,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ struct drm_device *dev = intel_lvds-base.enc.dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct drm_display_mode *fixed_mode = dev_priv-panel_fixed_mode;
+ int x, y, width, height;
+
+ x = y = width = height = 0;
+
+ /* Native modes don't need fitting */
+ if (adjusted_mode-hdisplay == mode-hdisplay
+ adjusted_mode-vdisplay == mode-vdisplay)
+ goto done;
+
+ switch (intel_lvds-fitting_mode) {
+ case DRM_MODE_SCALE_CENTER:
+ width = mode-hdisplay;
+ height = mode-vdisplay;
+ x = (fixed_mode-hdisplay - width + 1)/2;
+ y = (fixed_mode-vdisplay - height + 1)/2;
+ break;
+
+ case DRM_MODE_SCALE_ASPECT:
+ /* Scale but preserve the aspect ratio */
+ {
+ u32 scaled_width = fixed_mode-hdisplay *
mode-vdisplay;
+ u32 scaled_height = mode-hdisplay *
fixed_mode-vdisplay;
+ if (scaled_width scaled_height) { /* pillar */
+ width = scaled_height / mode-vdisplay;
+ x = (fixed_mode-hdisplay - width + 1) / 2;
+ y = 0;
+ height = fixed_mode-vdisplay;
+ } else if (scaled_width scaled_height) { /* letter */
+ height = scaled_width / mode-hdisplay;
+ y = (fixed_mode-vdisplay - height + 1) / 2;
+ x = 0;
+ width = fixed_mode-hdisplay;
+ } else {
+ x = y = 0;
+ width = fixed_mode-hdisplay;
+ height = fixed_mode-vdisplay;
+ }
+ }
+ break;
+
+ default:
+ case DRM_MODE_SCALE_FULLSCREEN:
+ x = y = 0;
+ width = fixed_mode-hdisplay;
+ height = fixed_mode-vdisplay;
+ break;
+ }
+
+done:
+ dev_priv-pch_pf_pos =
[Intel-gfx] Need to add a quirk to xserver-xorg-video-intel
Hello, I'm needing to add a quirk to xf86-video-intel. It looks like I can get the first two columns from lspci (chipType, subsysVendor == [VEND:CHIP])... But I can't figure out how to get the number for subsysCard. (But I gather that I need to interpret `dmidecode` for this part.) Thanks in advance! -gabriel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Need to add a quirk to xserver-xorg-video-intel
On Wed, Jul 21, 2010 at 1:26 PM, Gabriel M. Beddingfield
I'm needing to add a quirk to xf86-video-intel. It looks like I can get the
first two columns from lspci (chipType, subsysVendor == [VEND:CHIP])...
But I can't figure out how to get the number for subsysCard. (But I gather
that I need to interpret `dmidecode` for this part.)
Duh, I overlooked the answer here:
$ lspci -vvnn | grep -A1 VGA compat
00:02.0 VGA compatible controller [0300]: Intel Corporation Mobile
4 Series Chipset Integrated Graphics Controller [8086:2a42] (rev 07)
Subsystem: Micro-Star International Co., Ltd. Device [1462:1021]
So, looks like my row will be:
{PCI_CHIP_GM45_GM, 0x1462, 0x1021, quirk_ignore_tv}
Thanks,
Gabriel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: be sure panel is powered up in eDP configs
Hi!,
so what is the state of this ?
From: Adam Jackson a...@redhat.com
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 1/6] drm/i915/dp: Rename has_edp to
is_pch_edp to reflect its real meaning
Date: Fri, 16 Jul 2010 14:46:27 -0400 (07/16/2010 07:46:27 PM)
seems that have something related to this.
Should I try yours patch in this email ?
On Wed, 2010-07-14 at 15:40 -0700, Jesse Barnes wrote:
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=28739. We need to
enable power to the panel with the AUX VDD bit in order to properly
detect the eDP attached panel, and we also need to turn the panel on in
case it was off when we started (as happens at resume time).
But this patch raises a couple of questions:
1) why does the first panel on sequence time out?
2) why do I need to unlock the panel protected regs?
Keith, I think this is your code, any ideas?
Thanks,
Jesse
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 42c6024..b191f02 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2805,6 +2805,7 @@
#define PCH_PP_STATUS0xc7200
#define PCH_PP_CONTROL 0xc7204
+#define PANEL_UNLOCK_REGS (0xabcd 16)
#define EDP_FORCE_VDD (1 3)
#define EDP_BLC_ENABLE (1 2)
#define PANEL_POWER_RESET (1 1)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b4f0282..a20dd7b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -744,6 +744,32 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct
drm_display_mode *mode,
}
}
+static void ironlake_edp_panel_on(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ unsigned long timeout = jiffies + msecs_to_jiffies(5000);
+ u32 pp, pp_status;
+
+ pp_status = I915_READ(PCH_PP_STATUS);
+ if (pp_status PP_ON)
+ return;
+
+ DRM_DEBUG_KMS(\n);
+ pp = I915_READ(PCH_PP_CONTROL);
+ pp |= POWER_TARGET_ON;
+ I915_WRITE(PCH_PP_CONTROL, pp);
+ do {
+ pp_status = I915_READ(PCH_PP_STATUS);
+ } while (((pp_status PP_ON) == 0) !time_after(jiffies, timeout));
+
+ if (time_after(jiffies, timeout))
+ DRM_DEBUG_KMS(panel on wait timed out: 0x%08x\n, pp_status);
+
+ pp |= PANEL_UNLOCK_REGS;
+ pp = ~EDP_FORCE_VDD;
+ I915_WRITE(PCH_PP_CONTROL, pp);
+}
+
static void ironlake_edp_backlight_on (struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -755,6 +781,28 @@ static void ironlake_edp_backlight_on (struct drm_device
*dev)
I915_WRITE(PCH_PP_CONTROL, pp);
}
+static void ironlake_edp_panel_off(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ unsigned long timeout = jiffies + msecs_to_jiffies(5000);
+ u32 pp, pp_status;
+
+ DRM_DEBUG_KMS(\n);
+ pp = I915_READ(PCH_PP_CONTROL);
+ pp = ~POWER_TARGET_ON;
+ I915_WRITE(PCH_PP_CONTROL, pp);
+ do {
+ pp_status = I915_READ(PCH_PP_STATUS);
+ } while ((pp_status PP_ON) !time_after(jiffies, timeout));
+
+ if (time_after(jiffies, timeout))
+ DRM_DEBUG_KMS(panel off wait timed out\n);
+
+ /* Make sure VDD is enabled so DP AUX will work */
+ pp |= EDP_FORCE_VDD;
+ I915_WRITE(PCH_PP_CONTROL, pp);
+}
+
static void ironlake_edp_backlight_off (struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -776,16 +824,24 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
uint32_t dp_reg = I915_READ(dp_priv-output_reg);
if (mode != DRM_MODE_DPMS_ON) {
+ if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
+ ironlake_edp_backlight_off(dev);
+ ironlake_edp_panel_off(dev);
+ }
if (dp_reg DP_PORT_EN) {
intel_dp_link_down(intel_encoder, dp_priv-DP);
- if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv))
- ironlake_edp_backlight_off(dev);
}
} else {
+ /* Turn off the panel so we can modify DP_A etc */
+ if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv))
+ ironlake_edp_panel_off(dev);
if (!(dp_reg DP_PORT_EN)) {
intel_dp_link_train(intel_encoder, dp_priv-DP,
dp_priv-link_configuration);
- if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv))
- ironlake_edp_backlight_on(dev);
+ }
+ if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
+ if (I915_READ(dp_priv-output_reg) DP_PORT_EN)
+ ironlake_edp_panel_on(dev);
+
