[Intel-gfx] [PATCH] drm/i915/ringbuffer: Set ring-gem_buffer = NULL on init unwind
The cleanup path for early abort failed to nullify the gem_buffer. The
likely consequence of this is zero, since a failure here should mean
aborting the module load.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 31 +--
1 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3a02425..7823b96 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -608,9 +608,10 @@ err:
int intel_init_ring_buffer(struct drm_device *dev,
struct intel_ring_buffer *ring)
{
- int ret;
struct drm_i915_gem_object *obj_priv;
struct drm_gem_object *obj;
+ int ret;
+
ring-dev = dev;
if (I915_NEED_GFX_HWS(dev)) {
@@ -623,16 +624,14 @@ int intel_init_ring_buffer(struct drm_device *dev,
if (obj == NULL) {
DRM_ERROR(Failed to allocate ringbuffer\n);
ret = -ENOMEM;
- goto cleanup;
+ goto err_hws;
}
ring-gem_object = obj;
ret = i915_gem_object_pin(obj, ring-alignment);
- if (ret != 0) {
- drm_gem_object_unreference(obj);
- goto cleanup;
- }
+ if (ret)
+ goto err_unref;
obj_priv = to_intel_bo(obj);
ring-map.size = ring-size;
@@ -644,18 +643,14 @@ int intel_init_ring_buffer(struct drm_device *dev,
drm_core_ioremap_wc(ring-map, dev);
if (ring-map.handle == NULL) {
DRM_ERROR(Failed to map ringbuffer.\n);
- i915_gem_object_unpin(obj);
- drm_gem_object_unreference(obj);
ret = -EINVAL;
- goto cleanup;
+ goto err_unpin;
}
ring-virtual_start = ring-map.handle;
ret = ring-init(dev, ring);
- if (ret != 0) {
- intel_cleanup_ring_buffer(dev, ring);
- return ret;
- }
+ if (ret)
+ goto err_unmap;
if (!drm_core_check_feature(dev, DRIVER_MODESET))
i915_kernel_lost_context(dev);
@@ -669,7 +664,15 @@ int intel_init_ring_buffer(struct drm_device *dev,
INIT_LIST_HEAD(ring-active_list);
INIT_LIST_HEAD(ring-request_list);
return ret;
-cleanup:
+
+err_unmap:
+ drm_core_ioremapfree(ring-map, dev);
+err_unpin:
+ i915_gem_object_unpin(obj);
+err_unref:
+ drm_gem_object_unreference(obj);
+ ring-gem_object = NULL;
+err_hws:
cleanup_status_page(dev, ring);
return ret;
}
--
1.7.1
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[Intel-gfx] [PATCH] drm/i915: Implement fair lru eviction across both rings. (v2)
Based in a large part upon Daniel Vetter's implementation and adapted
for handling multiple rings in a single pass.
This should lead to better gtt usage and fixes the page-fault-of-doom
triggered. The fairness is provided by scanning through the GTT space
amalgamating space in rendering order. As soon as we have a contiguous
space in the GTT large enough for the new object (and its alignment),
evict any object which lies within that space. This should keep more
objects resident in the GTT.
Doing throughput testing on a PineView machine with cairo-perf-trace
indicates that there is very little difference with the new LRU scan,
perhaps a small improvement... Except oddly for the poppler trace.
Reference:
Bug 15911 - Intermittent X crash (freeze)
https://bugzilla.kernel.org/show_bug.cgi?id=15911
Bug 20152 - cannot view JPG in firefox when running UXA
https://bugs.freedesktop.org/show_bug.cgi?id=20152
Bug 24369 - Hang when scrolling firefox page with window in front
https://bugs.freedesktop.org/show_bug.cgi?id=24369
Bug 28478 - Intermittent graphics lockups due to overflow/loop
https://bugs.freedesktop.org/show_bug.cgi?id=28478
v2: Attempt to clarify the logic and order of eviction through the use
of comments and macros.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Daniel Vetter dan...@ffwll.ch
---
drivers/gpu/drm/i915/i915_drv.h |2 +
drivers/gpu/drm/i915/i915_gem_evict.c | 276 +
2 files changed, 144 insertions(+), 134 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 75fe397..61a8c90 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -668,6 +668,8 @@ struct drm_i915_gem_object {
struct list_head list;
/** This object's place on GPU write list */
struct list_head gpu_write_list;
+ /** This object's place on eviction list */
+ struct list_head evict_list;
/**
* This is set if the object is on the active or flushing lists
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index 479e450..17ec91f 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -31,167 +31,175 @@
#include i915_drv.h
#include i915_drm.h
-static inline int
-i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
-{
- return obj_priv-madv == I915_MADV_DONTNEED;
-}
-
-static int
-i915_gem_scan_inactive_list_and_evict(struct drm_device *dev, int min_size,
- unsigned alignment, int *found)
+static struct drm_i915_gem_object *
+i915_gem_next_active_object(struct drm_device *dev,
+ struct list_head **render_iter,
+ struct list_head **bsd_iter)
{
drm_i915_private_t *dev_priv = dev-dev_private;
- struct drm_gem_object *obj;
- struct drm_i915_gem_object *obj_priv;
- struct drm_gem_object *best = NULL;
- struct drm_gem_object *first = NULL;
-
- /* Try to find the smallest clean object */
- list_for_each_entry(obj_priv, dev_priv-mm.inactive_list, list) {
- struct drm_gem_object *obj = obj_priv-base;
- if (obj-size = min_size) {
- if ((!obj_priv-dirty ||
-i915_gem_object_is_purgeable(obj_priv))
- (!best || obj-size best-size)) {
- best = obj;
- if (best-size == min_size)
- break;
- }
- if (!first)
- first = obj;
- }
- }
+ struct drm_i915_gem_object *render_obj = NULL, *bsd_obj = NULL;
- obj = best ? best : first;
+ if (*render_iter != dev_priv-render_ring.active_list)
+ render_obj = list_entry(*render_iter,
+ struct drm_i915_gem_object,
+ list);
- if (!obj) {
- *found = 0;
- return 0;
- }
+ if (HAS_BSD(dev)) {
+ if (*bsd_iter != dev_priv-bsd_ring.active_list)
+ bsd_obj = list_entry(*bsd_iter,
+struct drm_i915_gem_object,
+list);
- *found = 1;
+ if (render_obj == NULL) {
+ *bsd_iter = (*bsd_iter)-next;
+ return bsd_obj;
+ }
-#if WATCH_LRU
- DRM_INFO(%s: evicting %p\n, __func__, obj);
-#endif
- obj_priv = to_intel_bo(obj);
- BUG_ON(obj_priv-pin_count != 0);
- BUG_ON(obj_priv-active);
+ if (bsd_obj == NULL) {
+ *render_iter = (*render_iter)-next;
+ return render_obj;
+
[Intel-gfx] [PATCH] drm/i915/edp: Flush the write before waiting for PLLs
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- drivers/gpu/drm/i915/intel_display.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9814182..5cae58a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1570,6 +1570,7 @@ static void ironlake_enable_pll_edp (struct drm_crtc *crtc) dpa_ctl = I915_READ(DP_A); dpa_ctl |= DP_PLL_ENABLE; I915_WRITE(DP_A, dpa_ctl); + POSTING_READ(DP_A); udelay(200); } -- 1.7.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Ensure that while(INREG()) are bounded.
Add a new macro, wait_for, to simplify the act of waiting on a register
to change state. wait_for() takes three arguments, the condition to
inspect on every loop, the maximum amount of time to wait and whether to
yield the cpu for a length of time after each check.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_crt.c | 17 --
drivers/gpu/drm/i915/intel_display.c | 54 +++---
drivers/gpu/drm/i915/intel_dp.c | 25 +--
drivers/gpu/drm/i915/intel_drv.h | 14 +
drivers/gpu/drm/i915/intel_lvds.c| 12 +++
5 files changed, 46 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index d4d0c1c..45e043c 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -187,8 +187,9 @@ static bool intel_ironlake_crt_detect_hotplug(struct
drm_connector *connector)
DRM_DEBUG_KMS(pch crt adpa 0x%x, adpa);
I915_WRITE(PCH_ADPA, adpa);
- while ((I915_READ(PCH_ADPA) ADPA_CRT_HOTPLUG_FORCE_TRIGGER) != 0)
- ;
+ if (wait_for((I915_READ(PCH_ADPA) ADPA_CRT_HOTPLUG_FORCE_TRIGGER) ==
0,
+1000, 1))
+ DRM_DEBUG_DRIVER(timed out waiting for FORCE_TRIGGER);
if (HAS_PCH_CPT(dev)) {
I915_WRITE(PCH_ADPA, temp);
@@ -239,17 +240,13 @@ static bool intel_crt_detect_hotplug(struct drm_connector
*connector)
hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
for (i = 0; i tries ; i++) {
- unsigned long timeout;
/* turn on the FORCE_DETECT */
I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
- timeout = jiffies + msecs_to_jiffies(1000);
/* wait for FORCE_DETECT to go off */
- do {
- if (!(I915_READ(PORT_HOTPLUG_EN)
- CRT_HOTPLUG_FORCE_DETECT))
- break;
- msleep(1);
- } while (time_after(timeout, jiffies));
+ if (wait_for((I915_READ(PORT_HOTPLUG_EN)
+ CRT_HOTPLUG_FORCE_DETECT) == 0,
+1000, 1))
+ DRM_DEBUG_DRIVER(timed out waiting for FORCE_DETECT to
go off);
}
stat = I915_READ(PORT_HOTPLUG_STAT);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5cae58a..958d9aa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1034,7 +1034,6 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc,
unsigned long interval)
void i8xx_disable_fbc(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- unsigned long timeout = jiffies + msecs_to_jiffies(1);
u32 fbc_ctl;
if (!I915_HAS_FBC(dev))
@@ -1049,12 +1048,9 @@ void i8xx_disable_fbc(struct drm_device *dev)
I915_WRITE(FBC_CONTROL, fbc_ctl);
/* Wait for compressing bit to clear */
- while (I915_READ(FBC_STATUS) FBC_STAT_COMPRESSING) {
- if (time_after(jiffies, timeout)) {
- DRM_DEBUG_DRIVER(FBC idle timed out\n);
- break;
- }
- ; /* do nothing */
+ if (wait_for((I915_READ(FBC_STATUS) FBC_STAT_COMPRESSING) == 0, 10,
0)) {
+ DRM_DEBUG_KMS(FBC idle timed out\n);
+ return;
}
intel_wait_for_vblank(dev);
@@ -1845,7 +1841,6 @@ static int ironlake_crtc_dpms(struct drm_crtc *crtc, int
mode)
int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
int trans_dpll_sel = (pipe == 0) ? 0 : 1;
u32 temp;
- int n;
u32 pipe_bpc;
temp = I915_READ(pipeconf_reg);
@@ -2040,9 +2035,8 @@ static int ironlake_crtc_dpms(struct drm_crtc *crtc, int
mode)
temp |= pipe_bpc;
I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
- while ((I915_READ(transconf_reg) TRANS_STATE_ENABLE)
== 0)
- ;
-
+ if (wait_for(I915_READ(transconf_reg)
TRANS_STATE_ENABLE, 10, 0))
+ DRM_DEBUG_KMS(failed to enable transcoder\n);
}
intel_crtc_load_lut(crtc);
@@ -2074,19 +2068,9 @@ static int ironlake_crtc_dpms(struct drm_crtc *crtc, int
mode)
if (temp PIPEACONF_ENABLE) {
I915_WRITE(pipeconf_reg, temp ~PIPEACONF_ENABLE);
- n = 0;
/* wait for cpu pipe off, pipe state */
- while (I915_READ(pipeconf_reg) I965_PIPECONF_ACTIVE) {
- n++;
- if (n 60) {
- udelay(500);
-
[Intel-gfx] [PATCH] drm/i915: FBC is updated within set_base() so remove second call in mode_set()
The FBC is dependent upon a few details of the framebuffer so it is required to be updated within set_base(), so remove the redundant call from mode_set(). Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- drivers/gpu/drm/i915/intel_display.c |3 --- 1 files changed, 0 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 958d9aa..c920508 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4041,9 +4041,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, /* Flush the plane changes */ ret = intel_pipe_set_base(crtc, x, y, old_fb); - if ((IS_I965G(dev) || plane == 0)) - intel_update_fbc(crtc, crtc-mode); - intel_update_watermarks(dev); drm_vblank_post_modeset(dev, pipe); -- 1.7.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [stable] [PATCH 2/4] drm/i915: Enable panel fitting for eDP
On Thu, Jul 29, 2010 at 10:58:53AM +1000, Dave Airlie wrote:
did this patch go anywhere?
It's now upstream in Linus's tree.
thanks,
greg k-h
On Mon, Jul 19, 2010 at 6:43 PM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
From: Zhao Yakui yakui.z...@intel.com
When trying to set other display mode besides the fixed panel mode, the
panel fitting should be enabled. This is similar to LVDS.
Signed-off-by: Zhao Yakui yakui.z...@intel.com
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: sta...@kernel.org
---
drivers/gpu/drm/i915/intel_display.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8359c50..77ae44e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1888,7 +1888,8 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc,
int mode)
}
/* Enable panel fitting for LVDS */
- if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
+ || HAS_eDP || intel_pch_has_edp(crtc)) {
temp = I915_READ(pf_ctl_reg);
I915_WRITE(pf_ctl_reg, temp | PF_ENABLE |
PF_FILTER_MED_3x3);
--
1.7.1
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___
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http://linux.kernel.org/mailman/listinfo/stable
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Re: [Intel-gfx] [PATCH] drm/i915: Implement fair lru eviction across both rings. (v2)
On Fri, Aug 06, 2010 at 12:25:45PM +0100, Chris Wilson wrote:
Based in a large part upon Daniel Vetter's implementation and adapted
for handling multiple rings in a single pass.
This should lead to better gtt usage and fixes the page-fault-of-doom
triggered. The fairness is provided by scanning through the GTT space
amalgamating space in rendering order. As soon as we have a contiguous
space in the GTT large enough for the new object (and its alignment),
evict any object which lies within that space. This should keep more
objects resident in the GTT.
Doing throughput testing on a PineView machine with cairo-perf-trace
indicates that there is very little difference with the new LRU scan,
perhaps a small improvement... Except oddly for the poppler trace.
Reference:
Bug 15911 - Intermittent X crash (freeze)
https://bugzilla.kernel.org/show_bug.cgi?id=15911
Bug 20152 - cannot view JPG in firefox when running UXA
https://bugs.freedesktop.org/show_bug.cgi?id=20152
Bug 24369 - Hang when scrolling firefox page with window in front
https://bugs.freedesktop.org/show_bug.cgi?id=24369
Bug 28478 - Intermittent graphics lockups due to overflow/loop
https://bugs.freedesktop.org/show_bug.cgi?id=28478
v2: Attempt to clarify the logic and order of eviction through the use
of comments and macros.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Daniel Vetter dan...@ffwll.ch
One small nitpick below.
int
-i915_gem_evict_something(struct drm_device *dev,
- int min_size, unsigned alignment)
+i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned
alignment)
{
[cut]
+ return i915_gem_evict_everything(dev);
I think this should be equivalent to
return -ENOMEM;
(minus wasting less cpu, of course ;) But that's easily fixable in another
patch (and probably better for bisection). Otherwise the patch looks good,
besides that my gut still thinks that One Scan to Rule Them All is
overkill. But that's simply bike-shedding, hence:
Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch
--
Daniel Vetter
Mail: dan...@ffwll.ch
Mobile: +41 (0)79 365 57 48
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Re: [Intel-gfx] [PATCH] drm/i915: Implement fair lru eviction across both rings. (v2)
On Fri, 6 Aug 2010 20:58:30 +0200, Daniel Vetter dan...@ffwll.ch wrote: On Fri, Aug 06, 2010 at 12:25:45PM +0100, Chris Wilson wrote: + return i915_gem_evict_everything(dev); I think this should be equivalent to return -ENOMEM; Yes, we could return -ENOSPC and then do_execbuffer() would unpin and call i915_gem_evict_everything() before retrying. I'm happy for anybody to paint it a completely different colour just as soon as it is heading upstream. :) -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Append the object onto the inactive list on binding.
In order to properly track bound objects, they need to exist on one of the inactive/active lists or be pinned. As this is a requirement, do the work inside i915_gem_bind_to_gtt() rather than dotted around the callsites. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem.c |9 - 1 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 63251c9..69753bd 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1159,8 +1159,6 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) if (ret) goto unlock; - list_add_tail(obj_priv-list, dev_priv-mm.inactive_list); - ret = i915_gem_object_set_to_gtt_domain(obj, write); if (ret) goto unlock; @@ -1416,7 +1414,6 @@ i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, mutex_unlock(dev-struct_mutex); return ret; } - list_add_tail(obj_priv-list, dev_priv-mm.inactive_list); } drm_gem_object_unreference(obj); @@ -2517,6 +2514,9 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) atomic_inc(dev-gtt_count); atomic_add(obj-size, dev-gtt_memory); + /* keep track of bounds object by adding it to the inactive list */ + list_add_tail(obj_priv-list, dev_priv-mm.inactive_list); + /* Assert that the object is not currently in any GPU domain. As it * wasn't in the GTT, there shouldn't be any way it could have been in * a GPU cache @@ -4017,8 +4017,7 @@ i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) atomic_inc(dev-pin_count); atomic_add(obj-size, dev-pin_memory); if (!obj_priv-active - (obj-write_domain I915_GEM_GPU_DOMAINS) == 0 - !list_empty(obj_priv-list)) + (obj-write_domain I915_GEM_GPU_DOMAINS) == 0) list_del_init(obj_priv-list); } i915_verify_inactive(dev, __FILE__, __LINE__); -- 1.7.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] SVDO properties patchset
On Wed, 4 Aug 2010 13:50:22 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: This patchset touches virtually all of i915/intel*.c simply to subclass encoders and connectors, then cleans up intel_sdvo in order to add a few more TV properties. Applied to for-linus. It's early, let's get this cleanup (and a couple fixes!) in this cycle. pgpZpVZEFpkvw.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Only emit flushes on active rings.
On Wed, 4 Aug 2010 13:55:32 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: This avoids the excess flush and requests on idle rings (and spamming the debug log ;-) Applied to for-linus. pgpX8IaVxLdZK.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Kill the active list spinlock
On Wed, 4 Aug 2010 14:09:45 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: This spinlock only served debugging purposes in a time when we could not be sure of the mutex ever being released upon a GPU hang. As we now should be able rely on hangcheck to do the job for us (and that error reporting should not itself require the struct mutex) we can kill the incomplete and misleading attempt at protection. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk So, when am I getting hangcheck resets on Ironlake? Hmm? But yeah, this was a hack during initial bringup of GEM and I'll be glad to see it go away... once you rebase so it doesn't conflict. pgpVq8hin3dS5.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: report all active objects as busy
On Wed, 4 Aug 2010 21:11:13 +0200, Daniel Vetter dan...@ffwll.ch wrote: On Wed, Aug 04, 2010 at 08:57:26PM +0200, Daniel Vetter wrote: On Wed, Aug 04, 2010 at 03:36:30PM +0100, Chris Wilson wrote: Incorporates a similar patch by Daniel Vetter, the alteration being to report the current busy state after retiring. Woot, nice idea to exactly preserve the semantics of the old implementation. /me bangs the head against the wall for not coming up with this myself Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch Chris thought that given how much his patch looks like mine, a s-o-b is more appropriated: Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch Very nice, I suspect this will resolve the issues I think I was seeing with the last version. Applied to for-linus. pgp3tSNXUNoSd.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Emit a backtrace if we attempt to rebind a pinned buffer
On Wed, 4 Aug 2010 12:37:41 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: This debugging trace was useful for finding the fbcon regression on i965, and it may prove useful again in future. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Applied to for-linus. pgpZZLQVEkKgE.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Disable FDI link before retraining.
On Fri, 06 Aug 2010 14:21:59 -0700, Eric Anholt e...@anholt.net wrote: On Tue, 3 Aug 2010 08:12:12 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: At the moment, we have a habit of occasionally performing a double dpms on. This confuses the FDI link training performed on a dpms on as we can only adjust the settings whilst the link is disabled and the second attempt at training fails. A simple defensive workaround is to always disable the link prior to adjustment and re-enabling on dpms on. With the drm fix to not re-dpms the crtc, is this one still needed? No. I had to disable both this and Dave Airlie's double dpms defense, but with the drm crtc dpms fix this patch is no longer required. -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Kill the active list spinlock
On Fri, 06 Aug 2010 14:41:02 -0700, Eric Anholt e...@anholt.net wrote: On Wed, 4 Aug 2010 14:09:45 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: This spinlock only served debugging purposes in a time when we could not be sure of the mutex ever being released upon a GPU hang. As we now should be able rely on hangcheck to do the job for us (and that error reporting should not itself require the struct mutex) we can kill the incomplete and misleading attempt at protection. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk So, when am I getting hangcheck resets on Ironlake? Hmm? I suppose you'll want a more sophisticated watchdog using GPU timers, as well ;-) Yes, we should sort out the reset bits for ILK and the rest. -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] Intel 82Q35 problem
Hi,
Via a Fedora mailing list I was redirected to this list to post my
problem.
I have a problem with an IBM point-of-sale system with an Intel 82Q35
graphics chipset that does not work in RHEL6/F13, but that does work
fine on SLED 11 (older software). OpenSUSE 11.3 seems to face the
same problem. My system has a 15 display attached and also a VGA
port for a second display (to which I have connected a monitor now,
to see what happens).
This is the dmesg output on F13 with my comment inserted:
[...]
usb 1-5.2: new full speed USB device using ehci_hcd and address 3
usb 1-5.2: New USB device found, idVendor=05ba, idProduct=000a
usb 1-5.2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
usb 1-5.2: Product: U.are.U® 4500 Fingerprint Reader
usb 1-5.2: Manufacturer: DigitalPersona, Inc.
usb 1-5.2: SerialNumber: {3740B292-0CE7-0C45-BFC2-5053D2C76391}
fbcon: inteldrmfb (fb0) is primary device
## HERE THE CONSOLE SWITCHES FROM PRIMARY TO SECONDARY DISPLAY !!! ##
Console: switching to colour frame buffer device 160x64
fb0: inteldrmfb frame buffer device
registered panic notifier
No ACPI video bus found
[drm] Initialized i915 1.6.0 20080730 for :00:02.0 on minor 0
[...]
So, at the point of the comment, the primary display becomes black
and from then on all output is redirected to the secondary display,
including subsequent X sessions.
In the dmesg output I also see:
[drm] set up 7M of stolen space
[drm:intel_init_bios] *ERROR* VBT signature missing
[drm] failed to find VBIOS tables
I can avoid the video switcthing with the nomodeset kernel
parameter, but after that X can not be started at all.
Any help is appreciated.
--
--Jos Vos j...@xos.nl
--X/OS Experts in Open Systems BV | Phone: +31 20 6938364
--Amsterdam, The Netherlands| Fax: +31 20 6948204
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Re: [Intel-gfx] Small ringbuffer cleanup
On Wed, 4 Aug 2010 15:18:11 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: The goal here is to simplify the ringbuffer emission so that we can avoid the function call overhead when writing into the ringbuffer. Sweet. Applied. pgpDCN497TLQN.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Truncate the inode as well as the backing pages on purge
On Wed, 4 Aug 2010 16:22:28 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Any clarification what the impact was here? pgpJukfKw83yH.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Intel 82Q35 problem
On Fri, 06 Aug 2010 23:20:42 +0200, Jos Vos j...@xos.nl wrote: Via a Fedora mailing list I was redirected to this list to post my problem. [snip] So, at the point of the comment, the primary display becomes black and from then on all output is redirected to the secondary display, including subsequent X sessions. In the dmesg output I also see: [drm] set up 7M of stolen space [drm:intel_init_bios] *ERROR* VBT signature missing [drm] failed to find VBIOS tables This looks like an interesting regression where KMS is unable to find the modes for the panel. Hmm, is it a panel, or another external display? I apologise for redirecting you again You have a bug, please can you file one on http://bugs.freedesktop.org/ under Xorg,Driver/Intel and attach the full dmesg (if you can set drm.debug=0xc on the boot command line that would be a bonus), Xorg.log [KMS], and xrandr --verbose under KMS and UMS (the older software). The first question to answer is just how UMS is able to driver the 15 display. Hopefully then what is missing in KMS will be apparent. Thanks. -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
