Re: [Intel-gfx] i915_init takes a full second of kernel init time
On Wed, 14 Dec 2011 16:38:09 -0800, Scott James Remnant key...@google.com wrote: After a little bit of digging I found: http://cgit.freedesktop.org/~ickle/linux-2.6/commit/?h=asyncid=470d6985b508466308fc4c6aec945cdbf6de39b8 -Chris I've tried this patch, but it doesn't really reduce the startup time by much, the mainline of i915_init is still taking 0.7s with the patch applied. Reverting de842eff4101 (drm/i915: Wait for LVDS panel power sequence) should get another 0.4s back if intel_lvds_enable() is still in the critical path. After that the focus looks to be upon speeding up modeset. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] xf86-video-intel: deactivate unused CRTCs
Hi everyone,
would you mind putting something along the following into xf86-video-intel?
Thanks!
Helge Bahmann
---
Deactivate unused CRTCs
Have intel_crtc_dpms actually do something and deactivate CRTCs
on demand. This allows the X-Server to actually deactivate all
unused CRTCs, avoiding the following bug scenario:
- boot system with only internal LVDS display
- start X
- attach external display
- use xrandr to turn off internal LVDS, and turn on external display
- switch to console
- switch back to X
- use xrandr to turn off external display, turn an internal LVDS
At this point X believes that internal LVDS is active, when in fact it is not
displaying any image. The root cause appears to be that X and kernel disagree
on CRTC states.
This problem is verifiable on some notebooks (e.g. ThinkPad T400) but not all.
I guess this is due to varying crtc selection logic.
---
src/intel_display.c | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/intel_display.c b/src/intel_display.c
index b6592c4..f771df8 100644
--- a/src/intel_display.c
+++ b/src/intel_display.c
@@ -324,9 +324,15 @@ mode_to_kmode(ScrnInfoPtr scrn,
}
static void
-intel_crtc_dpms(xf86CrtcPtr intel_crtc, int mode)
+intel_crtc_dpms(xf86CrtcPtr crtc, int mode)
{
-
+ struct intel_crtc *intel_crtc = crtc-driver_private;
+ struct intel_mode *modeset = intel_crtc-mode;
+ if (mode == DPMSModeOff) {
+ drmModeSetCrtc(modeset-fd, crtc_id(intel_crtc),
+ 0, 0, 0, NULL, 0,
+ NULL);
+ }
}
static Bool
--
1.7.2.5
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Re: [Intel-gfx] [PATCH 2/3] drm/i915: Force sync command ordering (Gen6+)
On Wed, Dec 14, 2011 at 19:33, Jesse Barnes jbar...@virtuousgeek.orgwrote: On Thu, 08 Dec 2011 18:35:24 -0800 Eric Anholt e...@anholt.net wrote: Since MI_FLUSH_DW exists on gen6, and keithp says we still have outstanding issues with missed blit IRQs there, I started trying it today. Two kernel branches posted at git://people.freedesktop.org/~anholt/linux/http://people.freedesktop.org/%7Eanholt/linux/ flush-dw-notify: This is the initial attempt I did with MI_FLUSH_DW with internal notify. Quickly produced missed blit IRQs. I thought this was because the notify was in parallel with the post-sync op, not synced to be after. So I reverted part of the patch and produced... Bummer, that one looks like it ought to work. On current drm-intel-next, this patch seems to be preventing missed IRQs on IVB at least. Anyone else wanna give it a try and confirm? I've only tested with Eric's blit-and-wait.c test so far. I am still hitting missed IRQs with gem_dummy_reloc_loop even with this one on IVB mobile :(. -- Eugeni Dodonov http://eugeni.dodonov.net/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Removing TV Out modes.
These modes are no longer needed or are not according to TV timing standards.
Intel PRM Vol 3 - Display Registers Updated - Section 5 TV-Out Programming /
5.2.1 Television Standards / 5.2.1.1 Timing tables
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/intel_tv.c | 122 ---
1 files changed, 0 insertions(+), 122 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 2b1fcad..1571be3 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -674,78 +674,6 @@ static const struct tv_mode tv_modes[] = {
.filter_table = filter_table,
},
{
- .name = 480p@59.94Hz,
- .clock = 107520,
- .refresh= 59940,
- .oversample = TV_OVERSAMPLE_4X,
- .component_only = 1,
-
- .hsync_end = 64, .hblank_end = 122,
- .hblank_start = 842, .htotal = 857,
-
- .progressive= true, .trilevel_sync = false,
-
- .vsync_start_f1 = 12, .vsync_start_f2 = 12,
- .vsync_len = 12,
-
- .veq_ena= false,
-
- .vi_end_f1 = 44, .vi_end_f2 = 44,
- .nbr_end= 479,
-
- .burst_ena = false,
-
- .filter_table = filter_table,
- },
- {
- .name = 480p@60Hz,
- .clock = 107520,
- .refresh= 6,
- .oversample = TV_OVERSAMPLE_4X,
- .component_only = 1,
-
- .hsync_end = 64, .hblank_end = 122,
- .hblank_start = 842, .htotal = 856,
-
- .progressive= true, .trilevel_sync = false,
-
- .vsync_start_f1 = 12, .vsync_start_f2 = 12,
- .vsync_len = 12,
-
- .veq_ena= false,
-
- .vi_end_f1 = 44, .vi_end_f2 = 44,
- .nbr_end= 479,
-
- .burst_ena = false,
-
- .filter_table = filter_table,
- },
- {
- .name = 576p,
- .clock = 107520,
- .refresh= 5,
- .oversample = TV_OVERSAMPLE_4X,
- .component_only = 1,
-
- .hsync_end = 64, .hblank_end = 139,
- .hblank_start = 859, .htotal = 863,
-
- .progressive= true, .trilevel_sync = false,
-
- .vsync_start_f1 = 10, .vsync_start_f2 = 10,
- .vsync_len = 10,
-
- .veq_ena= false,
-
- .vi_end_f1 = 48, .vi_end_f2 = 48,
- .nbr_end= 575,
-
- .burst_ena = false,
-
- .filter_table = filter_table,
- },
- {
.name = 720p@60Hz,
.clock = 148800,
.refresh= 6,
@@ -770,30 +698,6 @@ static const struct tv_mode tv_modes[] = {
.filter_table = filter_table,
},
{
- .name = 720p@59.94Hz,
- .clock = 148800,
- .refresh= 59940,
- .oversample = TV_OVERSAMPLE_2X,
- .component_only = 1,
-
- .hsync_end = 80, .hblank_end = 300,
- .hblank_start = 1580, .htotal = 1651,
-
- .progressive= true, .trilevel_sync = true,
-
- .vsync_start_f1 = 10, .vsync_start_f2 = 10,
- .vsync_len = 10,
-
- .veq_ena= false,
-
- .vi_end_f1 = 29, .vi_end_f2 = 29,
- .nbr_end= 719,
-
- .burst_ena = false,
-
- .filter_table = filter_table,
- },
- {
.name = 720p@50Hz,
.clock = 148800,
.refresh= 5,
@@ -870,32 +774,6 @@ static const struct tv_mode tv_modes[] = {
.filter_table = filter_table,
},
- {
- .name = 1080i@59.94Hz,
- .clock = 148800,
- .refresh= 29970,
- .oversample = TV_OVERSAMPLE_2X,
- .component_only = 1,
-
- .hsync_end = 88, .hblank_end = 235,
- .hblank_start = 2155, .htotal = 2201,
-
-
[Intel-gfx] [PATCH 2/2] drm/i915: Adding 1080p modes to our TV Out mode list.
Adding 1080p supported modes according to new PRM version which is
internal for now.
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/intel_tv.c | 72 +++
1 files changed, 72 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 1571be3..cfb44f4 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -774,6 +774,78 @@ static const struct tv_mode tv_modes[] = {
.filter_table = filter_table,
},
+ {
+ .name = 1080p@30Hz,
+ .clock = 148800,
+ .refresh= 3,
+ .oversample = TV_OVERSAMPLE_2X,
+ .component_only = 1,
+
+ .hsync_end = 88, .hblank_end = 235,
+ .hblank_start = 2155, .htotal = 2199,
+
+ .progressive= true, .trilevel_sync = true,
+
+ .vsync_start_f1 = 8,.vsync_start_f2 = 8,
+ .vsync_len = 10,
+
+ .veq_ena= false,
+
+ .vi_end_f1 = 44, .vi_end_f2 = 44,
+ .nbr_end= 1079,
+
+ .burst_ena = false,
+
+ .filter_table = filter_table,
+ },
+ {
+ .name = 1080p@50Hz,
+ .clock = 148800,
+ .refresh= 5,
+ .oversample = TV_OVERSAMPLE_2X,
+ .component_only = 1,
+
+ .hsync_end = 88, .hblank_end = 235,
+ .hblank_start = 2155, .htotal = 2639,
+
+ .progressive= true, .trilevel_sync = true,
+
+ .vsync_start_f1 = 8,.vsync_start_f2 = 8,
+ .vsync_len = 10,
+
+ .veq_ena= false,
+
+ .vi_end_f1 = 44, .vi_end_f2 = 44,
+ .nbr_end= 1079,
+
+ .burst_ena = false,
+
+ .filter_table = filter_table,
+ },
+ {
+ .name = 1080p@60Hz,
+ .clock = 148800,
+ .refresh= 6,
+ .oversample = TV_OVERSAMPLE_2X,
+ .component_only = 1,
+
+ .hsync_end = 88, .hblank_end = 235,
+ .hblank_start = 2155, .htotal = 2199,
+
+ .progressive= true, .trilevel_sync = true,
+
+ .vsync_start_f1 = 8,.vsync_start_f2 = 8,
+ .vsync_len = 10,
+
+ .veq_ena= false,
+
+ .vi_end_f1 = 44, .vi_end_f2 = 44,
+ .nbr_end= 1079,
+
+ .burst_ena = false,
+
+ .filter_table = filter_table,
+ },
};
static struct intel_tv *enc_to_intel_tv(struct drm_encoder *encoder)
--
1.7.7.4
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Re: [Intel-gfx] i915_init takes a full second of kernel init time
On Thu, 15 Dec 2011 10:38:16 +, Chris Wilson ch...@chris-wilson.co.uk wrote: Reverting de842eff4101 (drm/i915: Wait for LVDS panel power sequence) should get another 0.4s back if intel_lvds_enable() is still in the critical path. After that the focus looks to be upon speeding up modeset. *not* doing modeset for LVDS/eDP is the key here -- the panel is probably already running, and all we need to do is change the scaling parameters, which (on new hardware) doesn't require a full mode set. I worked with vorlon to investigate what this would take and got pretty far down the path; the big missing piece is that we have to have a valid scanout buffer for the whole setup sequence. -- keith.pack...@intel.com pgpx6kxVcEn10.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Install a backup timer-tick when waiting on a request
As we continue to struggle to unravel the mysteries of sending a seqno
along with notification interrupt from the GPU to the CPU, fallback to
polling the seqno. We know that the seqno write eventually becomes
visible to the CPU as we find the seqno value has been updated during
hangcheck, so this method simply runs a hangcheck much faster whilst
we are waiting for a request to finish.
Optimistically such waits (of the CPU waiting for the GPU to complete)
are rare and complete quickly, and we can migrate most to using semaphores.
Or in other words: yes, this is a large amount of duct-tape.
For testing, set i915.irq_notify=3
References: https://bugs.freedesktop.org/show_bug.cgi?id=38862
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
This is more or less debugging code that provides a workaround for the
problems we have so far encountered with the IRQ/seqno race. Even after
we find the correct solution, having an option to fallback to polling
may help debug other problems (for example it would have been useful
during the gen3 lost irqs) and so is worth supporting.
The only question is whether we actually enable polling by default.
Eugeni's initial powermeter readings suggested that it had no noticeable
impact, but we need confirmation to be sure. And the other question is
whether the 1ms poll interval will lead to micro-stuttering and
less-than-ideal performance.
-Chris
---
drivers/gpu/drm/i915/i915_drv.c |8 ++
drivers/gpu/drm/i915/i915_drv.h |4 +
drivers/gpu/drm/i915/i915_gem.c |8 +-
drivers/gpu/drm/i915/i915_irq.c |4 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 190 +--
drivers/gpu/drm/i915/intel_ringbuffer.h |9 +-
6 files changed, 130 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 15bfa91..36e2938 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -103,6 +103,14 @@ MODULE_PARM_DESC(enable_hangcheck,
WARNING: Disabling this can cause system wide hangs.
(default: true));
+unsigned int i915_irq_notify __read_mostly = I915_IRQ_NOTIFY_INTERRUPT;
+module_param_named(irq_notify, i915_irq_notify, int, 0600);
+MODULE_PARM_DESC(irq_notify,
+ Choose the request notification method, can be any
+ combination of irq (0x1) or polling (0x2).
+ WARNING: Selecting no method will result in busy-waits.
+ (default: is to use irq only));
+
static struct drm_driver driver;
extern int intel_agp_enabled;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4a9c1b9..49fa8e9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1006,6 +1006,10 @@ extern unsigned int i915_enable_rc6 __read_mostly;
extern int i915_enable_fbc __read_mostly;
extern bool i915_enable_hangcheck __read_mostly;
+extern unsigned int i915_irq_notify __read_mostly;
+#define I915_IRQ_NOTIFY_INTERRUPT 0x1
+#define I915_IRQ_NOTIFY_POLL 0x2
+
extern int i915_suspend(struct drm_device *dev, pm_message_t state);
extern int i915_resume(struct drm_device *dev);
extern int i915_master_create(struct drm_device *dev, struct drm_master
*master);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 60ff1b6..8eadcc5 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1995,7 +1995,7 @@ i915_wait_request(struct intel_ring_buffer *ring,
trace_i915_gem_request_wait_begin(ring, seqno);
ring-waiting_seqno = seqno;
- if (ring-irq_get(ring)) {
+ if (intel_ring_get_irq(ring)) {
if (dev_priv-mm.interruptible)
ret = wait_event_interruptible(ring-irq_queue,
i915_seqno_passed(ring-get_seqno(ring), seqno)
@@ -2005,7 +2005,7 @@ i915_wait_request(struct intel_ring_buffer *ring,
i915_seqno_passed(ring-get_seqno(ring), seqno)
||
atomic_read(dev_priv-mm.wedged));
- ring-irq_put(ring);
+ intel_ring_put_irq(ring);
} else if (wait_for(i915_seqno_passed(ring-get_seqno(ring),
seqno) ||
atomic_read(dev_priv-mm.wedged), 3000))
@@ -3306,11 +3306,11 @@ i915_gem_ring_throttle(struct drm_device *dev, struct
drm_file *file)
* generation is designed to be run atomically and so is
* lockless.
*/
- if (ring-irq_get(ring)) {
+ if (intel_ring_get_irq(ring)) {
ret = wait_event_interruptible(ring-irq_queue,
[Intel-gfx] [PATCH 1/3] drm/i915: split 9xx refclk sdvo tv code out
Makes the mode set routine a little cleaner and easier to extend.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 74 +-
1 files changed, 46 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e77a863..0e2dd57 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4798,6 +4798,48 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc
*crtc,
return display_bpc != bpc;
}
+static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
+{
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ int refclk;
+
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
+ intel_panel_use_ssc(dev_priv) num_connectors 2) {
+ refclk = dev_priv-lvds_ssc_freq * 1000;
+ DRM_DEBUG_KMS(using SSC reference clock of %d MHz\n,
+ refclk / 1000);
+ } else if (!IS_GEN2(dev)) {
+ refclk = 96000;
+ } else {
+ refclk = 48000;
+ }
+
+ return refclk;
+}
+
+static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
+ intel_clock_t *clock)
+{
+ /* SDVO TV has fixed PLL values depend on its clock range,
+ this mirrors vbios setting. */
+ if (adjusted_mode-clock = 10
+adjusted_mode-clock 140500) {
+ clock-p1 = 2;
+ clock-p2 = 10;
+ clock-n = 3;
+ clock-m1 = 16;
+ clock-m2 = 8;
+ } else if (adjusted_mode-clock = 140500
+ adjusted_mode-clock = 20) {
+ clock-p1 = 1;
+ clock-p2 = 10;
+ clock-n = 6;
+ clock-m1 = 12;
+ clock-m2 = 8;
+ }
+}
+
static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode,
@@ -4852,15 +4894,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
num_connectors++;
}
- if (is_lvds intel_panel_use_ssc(dev_priv) num_connectors 2) {
- refclk = dev_priv-lvds_ssc_freq * 1000;
- DRM_DEBUG_KMS(using SSC reference clock of %d MHz\n,
- refclk / 1000);
- } else if (!IS_GEN2(dev)) {
- refclk = 96000;
- } else {
- refclk = 48000;
- }
+ refclk = i9xx_get_refclk(crtc, num_connectors);
/*
* Returns a set of divisors for the desired target clock with the given
@@ -4894,25 +4928,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
has_reduced_clock = 0;
}
}
- /* SDVO TV has fixed PLL values depend on its clock range,
- this mirrors vbios setting. */
- if (is_sdvo is_tv) {
- if (adjusted_mode-clock = 10
-adjusted_mode-clock 140500) {
- clock.p1 = 2;
- clock.p2 = 10;
- clock.n = 3;
- clock.m1 = 16;
- clock.m2 = 8;
- } else if (adjusted_mode-clock = 140500
- adjusted_mode-clock = 20) {
- clock.p1 = 1;
- clock.p2 = 10;
- clock.n = 6;
- clock.m1 = 12;
- clock.m2 = 8;
- }
- }
+
+ if (is_sdvo is_tv)
+ i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
if (IS_PINEVIEW(dev)) {
fp = (1 clock.n) 16 | clock.m1 8 | clock.m2;
--
1.7.4.1
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[Intel-gfx] [PATCH 2/3] drm/i915: split out pll divider code
This cleans up the mode set path a little further, making it easier to
extend for future platforms.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 62 ++
1 files changed, 40 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 0e2dd57..b08089c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4840,6 +4840,40 @@ static void i9xx_adjust_sdvo_tv_clock(struct
drm_display_mode *adjusted_mode,
}
}
+static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
+intel_clock_t *clock,
+intel_clock_t *reduced_clock)
+{
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc-pipe;
+ u32 fp, fp2;
+
+ if (IS_PINEVIEW(dev)) {
+ fp = (1 clock-n) 16 | clock-m1 8 | clock-m2;
+ if (reduced_clock)
+ fp2 = (1 reduced_clock-n) 16 |
+ reduced_clock-m1 8 | reduced_clock-m2;
+ } else {
+ fp = clock-n 16 | clock-m1 8 | clock-m2;
+ if (reduced_clock)
+ fp2 = reduced_clock-n 16 | reduced_clock-m1 8 |
+ reduced_clock-m2;
+ }
+
+ I915_WRITE(FP0(pipe), fp);
+
+ intel_crtc-lowfreq_avail = false;
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
+ reduced_clock i915_powersave) {
+ I915_WRITE(FP1(pipe), fp2);
+ intel_crtc-lowfreq_avail = true;
+ } else {
+ I915_WRITE(FP1(pipe), fp);
+ }
+}
+
static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode,
@@ -4853,7 +4887,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
int plane = intel_crtc-plane;
int refclk, num_connectors = 0;
intel_clock_t clock, reduced_clock;
- u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
+ u32 dpll, dspcntr, pipeconf;
bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
struct drm_mode_config *mode_config = dev-mode_config;
@@ -4932,17 +4966,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
if (is_sdvo is_tv)
i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
- if (IS_PINEVIEW(dev)) {
- fp = (1 clock.n) 16 | clock.m1 8 | clock.m2;
- if (has_reduced_clock)
- fp2 = (1 reduced_clock.n) 16 |
- reduced_clock.m1 8 | reduced_clock.m2;
- } else {
- fp = clock.n 16 | clock.m1 8 | clock.m2;
- if (has_reduced_clock)
- fp2 = reduced_clock.n 16 | reduced_clock.m1 8 |
- reduced_clock.m2;
- }
+ i9xx_update_pll_dividers(crtc, clock, has_reduced_clock ?
+reduced_clock : NULL);
dpll = DPLL_VGA_MODE_DIS;
@@ -5042,7 +5067,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
DRM_DEBUG_KMS(Mode for pipe %c:\n, pipe == 0 ? 'A' : 'B');
drm_mode_debug_printmodeline(mode);
- I915_WRITE(FP0(pipe), fp);
I915_WRITE(DPLL(pipe), dpll ~DPLL_VCO_ENABLE);
POSTING_READ(DPLL(pipe));
@@ -5129,17 +5153,11 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
I915_WRITE(DPLL(pipe), dpll);
}
- intel_crtc-lowfreq_avail = false;
- if (is_lvds has_reduced_clock i915_powersave) {
- I915_WRITE(FP1(pipe), fp2);
- intel_crtc-lowfreq_avail = true;
- if (HAS_PIPE_CXSR(dev)) {
+ if (HAS_PIPE_CXSR(dev)) {
+ if (intel_crtc-lowfreq_avail) {
DRM_DEBUG_KMS(enabling CxSR downclocking\n);
pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
- }
- } else {
- I915_WRITE(FP1(pipe), fp);
- if (HAS_PIPE_CXSR(dev)) {
+ } else {
DRM_DEBUG_KMS(disabling CxSR downclocking\n);
pipeconf = ~PIPECONF_CXSR_DOWNCLOCK;
}
--
1.7.4.1
___
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[Intel-gfx] [PATCH 3/3] drm/i915: split out DPLL update code from i9xx_crtc_mode_set
More i9xx mode set cleanups, further simplifying the mode set path and
making it easier to extend.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 402 --
1 files changed, 236 insertions(+), 166 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index b08089c..0eff163 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4848,7 +4848,7 @@ static void i9xx_update_pll_dividers(struct drm_crtc
*crtc,
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc-pipe;
- u32 fp, fp2;
+ u32 fp, fp2 = 0;
if (IS_PINEVIEW(dev)) {
fp = (1 clock-n) 16 | clock-m1 8 | clock-m2;
@@ -4874,6 +4874,233 @@ static void i9xx_update_pll_dividers(struct drm_crtc
*crtc,
}
}
+static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
+ struct drm_display_mode *adjusted_mode)
+{
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc-pipe;
+ u32 temp, lvds_sync = 0;
+
+ temp = I915_READ(LVDS);
+ temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
+ if (pipe == 1) {
+ temp |= LVDS_PIPEB_SELECT;
+ } else {
+ temp = ~LVDS_PIPEB_SELECT;
+ }
+ /* set the corresponsding LVDS_BORDER bit */
+ temp |= dev_priv-lvds_border_bits;
+ /* Set the B0-B3 data pairs corresponding to whether we're going to
+* set the DPLLs for dual-channel mode or not.
+*/
+ if (clock-p2 == 7)
+ temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
+ else
+ temp = ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
+
+ /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
+* appropriately here, but we need to look more thoroughly into how
+* panels behave in the two modes.
+*/
+ /* set the dithering flag on LVDS as needed */
+ if (INTEL_INFO(dev)-gen = 4) {
+ if (dev_priv-lvds_dither)
+ temp |= LVDS_ENABLE_DITHER;
+ else
+ temp = ~LVDS_ENABLE_DITHER;
+ }
+ if (adjusted_mode-flags DRM_MODE_FLAG_NHSYNC)
+ lvds_sync |= LVDS_HSYNC_POLARITY;
+ if (adjusted_mode-flags DRM_MODE_FLAG_NVSYNC)
+ lvds_sync |= LVDS_VSYNC_POLARITY;
+ if ((temp (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
+ != lvds_sync) {
+ char flags[2] = -+;
+ DRM_INFO(Changing LVDS panel from
+(%chsync, %cvsync) to (%chsync, %cvsync)\n,
+flags[!(temp LVDS_HSYNC_POLARITY)],
+flags[!(temp LVDS_VSYNC_POLARITY)],
+flags[!(lvds_sync LVDS_HSYNC_POLARITY)],
+flags[!(lvds_sync LVDS_VSYNC_POLARITY)]);
+ temp = ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
+ temp |= lvds_sync;
+ }
+ I915_WRITE(LVDS, temp);
+}
+
+static void i9xx_update_pll(struct drm_crtc *crtc,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode,
+ intel_clock_t *clock, intel_clock_t *reduced_clock,
+ int num_connectors)
+{
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc-pipe;
+ u32 dpll;
+ bool is_sdvo;
+
+ is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
+ intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
+
+ dpll = DPLL_VGA_MODE_DIS;
+
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
+ dpll |= DPLLB_MODE_LVDS;
+ else
+ dpll |= DPLLB_MODE_DAC_SERIAL;
+ if (is_sdvo) {
+ int pixel_multiplier =
intel_mode_get_pixel_multiplier(adjusted_mode);
+ if (pixel_multiplier 1) {
+ if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
+ dpll |= (pixel_multiplier - 1)
SDVO_MULTIPLIER_SHIFT_HIRES;
+ }
+ dpll |= DPLL_DVO_HIGH_SPEED;
+ }
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+ dpll |= DPLL_DVO_HIGH_SPEED;
+
+ /* compute bitmask from p1 value */
+ if (IS_PINEVIEW(dev))
+ dpll |= (1 (clock-p1 - 1))
DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
+ else {
+ dpll |= (1 (clock-p1 - 1)) DPLL_FPA01_P1_POST_DIV_SHIFT;
+
Re: [Intel-gfx] i915_init takes a full second of kernel init time
On Thu, Dec 15, 2011 at 2:38 AM, Chris Wilson ch...@chris-wilson.co.uk wrote: On Wed, 14 Dec 2011 16:38:09 -0800, Scott James Remnant key...@google.com wrote: After a little bit of digging I found: http://cgit.freedesktop.org/~ickle/linux-2.6/commit/?h=asyncid=470d6985b508466308fc4c6aec945cdbf6de39b8 -Chris I've tried this patch, but it doesn't really reduce the startup time by much, the mainline of i915_init is still taking 0.7s with the patch applied. Reverting de842eff4101 (drm/i915: Wait for LVDS panel power sequence) should get another 0.4s back if intel_lvds_enable() is still in the critical path. After that the focus looks to be upon speeding up modeset. This gives us a significant chunk of time back (0.5s) - what would be the downside of carrying a revert to this patch? Scott -- Scott James Remnant | Chrome OS Systems | key...@google.com | Google ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Fan running with Intel Graphics
Am 13.12.2011 22:46, schrieb Jesse Barnes: On Tue, 13 Dec 2011 22:30:42 +0100 Johannes Bauer dfnsonfsdu...@gmx.de wrote: then echo that value into the max freq file, e.g.: $ echo 400 /sys/kernel/debug/dri/0/i915_max_freq This doesn't work for joelaptop [/sys/kernel/debug/dri]: uname -a Linux joelaptop 3.0.0-14-generic #23-Ubuntu SMP Mon Nov 21 20:28:43 UTC 2011 x86_64 x86_64 x86_64 GNU/Linux Since i915_max_freq does not exist -- do I need to switch to a more recent kernel version? Yes. Try running drm-intel-next from Keith's git tree: git://people.freedesktop.org/~keithp/linux Hmmm: joelaptop [~/intel-graphics]: git pull git://people.freedesktop.org/~keithp/linux fatal: Couldn't find remote ref HEAD Is the server currently down? Can I fetch it somewhere else? Best regards, Joe ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Fan running with Intel Graphics
Am 14.12.2011 03:49, schrieb Eugeni Dodonov: But meanwhile, for better understanding what is going on with your machine, could you setup some thermal sensors and check what do they say about temperature? And also check with powertop about what is using the most power out there? Well, temperature as read by coretemp is around 60°C for the CPU, which appears to be quite high for a completely idle device. There seems to be some second sensor that I'm unable to read out which controls the fan, however. powertop seems nice -- but I have no clue on how to read it actually. Or how to get to know what power which process actually draws. I can just see that by far the application with the highest Usage is the X server (around 10 times that of the second largest, which usually is 7,1 ms/s 50,2Process/usr/bin/X :0 -auth /var/run/lightdm/root/:0 -nolisten tcp vt7 -novtswitch -background none 453,5 µs/s 19,9Interrupt [6] tasklet(softirq) But since I have no clue on how to read those values, they mean next to nothing to me. On the Idle Stats page, the CPU is 99.8% of the time in C7 mode. The frequency stats show the CPU is clocked at 800Mhz (the lowest setting). The Device Stats also mean little to me: It looks like a part of lspci (with always 100% usage), i.e. 100,0%Radio device: btusb 100,0%USB Device: usb-device-8087-0024 100,0%USB device: DW375 Bluetooth Module (Dell Computer Corp) 100,0%PCI Device: Intel Corporation 2nd Generation Core Processor Family Integrated Graphics Controller 100,0%Radio device: dell-laptop 100,0%Radio device: dell-laptop 100,0%Radio device: iwlagn 100,0%PCI Device: Intel Corporation 2nd Generation Core Processor Family DRAM Controller 100,0%PCI Device: Intel Corporation Centrino Advanced-N 6205 100,0%PCI Device: Intel Corporation 6 Series/C200 Series Chipset Family MEI Controller #1 100,0%PCI Device: O2 Micro, Inc. Device 8321 100,0%USB device: EHCI Host Controller 100,0%PCI Device: Broadcom Corporation NetXtreme BCM5761 Gigabit Ethernet PCIe 100,0%PCI Device: Intel Corporation 6 Series/C200 Series Chipset Family High Definition Audio Controller 100,0%PCI Device: Intel Corporation 6 Series/C200 Series Chipset Family USB Enhanced Host Controller #1 100,0%PCI Device: Intel Corporation 6 Series/C200 Series Chipset Family PCI Express Root Port 2 100,0%PCI Device: Intel Corporation 6 Series/C200 Series Chipset Family PCI Express Root Port 3 100,0%PCI Device: Intel Corporation 6 Series/C200 Series Chipset Family PCI Express Root Port 6 100,0%PCI Device: Intel Corporation 6 Series/C200 Series Chipset Family PCI Express Root Port 7 100,0%PCI Device: Intel Corporation 6 Series/C200 Series Chipset Family PCI Express Root Port 1 100,0%PCI Device: Intel Corporation 6 Series/C200 Series Chipset Family 6 port SATA AHCI Controller 100,0%PCI Device: O2 Micro, Inc. Device 13f7 And a few others with 0%. The Tunables I don't get at all. Some are Bad, some are Good -- but I can somehow switch how they are rated? I'm confused. Best regards, Joe ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
