On Mon, Jan 16, 2012 at 21:28, Daniel Vetter dan...@ffwll.ch wrote:
On Sun, Jan 08, 2012 at 03:01:12AM +0100, Cyril Brulebois wrote:
Eugeni Dodonov eugeni.dodo...@intel.com (07/01/2012):
This is also handled by i915_reg.h, so just reuse this trick to reduce
universe enthropy.
entropy.
On Mon, Jan 16, 2012 at 11:01:13PM +, Chris Wilson wrote:
Staring at an error state such as:
PGTBL_ER: 0x0400
Display B: Invalid tiling
fence[0] = 05001001
valid, x-tiled, pitch: 512, start: 0x0500, size: 1048576
Pinned [2]:
131072 0001 0001 P
On Mon, Jan 16, 2012 at 02:20:55PM -0800, Ben Widawsky wrote:
On 01/16/2012 01:50 PM, Daniel Vetter wrote:
On Tue, Dec 13, 2011 at 10:36:15AM -0800, Ben Widawsky wrote:
On 12/13/2011 09:22 AM, Eric Anholt wrote:
On Mon, 12 Dec 2011 19:52:08 -0800, Ben Widawskyb...@bwidawsk.net
wrote:
On Tue, Jan 17, 2012 at 07:08:09AM +0800, Wu Fengguang wrote:
On Mon, Jan 16, 2012 at 12:44:43PM -0800, Keith Packard wrote:
On Mon, 16 Jan 2012 21:26:18 +0100, Daniel Vetter dan...@ffwll.ch wrote:
Keith, does this address your concern and this patch is r-b: Keith or do
we want an
On Tue, Nov 15, 2011 at 07:47:58PM +0100, Takashi Iwai wrote:
At Fri, 11 Nov 2011 14:12:58 -0800,
Simon Que wrote:
If the firmware did not initialize the backlight PWM registers, set up a
default PWM frequency of 200 Hz. This is determined using the following
formula:
freq =
On Thu, Nov 10, 2011 at 05:50:26PM -0800, Simon Que wrote:
There is an error in i915_read_blc_pwm_ctl, where the register values
are not being copied correctly. BLC_PWM_CTL and BLC_PWM_CTL2 are
getting mixed up. This patch fixes that so that saveBLC_PWM_CTL2 and
not saveBLC_PWM_CTL is copied
On Wed, Nov 09, 2011 at 12:17:06PM -0800, Eric Anholt wrote:
On Wed, 09 Nov 2011 19:15:06 +, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Wed, 09 Nov 2011 10:57:00 -0800, Eric Anholt e...@anholt.net wrote:
On Wed, 9 Nov 2011 17:32:26 +, Chris Wilson
ch...@chris-wilson.co.uk
On Tue, Nov 08, 2011 at 11:17:34PM +, Chris Wilson wrote:
Enabling FBC is causing the BLT ring to run between 10-100x slower than
normal and frequently lockup. The interim solution is disable FBC once
more until we know why.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Iirc fbc
On Tue, Jan 17, 2012 at 10:45 AM, Keith Whitwell kei...@vmware.com wrote:
On Mon, 2012-01-16 at 21:56 +0100, Daniel Vetter wrote:
On Thu, Dec 22, 2011 at 10:23:14PM +0100, Daniel Vetter wrote:
Some decent history digging indicates that this was to be used for the
GLX_MESA_allocate_memory
On Tue, Nov 08, 2011 at 11:13:12PM +, Chris Wilson wrote:
Rather than relying on the hardware to do this correctly, we can
trivially do it ourselves.
This fixes a very reliable crash on d-i-n with all bits enabled during a
cairo-trace replay. The symptoms of the crash is that we continue
On Fri, Nov 04, 2011 at 05:03:54PM -0700, Ben Widawsky wrote:
The GTFIFODBG register gives us 3 error types when the fifo is accessed
and full. Whenever we do a forcewake_put we can check this register to
see if any of the CPU related errors occurred.
Of more interest is perhaps the bit I am
On Tue, 17 Jan 2012 11:59:27 +0100, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Nov 08, 2011 at 11:13:12PM +, Chris Wilson wrote:
Rather than relying on the hardware to do this correctly, we can
trivially do it ourselves.
This fixes a very reliable crash on d-i-n with all bits
On Thu, Nov 03, 2011 at 03:23:39PM -0700, Ben Widawsky wrote:
On Thu, 3 Nov 2011 20:19:23 +
Dave Airlie airl...@gmail.com wrote:
The solution here is to add a new flag to the call chain which gives
the
routines the information they need to possibly defer actions which may
On Tue, 17 Jan 2012 11:57:05 +0100, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Nov 08, 2011 at 11:17:34PM +, Chris Wilson wrote:
Enabling FBC is causing the BLT ring to run between 10-100x slower than
normal and frequently lockup. The interim solution is disable FBC once
more until we
On Thu, Oct 20, 2011 at 03:15:09PM -0200, Eugeni Dodonov wrote:
This is mostly similar to Ironlake, with some register changes and
additional tricks.
Jesse mentioned that it would make more sense to move those bits into
ivb-specific functions instead of making this work within ironlake ones,
On Tue, 17 Jan 2012 12:08:57 +0100, Daniel Vetter dan...@ffwll.ch wrote:
On Fri, Nov 04, 2011 at 05:03:54PM -0700, Ben Widawsky wrote:
The GTFIFODBG register gives us 3 error types when the fifo is accessed
and full. Whenever we do a forcewake_put we can check this register to
see if any of
Some decent history digging indicates that this was to be used for the
GLX_MESA_allocate_memory extension but never actually implemented for
any released i915 userspace code.
So just rip it out.
v2: Fixup the Makefile.
Acked-by: Dave Airlie airl...@gmail.com
Cc: Keith Whitwell kei...@vmware.com
On Fri, Oct 07, 2011 at 02:38:41PM -0400, Adam Jackson wrote:
Just a few things spotted in a readthrough. The DPLL disable one might
actually be a bugfix, who knows.
I've queued patches 1,25 for -next. 3 is already fixed and 4 won't be
true in the near future due to something I'm not yet
On Tue, 17 Jan 2012 11:49:53 +0100, Daniel Vetter dan...@ffwll.ch wrote:
What's the status of this patch? If you resend can you clarify the
bugzilla reference and also include a Bspec/PRM/whatever citation for
this workaround?
We don't know what it works around, nor do we have any idea if it
On Tue, Jan 17, 2012 at 08:57, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Nov 08, 2011 at 11:17:34PM +, Chris Wilson wrote:
Enabling FBC is causing the BLT ring to run between 10-100x slower than
normal and frequently lockup. The interim solution is disable FBC once
more until we
On Tue, Jan 17, 2012 at 08:58, Dave Airlie airl...@gmail.com wrote:
On Tue, Jan 17, 2012 at 10:45 AM, Keith Whitwell kei...@vmware.com
wrote:
On Mon, 2012-01-16 at 21:56 +0100, Daniel Vetter wrote:
On Thu, Dec 22, 2011 at 10:23:14PM +0100, Daniel Vetter wrote:
Some decent history
On Tue, Jan 17, 2012 at 12:16, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Tue, 17 Jan 2012 11:57:05 +0100, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Nov 08, 2011 at 11:17:34PM +, Chris Wilson wrote:
Enabling FBC is causing the BLT ring to run between 10-100x slower than
normal
On Tue, 26 Jul 2011 15:39:44 -0400
Adam Jackson a...@redhat.com wrote:
Matches the advice in the Sandybridge documentation.
Signed-off-by: Adam Jackson a...@redhat.com
---
drivers/gpu/drm/i915/intel_dp.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git
On Tue, 26 Jul 2011 15:39:44 -0400
Adam Jackson a...@redhat.com wrote:
Matches the advice in the Sandybridge documentation.
Signed-off-by: Adam Jackson a...@redhat.com
---
drivers/gpu/drm/i915/intel_dp.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git
On Tue, Jan 17, 2012 at 07:19:35AM -0800, Jesse Barnes wrote:
On Tue, 26 Jul 2011 15:39:44 -0400
Adam Jackson a...@redhat.com wrote:
Matches the advice in the Sandybridge documentation.
Signed-off-by: Adam Jackson a...@redhat.com
---
drivers/gpu/drm/i915/intel_dp.c |2 +-
1
On Tue, Jul 12, 2011 at 03:42:11PM -0700, Keith Packard wrote:
On Tue, 12 Jul 2011 17:37:59 -0400, Adam Jackson a...@redhat.com wrote:
Signed-off-by: Adam Jackson a...@redhat.com
+# define DP_DWN_STRM_PORT_TYPE_TMDS(2 1)
This could be labeled TYPE_DVI_OR_HDMI according to
On Fri, Jul 08, 2011 at 08:43:47PM +0100, Chris Wilson wrote:
Oh dear, it was all looking too good. Works fine with just one output.
Runs into a nasty race if you add a second and start unplugging things...
The issue is that when unplugging an output, userspace sees this and
appropriately
LLC is not SNB/IVB-specific, so we should check for it in a more generic
way.
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c |1 +
This adds support for querying the kernel about the LLC support in the
hardware.
In case the ioctl fails, we assume that it is present on GEN6 and GEN7.
Signed-off-by: Eugeni Dodonov eug...@dodonov.net
---
include/drm/i915_drm.h |1 +
intel/intel_bufmgr_gem.c | 12
2 files
On Tue, 17 Jan 2012 17:18:17 +0100, Daniel Vetter dan...@ffwll.ch wrote:
I've just noticed that we seem to miss this plug to fix fbc issues. Care
to resend a proper patch in case we still need this?
Also, I we could try to also disable fbc when we detect frontbuffer
rendering (and generally
This adds support for querying the kernel about the LLC support in the
hardware.
In case the ioctl fails, we assume that it is present on GEN6 and GEN7.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
include/drm/i915_drm.h |1 +
intel/intel_bufmgr_gem.c | 12
2
On Tue, Jan 17, 2012 at 14:44, Eugeni Dodonov eug...@dodonov.net wrote:
This adds support for querying the kernel about the LLC support in the
hardware.
In case the ioctl fails, we assume that it is present on GEN6 and GEN7.
Signed-off-by: Eugeni Dodonov eug...@dodonov.net
Please ignore
On Tue, 17 Jan 2012 12:22:44 +0100
Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Oct 20, 2011 at 03:15:09PM -0200, Eugeni Dodonov wrote:
This is mostly similar to Ironlake, with some register changes and
additional tricks.
Jesse mentioned that it would make more sense to move those bits
Otherwise, we are left with pretty bogus message saying that the pixel
format is not supported while leaving the details to the telepatic powers.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |3 ++-
1 files changed, 2 insertions(+), 1
On Tue, Jan 17, 2012 at 03:11:11PM -0200, Eugeni Dodonov wrote:
Otherwise, we are left with pretty bogus message saying that the pixel
format is not supported while leaving the details to the telepatic powers.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
This adds support for querying the kernel about the LLC support in the
hardware.
In case the ioctl fails, we assume that it is present on GEN6 and GEN7.
v2: fix the return code checking
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
include/drm/i915_drm.h |1 +
Otherwise, we are left with pretty bogus message saying that the pixel
format is not supported while leaving the details to the telepatic powers.
v2: use DRM_DEBUG_KMS instead of DRM_ERROR
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |3 ++-
On Tue, 17 Jan 2012 14:58:21 -0200, Eugeni Dodonov eugeni.dodo...@intel.com
wrote:
This adds support for querying the kernel about the LLC support in the
hardware.
In case the ioctl fails, we assume that it is present on GEN6 and GEN7.
This patch should probably come along with a consumer
On Tue, 17 Jan 2012 14:43:53 -0200, Eugeni Dodonov eugeni.dodo...@intel.com
wrote:
LLC is not SNB/IVB-specific, so we should check for it in a more generic
way.
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Eugeni
On Tue, 17 Jan 2012 12:50:12 +0100, Daniel Vetter daniel.vet...@ffwll.ch
wrote:
Some decent history digging indicates that this was to be used for the
GLX_MESA_allocate_memory extension but never actually implemented for
any released i915 userspace code.
So just rip it out.
v2: Fixup the
On Tue, 17 Jan 2012 11:15:31 +0100, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Jan 16, 2012 at 02:20:55PM -0800, Ben Widawsky wrote:
On 01/16/2012 01:50 PM, Daniel Vetter wrote:
On Tue, Dec 13, 2011 at 10:36:15AM -0800, Ben Widawsky wrote:
On 12/13/2011 09:22 AM, Eric Anholt wrote:
On Tue, Jan 17, 2012 at 09:35:48AM -0800, Eric Anholt wrote:
On Tue, 17 Jan 2012 12:50:12 +0100, Daniel Vetter daniel.vet...@ffwll.ch
wrote:
Some decent history digging indicates that this was to be used for the
GLX_MESA_allocate_memory extension but never actually implemented for
any
Instead of checking for CPU generation, use the libdrm-provided
I915_PARAM_HAS_LLC instead.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
src/sna/kgem.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/sna/kgem.c b/src/sna/kgem.c
index 970e462..96c5ddd
This is requried for I915_PARAM_HAS_LLC support.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
configure.ac |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/configure.ac b/configure.ac
index 63beb64..604ea6d 100644
--- a/configure.ac
+++ b/configure.ac
@@
On 01/17/2012 08:43 AM, Eugeni Dodonov wrote:
LLC is not SNB/IVB-specific, so we should check for it in a more generic
way.
Reviewed-by: Chris Wilsonch...@chris-wilson.co.uk
Reviewed-by: Daniel Vetterdaniel.vet...@ffwll.ch
Signed-off-by: Eugeni Dodonoveugeni.dodo...@intel.com
Reviewed-by:
Instead of checking for CPU generation, use the libdrm-provided
I915_PARAM_HAS_LLC instead.
v2: use a define check to verify if we have I915_PARAM_HAS_LLC.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
src/sna/kgem.c | 12
1 files changed, 12 insertions(+), 0
Hi Paulo,
sorry for not getting back you sooner... your email was here on my to do list
Could you please report this issue on bugs.freedesktop.org attaching
this xrandr verbose info and also dmesg xorg log and confs?
Also, Is it possible to test it without the AV receiver? I think you
wont see a
On Tue, 17 Jan 2012 16:16:37 -0200, Eugeni Dodonov eugeni.dodo...@intel.com
wrote:
Instead of checking for CPU generation, use the libdrm-provided
I915_PARAM_HAS_LLC instead.
v2: use a define check to verify if we have I915_PARAM_HAS_LLC.
Signed-off-by: Eugeni Dodonov
On Tue, Jan 17, 2012 at 02:43:53PM -0200, Eugeni Dodonov wrote:
LLC is not SNB/IVB-specific, so we should check for it in a more generic
way.
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Eugeni Dodonov
On Tue, Jan 17, 2012 at 18:14, Alfonso Fiore alfonso.fi...@gmail.comwrote:
Hi Angela,
I have a very similar problem!
I have Sandy Bridge (i3 2130) and a Philips 32pf9731d (coincidence?). With
my previous i3 550 I didn't have any problem.
I tried all possible resolutions over HDMI and all
On Tue, Jan 17, 2012 at 9:25 PM, Eugeni Dodonov eug...@dodonov.net wrote:
On Tue, Jan 17, 2012 at 18:14, Alfonso Fiore alfonso.fi...@gmail.comwrote:
Hi Angela,
I have a very similar problem!
I have Sandy Bridge (i3 2130) and a Philips 32pf9731d (coincidence?).
With my previous i3 550 I
On Tue, Jan 17, 2012 at 09:59:18PM +0100, Alfonso Fiore wrote:
Hi,
here is mine. Let me know if you need any other log.
Ok, your TV only reports 1080i as a mode (at least that's the only thing
your kernel can decode). The i915 driver then rejects it because it's
interlaced (we unfortunately
On Tue, Jan 17, 2012 at 10:32:33PM +0100, Angela Schmid wrote:
Hello
Thanks for helping. I added the dmesg with drm.debug=0x0e below.
I tried last month with get-edid in DOS, with the same unhappy result, see
below for actual linux.
Could you try with the following two patches which just
Hello
Over HDMI works:
1280x720@50hz 74.25 1280 1720 1760 1980 720 725 730 750 +hsync +vsync
1280x720@50hz (0xb4) 74.2MHz +HSync +VSync *current
h: width 1280 start 1720 end 1760 total 1980 skew0 clock 37.5KHz
v: height 720 start 725 end 730 total 750
On Tue, Jan 17, 2012 at 11:53:47PM +0100, Angela Schmid wrote:
Over HDMI works:
1280x720@50hz 74.25 1280 1720 1760 1980 720 725 730 750 +hsync +vsync
1280x720@50hz (0xb4) 74.2MHz +HSync +VSync *current
h: width 1280 start 1720 end 1760 total 1980 skew0 clock
On Wed, Jan 18, 2012 at 01:16:02AM +0100, CC wrote:
On Mon, Jan 16, 2012 at 5:36 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Jan 16, 2012 at 05:18:17PM +0100, CC wrote:
Hi,
I've heard that you need users having the RC6 bug.
I have the following setup:
CPU: Intel Core
On Thu, Jan 05, 2012 at 11:11:53PM +0100, Daniel Vetter wrote:
With the new ducttape of much finer quality, this seems to be no
longer necessary.
Tested on my ivb and snb machine with the usual suspects of testcases.
Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
Does what it says on the box.
Signed-off-by: Daniel Stone dan...@fooishbar.org
---
configure.ac | 14 ++
src/legacy/i810/Makefile.am |6 +-
src/legacy/i810/i810.h|4
src/legacy/i810/i810_dga.c|2 ++
src/legacy/i810/i810_driver.c |
Hello Daniel
Your TV likely sends a CEA block with some HDMI default modes set. Since
linux-3.3-rc1 (to be released in a few days) we should be able to decode that.
Can you grab the latest -linus kernel git and try that?
I wanted to remind, that the interlaced modes work with the noveau driver
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