[Intel-gfx] [ANNOUNCE] xf86-video-intel 2.19.0 [resend]
I sent this out over the weekend and never saw it arrive, so presuming the announcement was lost in transit... Release 2.19.0 (2012-04-29) === More stability fixes for UXA and support for another variant of IvyBridge. Given the severity of the stability fixes, I strongly recommend everybody to upgrade to 2.19.0. -Chris * Prevent waiting on scanlines whilst not in control of the VT and therefore whilst referencing foreign CRTC configurations. * Pixmap (and bo leak) during fallback glyph composition * Remove broken acceleration for rendering glyphs directly upon the destination pixmap, exposed by cairo-1.12.0 (and coincidentally fix another Pixmap leak upon fallback handling). * Add support for Ivy Bridge GT2 Server chipset [PCI id 0x016a] * Remove broken damage flushing with CompositeRectangles https://bugs.freedesktop.org/show_bug.cgi?id=32547 * Fix crash upon server start with multiple monitors https://bugs.freedesktop.org/show_bug.cgi?id=47395 * Fix composition issues resulting from overly aggressive Pixmap reuse https://bugs.freedesktop.org/show_bug.cgi?id=47345 Chris Wilson (229): legacy: Delete unused XF86DRI_DEVEL #define legacy: Rename XF86DRI to HAVE_DRI1 to avoid conflicts with xorg-server.h sna: Skip a tiled bo when searching the cache for a linear mmap sna: Ensure we trigger a retire for search_linear_cache sna/gen3+: Keep the vertex buffer resident between batches sna: Retain unfinished partial buffers between batches sna: Avoid reusing mmapped partial write buffers for readback meh sna: Upload the ordinary partial buffers! Revert meh sna/gen2; Initialise channel.is-opaque for fills uxa/gen3: Remove special casing of solid pictures sna/gen3: Tweak glyph rendering fast paths sna: Sort the partial buffers after stealing a write buffer sna: Discard use of inplace GTT uploads on LLC architectures sna: Revamp vmap support sna: Split storage of inactive partials sna/gen5: Help the compiler avoid an uncached read sna: Be careful not to discard the clear operation for move-region-to-cpu sna: Only discard the inplace flag for LLC partial buffers sna: Pass usage hint for creating linear buffers sna: Disable vmap on 965gm sna: Prevent backing pixmaps being created later sna: And fix compilation for last commit sna: Silence an assertion failure during shutdown sna: Align allocations with partial buffers to 64 bytes. sna: Encourage promotion of snooped CPU bo to real GPU bo sna: Fix assertion for checking inactive shadow buffers sna: Add some assertions to partial buffer list tracking sna: Flush dirty CPU damage before notifying the compositor sna/composite: Skip clipping the rectangle region against the singular clip sna/trapezoids: Ellide empty cells sna: Check for flush at the start of every WriteToClient sna: Only install the flush callback for the duration of the foriegn buffer sna: Defer the FlushCallback removal until after the next flush sna: Remove the 2-step damage flush sna/gen6: Add poor-man's linear implementation sna/gen7: Hook in the poor-man's linear gradient sna/gen5: Hook in the poor-man's linear gradient sna/gen4: Hook in the poor-man's linear gradient sna/gen2: Fix transformation of linear gradients sna: Restore checking for all-clipped-out for CompositeRectangles sna: Avoid recursive calls to kgem_retire_partials() sna: Convolution filter fixes sna: Do not reset partial buffers if they are not attached to the current batch sna/gen2+: Prefer not to fallback if the source is busy sna/dri: Use a counter for the number of DRI drawables attached to a pixmap sna: Becareful not to reduce operators for superluminal colors sna: Preserve the offset alignment when trimming unused rows from partials sna: Discard unbound partial buffers sna: Add some assertions around pixmap creation for render operations sna: Tidy marking pixmap-clear for CompositeRectangles sna/gen2+: Use the reduced operator from CompositeRectangles intel: Fix typo s/asert/assert/ sna: Mark the pixmap for writing when creating the screen resources sna: Force the creation of a backing pixmap for scanout sna: Avoid NULL deference in DBG sna: Fix reversed logic for CREATE_NO_RETIRE sna: Fix handling of large glyphs following large and shared buffer work sna/gen6: Replace the memset with explict initialisation sna/traps: Unroll insertion sort sna/traps: Fix the initialisation of the error term for vertical mono edges sna: Emit a INFO when compiled with debugging enabled sna/traps: Remove some dead code sna/dri: Only delivered a delayed flip if the drawable is still on the root sna/traps: Apply
Re: [Intel-gfx] [PATCH] drm/i915: Only enable IPS polling for gen5
On Mon, 30 Apr 2012 19:35:02 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
On SandyBridge IPS was entirely implemented in hardware and not reliant
on the driver monitoring power consumption and feeding back desired run
states, so the hardware is able to adapt quicker and more flexibly. Which
is a huge relief for us as we no longer have to carry empirically
derived magic algorithms.
Yet despite the advance in technology, the driver was still doing its
IPS polling on all machines. Restrict it to the only supported hardware,
Clarkdale/Arrandale.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_debugfs.c |3 +++
drivers/gpu/drm/i915/i915_dma.c | 15 ++-
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 1ff6ec7..b9bd9e8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1212,6 +1212,9 @@ static int i915_emon_status(struct seq_file *m, void
*unused)
unsigned long temp, chipset, gfx;
int ret;
+ if (!IS_GEN5(dev))
+ return -ENODEV;
+
ret = mutex_lock_interruptible(dev-struct_mutex);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 4c01a47..3d03f3a 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1527,6 +1527,9 @@ void i915_update_gfx_val(struct drm_i915_private
*dev_priv)
unsigned long diffms;
u32 count;
+ if (dev_priv-info-gen != 5)
+ return;
+
getrawmonotonic(now);
diff1 = timespec_sub(now, dev_priv-last_time2);
Looks ok, but I think just update_gfx_val is called in the idle
routine? The other isn't I think...
@@ -1966,12 +1969,14 @@ int i915_driver_load(struct drm_device *dev, unsigned
long flags)
setup_timer(dev_priv-hangcheck_timer, i915_hangcheck_elapsed,
(unsigned long) dev);
- spin_lock(mchdev_lock);
- i915_mch_dev = dev_priv;
- dev_priv-mchdev_lock = mchdev_lock;
- spin_unlock(mchdev_lock);
+ if (IS_GEN5(dev)) {
+ spin_lock(mchdev_lock);
+ i915_mch_dev = dev_priv;
+ dev_priv-mchdev_lock = mchdev_lock;
+ spin_unlock(mchdev_lock);
- ips_ping_for_i915_load();
+ ips_ping_for_i915_load();
+ }
return 0;
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 19/24] drm/i915: detect digital outputs on Haswell
On Mon, 30 Apr 2012 21:33:42 -0300 Eugeni Dodonov eug...@dodonov.net wrote: On Mon, Apr 30, 2012 at 21:27, Jesse Barnes jbar...@virtuousgeek.orgwrote: We really really need to get the port detection working on HSW using the VBT. It is not that easy from what I've seen. VBT can give some hints on which ports can support only DP or HDMI, but it does not answers all the cases. So the best solution seems to be running a DP AUX query when we got an output, and if it succeeds - it is a DP; otherwise, it is HDMI. So my idea here is: - add both HDMI and DP connectors for each available port (those we can get via VBT and from the GPU variant - some variants don't have specific DDIs in hardware, and VBT can further say which DDI are incapable of driving HDMI when present) - add an intel_ddi_detect routine for .detect of each of them - the intel_ddi_detect would try doing the DP AUX test, and dispatch either intel_hdmi_detect or intel_dp_detect accordingly. Once the DP code will be ready, we'll put this in place. But for now, only HDMI works anyway, and I don't have any DP monitor around to play with :). Does this looks reasonable? I had wanted to avoid every HSW system looking like it had a bunch of HDMI and DP ports, when it really only has one of each or something. -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Only enable IPS polling for gen5
On Tue, May 01, 2012 at 07:58:27AM -0700, Jesse Barnes wrote: On Mon, 30 Apr 2012 19:35:02 +0100 Chris Wilson ch...@chris-wilson.co.uk wrote: On SandyBridge IPS was entirely implemented in hardware and not reliant on the driver monitoring power consumption and feeding back desired run states, so the hardware is able to adapt quicker and more flexibly. Which is a huge relief for us as we no longer have to carry empirically derived magic algorithms. Yet despite the advance in technology, the driver was still doing its IPS polling on all machines. Restrict it to the only supported hardware, Clarkdale/Arrandale. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Jesse Barnes jbar...@virtuousgeek.org Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Mail: dan...@ffwll.ch Mobile: +41 (0)79 365 57 48 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/5] drm/i915: Dynamic Parity Detection handling
On Fri, Apr 27, 2012 at 05:40:18PM -0700, Ben Widawsky wrote:
On IVB hardware we are given an interrupt whenever a L3 parity error
occurs in the L3 cache. The L3 cache is used by internal GPU clients
only. This is a very rare occurrence (in fact to test this I need to
use specially instrumented silicon).
When a row in the L3 cache detects a parity error the HW generates an
interrupt. The interrupt is masked in GTIMR until we get a chance to
read some registers and alert userspace via a uevent. With this
information userspace can use a sysfs interface (follow-up patch) to
remap those rows.
Way above my level of understanding, but if a given row fails, it is
statistically more likely to fail again than a row which has not failed.
Therefore it is desirable for an operating system to maintain a lifelong
list of failing rows and always remap any bad rows on driver load.
Hardware limits the number of rows that are remappable per bank/subbank,
and should more than that many rows detect parity errors, software
should maintain a list of the most frequent errors, and remap those
rows.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_drv.h |2 +
drivers/gpu/drm/i915/i915_irq.c | 83
+++
drivers/gpu/drm/i915/i915_reg.h | 17
3 files changed, 102 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 69e1539..9505fc0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -804,6 +804,8 @@ typedef struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
+
+ struct work_struct parity_error_work;
} drm_i915_private_t;
enum hdmi_force_audio {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ab023ca..81e5a7d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -430,6 +430,83 @@ static void gen6_pm_rps_work(struct work_struct *work)
mutex_unlock(dev_priv-dev-struct_mutex);
}
+
+/**
+ * ivybridge_parity_work - Workqueue called when a parity error interrupt
+ * occurred.
+ *
+ * Doesn't actually do anything except notify userspace so that userspace may
+ * disable things later on.
+ */
+static void ivybridge_parity_work(struct work_struct *work)
+{
+ drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
+ parity_error_work);
+
+ u32 error_status, row, bank, subbank;
+ char *parity_event[5];
+ uint32_t misccpctl;
+ unsigned long flags;
+
+ /* We must turn off DOP level clock gating to access the L3 registers.
+ * In order to prevent a get/put style interface, acquire struct mutex
+ * any time we access those registers.
+ */
+ mutex_lock(dev_priv-dev-struct_mutex);
+
+ misccpctl = I915_READ(GEN7_MISCCPCTL);
+ I915_WRITE(GEN7_MISCCPCTL, misccpctl ~GEN7_DOP_CLOCK_GATE_ENABLE);
+ POSTING_READ(GEN7_MISCCPCTL);
+
+ error_status = I915_READ(GEN7_L3CDERRST1);
+ row = GEN7_PARITY_ERROR_ROW(error_status);
+ bank = GEN7_PARITY_ERROR_BANK(error_status);
+ subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
+
+ I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
+ GEN7_L3CDERRST1_ENABLE);
+ POSTING_READ(GEN7_L3CDERRST1);
+
+ I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+
+ spin_lock_irqsave(dev_priv-irq_lock, flags);
+ dev_priv-gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
+ I915_WRITE(GTIMR, dev_priv-gt_irq_mask);
+ spin_unlock_irqrestore(dev_priv-irq_lock, flags);
+
+ mutex_unlock(dev_priv-dev-struct_mutex);
+
+ parity_event[0] = L3_PARITY_ERROR=1;
+ parity_event[1] = kasprintf(GFP_KERNEL, ROW=%d, row);
+ parity_event[2] = kasprintf(GFP_KERNEL, BANK=%d, bank);
+ parity_event[3] = kasprintf(GFP_KERNEL, SUBBANK=%d, subbank);
+ parity_event[4] = NULL;
+
+ kobject_uevent_env(dev_priv-dev-primary-kdev.kobj,
+KOBJ_CHANGE, parity_event);
+
+ kfree(parity_event[3]);
+ kfree(parity_event[2]);
+ kfree(parity_event[1]);
+}
+
+void ivybridge_handle_parity_error(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev-dev_private;
+ unsigned long flags;
+
+ if (WARN_ON(IS_GEN6(dev)))
+ return;
+
+ spin_lock_irqsave(dev_priv-irq_lock, flags);
+ dev_priv-gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
+ I915_WRITE(GTIMR, dev_priv-gt_irq_mask);
+ spin_unlock_irqrestore(dev_priv-irq_lock, flags);
+
+ queue_work(dev_priv-wq, dev_priv-parity_error_work);
+ DRM_INFO(Parity error interrupt. Scheduling work\n);
+}
+
static void snb_gt_irq_handler(struct drm_device *dev,
Re: [Intel-gfx] [PATCH 4/5] drm/i915: wait render timeout ioctl
On Tue, 01 May 2012 10:19:53 -0700 Eric Anholt e...@anholt.net wrote: On Mon, 30 Apr 2012 18:41:08 -0700, Ben Widawsky b...@bwidawsk.net wrote: This helps implement GL_ARB_sync put stops short of allowing full blow but? blown? sync objects. Finally we can use the new timed seqno waiting function to allow userspace to wait on a request with a timeout. This implements that interface. It looks like this actually lets them wait on a BO with a timeout. I like it as an interface, but that's not what I expected from the commit message. Waiting on a request sounds like passing a seqno back out to userland that they could wait on. Yeah. Chris asked me to update the comments actually, and I forgot. I will resubmit this patch with better comments in the not too distant future. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/5] drm/i915: l3 parity sysfs interface
On Fri, Apr 27, 2012 at 05:40:21PM -0700, Ben Widawsky wrote:
Dumb binary interfaces which allow root-only updates of the cache
remapping registers. As mentioned in a previous patch, software using
this interface needs to know about HW limits, and other programming
considerations as the kernel interface does no checking for these things
on the root-only interface.
v1: Drop extra posting reads (Chris)
Return negative values in the sysfs interfaces on errors (Chris)
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_sysfs.c | 128
-
1 file changed, 126 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index 79f8344..ed77cbf 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -29,6 +29,7 @@
#include linux/module.h
#include linux/stat.h
#include linux/sysfs.h
+#include intel_drv.h
#include i915_drv.h
static u32 calc_residency(struct drm_device *dev, const u32 reg)
@@ -92,20 +93,143 @@ static struct attribute_group rc6_attr_group = {
.attrs = rc6_attrs
};
+static int l3_access_valid(struct drm_device *dev, loff_t offset)
+{
+ if (!IS_IVYBRIDGE(dev))
+ return -EPERM;
+
+ if (offset % 4 != 0)
+ return -EPERM;
+
+ if (offset = GEN7_L3LOG_SIZE)
+ return -ENXIO;
+
+ return 0;
+}
+
+static ssize_t
+i915_l3_read(struct file *filp, struct kobject *kobj,
+ struct bin_attribute *attr, char *buf,
+ loff_t offset, size_t count)
+{
+ struct device *dev = container_of(kobj, struct device, kobj);
+ struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
+ struct drm_device *drm_dev = dminor-dev;
+ struct drm_i915_private *dev_priv = drm_dev-dev_private;
+ uint32_t misccpctl;
+ int i, ret;
+
+ ret = l3_access_valid(drm_dev, offset);
+ if (ret)
+ return ret;
+
+ ret = i915_mutex_lock_interruptible(drm_dev);
+ if (ret)
+ return ret;
+
+ misccpctl = I915_READ(GEN7_MISCCPCTL);
+ I915_WRITE(GEN7_MISCCPCTL, misccpctl ~GEN7_DOP_CLOCK_GATE_ENABLE);
+
+ for (i = offset; count = 4 i GEN7_L3LOG_SIZE; i += 4, count -= 4)
+ *((uint32_t *)(buf[i])) = I915_READ(GEN7_L3LOG_BASE + i);
+
+ I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+
+ mutex_unlock(drm_dev-struct_mutex);
+
+ return i - offset;
+}
+
+static ssize_t
+i915_l3_write(struct file *filp, struct kobject *kobj,
+ struct bin_attribute *attr, char *buf,
+ loff_t offset, size_t count)
+{
+ struct device *dev = container_of(kobj, struct device, kobj);
+ struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
+ struct drm_device *drm_dev = dminor-dev;
+ struct drm_i915_private *dev_priv = drm_dev-dev_private;
+ u32 *temp = NULL;
+ int i, ret;
+
+ ret = l3_access_valid(drm_dev, offset);
+ if (ret)
+ return ret;
+
+ ret = i915_mutex_lock_interruptible(drm_dev);
+ if (ret)
+ return ret;
+
+ if (!dev_priv-mm.l3_remap_info) {
+ temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
+ if (!temp) {
+ mutex_unlock(drm_dev-struct_mutex);
+ return -ENOMEM;
+ }
+ }
+
+ ret = i915_gpu_idle(drm_dev, true);
+ if (ret) {
+ kfree(temp);
+ mutex_unlock(drm_dev-struct_mutex);
+ return ret;
+ }
+
+ /* TODO: Ideally we really want a GPU reset here to make sure errors
+ * aren't propagated Since I cannot find a stable way to reset the GPU
+ * at this point it is left as a TODO.
+ */
+
+ if (dev_priv-mm.l3_remap_info)
+ temp = dev_priv-mm.l3_remap_info;
+
+ dev_priv-mm.l3_remap_info = temp;
+
+ for (i = offset; count = 4 i GEN7_L3LOG_SIZE; i += 4, count -= 4)
{
+ u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
+ if (remap remap != *temp)
+ DRM_ERROR(0x%x was already programmed to %x\n,
+ GEN7_L3LOG_BASE + i, remap);
+ *temp++ = *(uint32_t *)(buf[i]);
+ }
+
+ i915_gem_l3_remap(drm_dev);
+
+ mutex_unlock(drm_dev-struct_mutex);
+
+ return offset - i;
+}
+
+static struct bin_attribute dpf_attrs = {
+ .attr = {.name = l3_parity, .mode = (S_IRUSR | S_IWUSR)},
+ .size = GEN7_L3LOG_SIZE,
+ .read = i915_l3_read,
+ .write = i915_l3_write,
+ .mmap = NULL
+};
+
void i915_setup_sysfs(struct drm_device *dev)
{
int ret;
- /* ILK doesn't have any residency information */
+ /* ILK and below don't yet have relevant sysfs files */
if (INTEL_INFO(dev)-gen 6)
return;
ret =
Re: [Intel-gfx] [PATCH 5/5] drm/i915: l3 parity sysfs interface
On Tue, 1 May 2012 20:24:44 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Fri, Apr 27, 2012 at 05:40:21PM -0700, Ben Widawsky wrote:
Dumb binary interfaces which allow root-only updates of the cache
remapping registers. As mentioned in a previous patch, software using
this interface needs to know about HW limits, and other programming
considerations as the kernel interface does no checking for these things
on the root-only interface.
v1: Drop extra posting reads (Chris)
Return negative values in the sysfs interfaces on errors (Chris)
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_sysfs.c | 128
-
1 file changed, 126 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index 79f8344..ed77cbf 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -29,6 +29,7 @@
#include linux/module.h
#include linux/stat.h
#include linux/sysfs.h
+#include intel_drv.h
#include i915_drv.h
static u32 calc_residency(struct drm_device *dev, const u32 reg)
@@ -92,20 +93,143 @@ static struct attribute_group rc6_attr_group = {
.attrs = rc6_attrs
};
+static int l3_access_valid(struct drm_device *dev, loff_t offset)
+{
+ if (!IS_IVYBRIDGE(dev))
+ return -EPERM;
+
+ if (offset % 4 != 0)
+ return -EPERM;
+
+ if (offset = GEN7_L3LOG_SIZE)
+ return -ENXIO;
+
+ return 0;
+}
+
+static ssize_t
+i915_l3_read(struct file *filp, struct kobject *kobj,
+struct bin_attribute *attr, char *buf,
+loff_t offset, size_t count)
+{
+ struct device *dev = container_of(kobj, struct device, kobj);
+ struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
+ struct drm_device *drm_dev = dminor-dev;
+ struct drm_i915_private *dev_priv = drm_dev-dev_private;
+ uint32_t misccpctl;
+ int i, ret;
+
+ ret = l3_access_valid(drm_dev, offset);
+ if (ret)
+ return ret;
+
+ ret = i915_mutex_lock_interruptible(drm_dev);
+ if (ret)
+ return ret;
+
+ misccpctl = I915_READ(GEN7_MISCCPCTL);
+ I915_WRITE(GEN7_MISCCPCTL, misccpctl ~GEN7_DOP_CLOCK_GATE_ENABLE);
+
+ for (i = offset; count = 4 i GEN7_L3LOG_SIZE; i += 4, count -= 4)
+ *((uint32_t *)(buf[i])) = I915_READ(GEN7_L3LOG_BASE + i);
+
+ I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+
+ mutex_unlock(drm_dev-struct_mutex);
+
+ return i - offset;
+}
+
+static ssize_t
+i915_l3_write(struct file *filp, struct kobject *kobj,
+ struct bin_attribute *attr, char *buf,
+ loff_t offset, size_t count)
+{
+ struct device *dev = container_of(kobj, struct device, kobj);
+ struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
+ struct drm_device *drm_dev = dminor-dev;
+ struct drm_i915_private *dev_priv = drm_dev-dev_private;
+ u32 *temp = NULL;
+ int i, ret;
+
+ ret = l3_access_valid(drm_dev, offset);
+ if (ret)
+ return ret;
+
+ ret = i915_mutex_lock_interruptible(drm_dev);
+ if (ret)
+ return ret;
+
+ if (!dev_priv-mm.l3_remap_info) {
+ temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
+ if (!temp) {
+ mutex_unlock(drm_dev-struct_mutex);
+ return -ENOMEM;
+ }
+ }
+
+ ret = i915_gpu_idle(drm_dev, true);
+ if (ret) {
+ kfree(temp);
+ mutex_unlock(drm_dev-struct_mutex);
+ return ret;
+ }
+
+ /* TODO: Ideally we really want a GPU reset here to make sure errors
+* aren't propagated Since I cannot find a stable way to reset the GPU
+* at this point it is left as a TODO.
+ */
+
+ if (dev_priv-mm.l3_remap_info)
+ temp = dev_priv-mm.l3_remap_info;
+
+ dev_priv-mm.l3_remap_info = temp;
+
+ for (i = offset; count = 4 i GEN7_L3LOG_SIZE; i += 4, count -= 4)
{
+ u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
+ if (remap remap != *temp)
+ DRM_ERROR(0x%x was already programmed to %x\n,
+ GEN7_L3LOG_BASE + i, remap);
+ *temp++ = *(uint32_t *)(buf[i]);
+ }
+
+ i915_gem_l3_remap(drm_dev);
+
+ mutex_unlock(drm_dev-struct_mutex);
+
+ return offset - i;
+}
+
+static struct bin_attribute dpf_attrs = {
+ .attr = {.name = l3_parity, .mode = (S_IRUSR | S_IWUSR)},
+ .size = GEN7_L3LOG_SIZE,
+ .read = i915_l3_read,
+ .write = i915_l3_write,
+ .mmap = NULL
+};
+
void i915_setup_sysfs(struct drm_device *dev)
{
int ret;
- /* ILK doesn't have any residency information */
+ /* ILK and below don't yet have relevant sysfs files */
if (INTEL_INFO(dev)-gen
Re: [Intel-gfx] [PATCH 19/24] drm/i915: detect digital outputs on Haswell
On Tue, 1 May 2012 08:01:08 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: I had wanted to avoid every HSW system looking like it had a bunch of HDMI and DP ports, when it really only has one of each or something. Every DP port is also an HDMI port when a DP to HDMI converter is plugged in. -- keith.pack...@intel.com pgpJ41qlOy7cv.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
