On Thu, Aug 15, 2013 at 05:30:25PM -0700, james.aus...@intel.com wrote:
Hello All-
I'm trying to determine if the ChromeOS-only patches being carried by
Google still make sense and are the right way to do things in the 3.11+
world, and Jesse asked me to forward the patches to the list for
On Thu, Aug 15, 2013 at 12:13 PM, Chris Wilson ch...@chris-wilson.co.uk wrote:
I've just pushed a (cairo-based!) tool to intel-gpu-tools,
intel_framebuffer_dump, that should also confirm everything we've found
so far - i.e. that we read and write consistently through the GTT into
stolen
On Tue, Aug 06, 2013 at 07:01:14PM +0100, Chris Wilson wrote:
After any soft gfx reset we must manually invalidate the TLBs
associated with each ring. Empirically, it seems that a
suspend/resume or D3-D0 cycle count as a soft reset. The symptom is
that the hardware would fail to note the new
On Fri, Aug 16, 2013 at 09:24:01AM +0200, Sedat Dilek wrote:
On Thu, Aug 15, 2013 at 12:13 PM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
I've just pushed a (cairo-based!) tool to intel-gpu-tools,
intel_framebuffer_dump, that should also confirm everything we've found
so far - i.e. that
On Thu, Aug 15, 2013 at 05:30:37PM -0700, james.aus...@intel.com wrote:
From: Todd Broch tbr...@chromium.org
BUG=chrome-os-partner:6768
TEST=manual,
- boot kernel
1. cat /sys/module/i915/parameters/i915_enable_rc6
- should equal 1
2. start powertop, goto 'Idle Stats' tab
- make sure
On Thu, Aug 15, 2013 at 05:30:40PM -0700, james.aus...@intel.com wrote:
From: Stéphane Marchesin marc...@chromium.org
The thresholds for GPU reclocking are highly asymetrical. This creates an
interesting phenomenon on Chrome startup where the clock ramps up very
quickly, and then the
On Thu, Aug 15, 2013 at 05:30:32PM -0700, james.aus...@intel.com wrote:
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
@@ -2330,6 +2336,12 @@ intel_dp_detect(struct drm_connector *connector, bool
force)
On Thu, Aug 15, 2013 at 05:30:39PM -0700, james.aus...@intel.com wrote:
From: Simon Que s...@chromium.org
marcheu added these changes in kernel 3.0:
https://gerrit.chromium.org/gerrit/12367
https://gerrit.chromium.org/gerrit/12368
They were undone in kernel 3.2. This patch restores
On Thu, Aug 15, 2013 at 05:30:27PM -0700, james.aus...@intel.com wrote:
From: Chris Wolfe cwo...@chromium.org
Unfortunately some combinations of hardware seem to generate successful
communications on the aux channel, which always report deferred. As a
result native_write can wind up in an
On Fri, 16 Aug 2013, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Aug 15, 2013 at 05:30:25PM -0700, james.aus...@intel.com wrote:
Hello All-
I'm trying to determine if the ChromeOS-only patches being carried by
Google still make sense and are the right way to do things in the 3.11+
world,
On Fri, Aug 16, 2013 at 9:39 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Fri, Aug 16, 2013 at 09:24:01AM +0200, Sedat Dilek wrote:
On Thu, Aug 15, 2013 at 12:13 PM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
I've just pushed a (cairo-based!) tool to intel-gpu-tools,
On Fri, Aug 16, 2013 at 10:34 AM, Sedat Dilek sedat.di...@gmail.com wrote:
On Fri, Aug 16, 2013 at 9:39 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Fri, Aug 16, 2013 at 09:24:01AM +0200, Sedat Dilek wrote:
On Thu, Aug 15, 2013 at 12:13 PM, Chris Wilson ch...@chris-wilson.co.uk
On Thu, Aug 15, 2013 at 04:54:15PM -0600, Alex Williamson wrote:
On Fri, 2013-08-16 at 08:49 +1000, Dave Airlie wrote:
On Fri, Aug 16, 2013 at 8:43 AM, Alex Williamson
alex.william...@redhat.com wrote:
This is intended to add VGA arbiter support for Intel HD graphics on
Core processors.
Summary
We covered the platform: Haswell mobile, HSW desktop, HSW ULT, IvyBridge,
SandyBridge, IronLake. in this circle, 13 new bugs are filed, 26 bugs are still
opened, no WONTFIX bugs, 1 NOTABUG bugs,4 NOTOURBUG bugs, 3 Duplicated bugs,1
REOPENED bugs, 17 bugs are closed.
Test Environment
Summary
We covered the platform: Haswell mobile, HSW desktop, HSW ULT, IvyBridge,
SandyBridge, IronLake. in this circle, 13 new bugs are filed, 26 bugs are still
opened, no WONTFIX bugs, 1 NOTABUG bugs,4 NOTOURBUG bugs, 3 Duplicated bugs,1
REOPENED bugs, 17 bugs are closed.
Test Environment
On Tue, 2013-08-06 at 11:09 +0200, Daniel Vetter wrote:
On Mon, Aug 05, 2013 at 02:45:25PM +0300, Imre Deak wrote:
At the moment any command line option handling done by tests will
interfere with the option handling of the subtest interface. To fix this
add a new version of the subtest_init
libvdpau uses second DRI driver name to determine which VDPAU driver
to use. This patch will allow libvdpau choose libvdpau_i965.so on systems
with Intel GPUs, libvdpau_nvidia.so on those with nVidia ones, and so on.
I'm experimenting now with generic vdpau driver using OpenGL/VA-API,
it would be
On Fri, Aug 16, 2013 at 02:07:07PM +0300, Imre Deak wrote:
On Tue, 2013-08-06 at 11:09 +0200, Daniel Vetter wrote:
On Mon, Aug 05, 2013 at 02:45:25PM +0300, Imre Deak wrote:
At the moment any command line option handling done by tests will
interfere with the option handling of the subtest
On Fri, Aug 16, 2013 at 09:20:49AM +0100, Chris Wilson wrote:
On Mon, May 20, 2013 at 11:15:08AM -0700, Stuart Abercrombie wrote:
90% of core speed (=180MHz dot clock) is too high for 2048x1280 to get
pixel doubling on Pineview, which it needs to avoid underruns, so
lower this to 85%.
On Fri, Aug 16, 2013 at 08:31:35AM +0100, Chris Wilson wrote:
On Tue, Aug 06, 2013 at 07:01:14PM +0100, Chris Wilson wrote:
After any soft gfx reset we must manually invalidate the TLBs
associated with each ring. Empirically, it seems that a
suspend/resume or D3-D0 cycle count as a soft
Hi all, v2 of
http://mid.gmane.org/cover.1376397804.git.jani.nik...@intel.com
Patch 10/15 is new, fixing PLL assertions for DSI PLL.
BR,
Jani.
Jani Nikula (10):
drm/i915: add more VLV IOSF sideband ports accessors
drm/i915: add VLV pipeconf bit definition for DSI PLL lock
drm/i915: add
From: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/drm_crtc.c |2 ++
include/uapi/drm/drm_mode.h |2 ++
2 files changed, 4 insertions(+)
diff --git
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b417a8c..2f8e341 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++
Add definitions for VLV MIPI DSI registers.
v2: Small fixes per Ville's review comments.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 410 +++
1 file changed, 410 insertions(+)
diff --git
v2: Rebase due to register bit definition change.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/Makefile|1 +
drivers/gpu/drm/i915/intel_dsi_cmd.c | 442 ++
drivers/gpu/drm/i915/intel_dsi_cmd.h | 109 +
3 files
From: ymohanma yogesh.mohan.marimu...@intel.com
v2:
- Grab dpio_lock mutex in vlv_enable_dsi_pll().
- Add and call vlv_disable_dsi_pll().
Signed-off-by: ymohanma yogesh.mohan.marimu...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Jani Nikula
For DSI, we need to be asserting DSI PLL, not DPLL.
This is a somewhat stopgap implementation. It's slightly ugly to have to
pass the dsi parameter to intel_enable_pipe().
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 44
DPLL is not needed for DSI
v2: Rebase due to added DSI PLL assertion patch.
Signed-off-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 48 --
1 file changed, 29 insertions(+),
From: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: ymohanma yogesh.mohan.marimu...@intel.com
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 48 ++
1 file
From: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/auo_dsi_display.c | 182
From: Shobhit Kumar shobhit.ku...@intel.com
Initial parsing of the VBT MIPI block. For now, just store the panel id
if found.
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |5 +
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 336bee4..2f00c98 100644
--- a/drivers/gpu/drm/i915/intel_display.c
The sub-encoder model is copied from DVO.
v2: Add attached_connector to struct intel_dsi.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.h | 99 ++
1 file changed, 99 insertions(+)
create mode 100644
This does not include any panel specific sub-encoders yet.
v2: Fix fixed mode handling (Daniel)
Signed-off-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/Makefile|1 +
drivers/gpu/drm/i915/intel_drv.h |1 +
Signed-off-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_drv.h |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index
For GPIO NC, CCK, CCU, and GPS CORE.
Signed-off-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |8 +
drivers/gpu/drm/i915/i915_reg.h |4 +++
drivers/gpu/drm/i915/intel_sideband.c | 56
On Fri, Aug 16, 2013 at 1:15 AM, Jani Nikula jani.nik...@linux.intel.com
wrote:
On Fri, 16 Aug 2013, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Aug 15, 2013 at 05:30:25PM -0700, james.aus...@intel.com wrote:
Hello All-
I'm trying to determine if the ChromeOS-only patches being carried
The vma will [possibly] be destroyed during unbind in eviction.
Immediately after this, we try to delete the list entry.
Chris and Ville did the debug on this before I woke up, I just get to
take credit for the fix :p
Reported-by: Mika Kuoppala mika.kuopp...@intel.com
Cc: Ville Syrjälä
On Fri, 2013-08-16 at 13:20 +0300, Ville Syrjälä wrote:
On Thu, Aug 15, 2013 at 04:54:15PM -0600, Alex Williamson wrote:
On Fri, 2013-08-16 at 08:49 +1000, Dave Airlie wrote:
On Fri, Aug 16, 2013 at 8:43 AM, Alex Williamson
alex.william...@redhat.com wrote:
This is intended to add VGA
On 08/14/2013 01:19 AM, Sedat Dilek wrote:
AFAICS, there are more updates needed to be in sync with recent kernel-drm.
I fell over the misspelling when digging into an issue in Linux-next.
The spelling should be consistent in kernel-drm, libdrm, intel-ddx, etc.
Here, I had a look especially at
The vma will [possibly] be destroyed during unbind in eviction.
Immediately after this, we try to delete the list entry.
Chris and Ville did the debug on this before I woke up, I just get to
take credit for the fix :p
v2: Missed the drm_object_unreference use after free (Ville)
Reported-by:
41 matches
Mail list logo
