Re: [Intel-gfx] [PATCH 1/3] drm/i915: Verify address field of PCBR register.

On Sun, Dec 08, 2013 at 01:52:35PM +0530, deepa...@intel.com wrote: > From: Deepak S > > On VLV the PCBR register has other bits besides the pcbr address > field. Verify only address field setup by BIOS to make sure we don't > misinterpret the PCBR setup. > > Signed-off-by: Deepak S > --- > dr

Re: [Intel-gfx] [Intel gfx][i-g-t PATCH 3/4] rendercopy/bdw: A workaround for 3D pipeline

On Mon, Dec 9, 2013 at 5:47 AM, Xiang, Haihao wrote: > Oh, it works even with an batch which has only MI_BATCH_BUFFER_END. This sounds like we're missing a tlb/cache invalidate before launching the batch in the kernel. But the big flush we unconditionally do after each batch is good enough to fix

Re: [Intel-gfx] [Intel gfx][i-g-t PATCH 3/4] rendercopy/bdw: A workaround for 3D pipeline

On Fri, 2013-12-06 at 13:30 +, Damien Lespiau wrote: > On Fri, Dec 06, 2013 at 04:54:46PM +0800, Xiang, Haihao wrote: > > From: "Xiang, Haihao" > > > > Emit PIPELINE_SELECT twice and make sure the commands in > > the first batch buffer have been done. > > > > However I don't know why this w

Re: [Intel-gfx] [PATCH 2/4] drm/i915: set min delay to rpe delay (Efficient frequency) for better performace.

On Sun, Dec 08, 2013 at 02:16:44PM +0530, deepa...@intel.com wrote: > From: Deepak S > > We use RPe here since it should match the Vmin we were shooting for. > That should give us better perf than if we used the min freq available. > System thermal can take the system to lowest possible freq (RP1

Re: [Intel-gfx] [PATCH 46/48] drm: Optionally create mm blocks from top-to-bottom

Hi On Fri, Dec 6, 2013 at 11:11 PM, Ben Widawsky wrote: > From: Chris Wilson > > Clients like i915 needs to segregate cache domains within the GTT which > can lead to small amounts of fragmentation. By allocating the uncached > buffers from the bottom and the cacheable buffers from the top, we c

Re: [Intel-gfx] [PATCH 05/19] drm/i915: add initial Runtime PM functions

At Fri, 6 Dec 2013 20:31:04 -0200, Paulo Zanoni wrote: > > 2013/11/29 Takashi Iwai : > > At Wed, 27 Nov 2013 18:10:30 -0200, > > Paulo Zanoni wrote: > >> > >> From: Paulo Zanoni > >> > >> This patch adds the initial infrastructure to allow a Runtime PM > >> implementation that sets the device to

[Intel-gfx] [PATCH 4/4] drm/i915: WA to fix Voltage is not getting dropped to Vmin when Gfx is power gated.

From: Deepak S Voltage is not getting dropped to Vmin when GFX enters RC6 and running in/out of turbo frequency. When we enter RC6 and GFX Clocks are off, the voltage remains higher than Vmin. As GFX does not request lower frequencies when it is power gated. Ideally the Voltage should be dropped

[Intel-gfx] [PATCH 1/4] drm/i915: update current freq properly before requesting new freq.

From: Deepak S on VLV, P-Unit doesn't garauntee that last requested freq by driver is actually the current running frequency. We need to make sure we update the cur freq. before requesitng new freq. Signed-off-by: Deepak S --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_i

[Intel-gfx] [PATCH 2/4] drm/i915: set min delay to rpe delay (Efficient frequency) for better performace.

From: Deepak S We use RPe here since it should match the Vmin we were shooting for. That should give us better perf than if we used the min freq available. System thermal can take the system to lowest possible freq (RP1). We are making sure, we calmp the freq to min_delay (RPe). Signed-off-by: D

[Intel-gfx] [PATCH 3/4] drm/i915: Disable/Enable PM Intrrupts based on the current freq.

From: Deepak S When current delay is already at max delay, Let's disable the PM UP THRESHOLD INTRRUPTS, so that we will not get further interrupts until current delay is less than max delay, Also request for the PM DOWN THRESHOLD INTRRUPTS to indicate the decrease in clock freq. and viceversa for

[Intel-gfx] [PATCH 0/4] Fixes for vlv turbo.

From: Deepak S This patch includes 1. update current freq properly before requesting new freq. 2. set min delay to rpe delay (Efficient frequency) for better performace. 3. Disable/Enable PM Intrrupts based on the current freq. 4. WA to fix Voltage is not getting

[Intel-gfx] [PATCH 3/3] drm/i915: Remove duplicate intel_uncore_forcewake_reset.

From: Deepak S Since early sanitize and uncore sanitize are called one after the other, I think, we can remove second forcewake reset which was are calling twice in both the functions. Signed-off-by: Deepak S --- drivers/gpu/drm/i915/intel_uncore.c | 2 -- 1 file changed, 2 deletions(-) diff

[Intel-gfx] [PATCH 1/3] drm/i915: Verify address field of PCBR register.

From: Deepak S On VLV the PCBR register has other bits besides the pcbr address field. Verify only address field setup by BIOS to make sure we don't misinterpret the PCBR setup. Signed-off-by: Deepak S --- drivers/gpu/drm/i915/intel_pm.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion

[Intel-gfx] [PATCH 2/3] drm/i915: Bring UP Power Wells before disabling RC6.

From: Deepak S Instead of waiting for HW to bringup the wells, We force the wells up before disabling RC6. This is to avoid any register access when wells are down. Signed-off-by: Deepak S --- drivers/gpu/drm/i915/intel_pm.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu