On Wed, 05 Mar 2014, Dave Airlie airl...@gmail.com wrote:
On Tue, Mar 4, 2014 at 11:49 PM, Jani Nikula jani.nik...@intel.com wrote:
Hi Dave -
Small fixes all around, mostly stable material. Please pull.
BR,
Jani.
The following changes since commit
On Wed, Mar 05, 2014 at 01:46:35AM +0100, Kenneth Johansson wrote:
Now the question is is it possible to make the i7 4770R chip(I
guess its another chip doing the displayport stuff the cpu is only
the gfx accellerator right) support MST and DisplayID . And if so
what is needed in the driver
On Wed, 05 Mar 2014, Ben Widawsky benjamin.widaw...@intel.com wrote:
The PDE needs to wrap after writing all the PTEs. Quite a small/silly
bug to find in the massive change. It was introduced:
commit 307dc4f99f6d3a74a78b0e776838f35b2004f14d
Author: Ben Widawsky benjamin.widaw...@intel.com
On Tue, Mar 04, 2014 at 10:01:56PM +, Chris Wilson wrote:
On Tue, Mar 04, 2014 at 01:27:05PM -0800, Ben Widawsky wrote:
On Tue, Mar 04, 2014 at 03:45:56PM +0100, Daniel Vetter wrote:
On Tue, Feb 18, 2014 at 11:18:04AM -0800, Ben Widawsky wrote:
On Wed, Feb 12, 2014 at 07:18:40PM
On Tue, Mar 04, 2014 at 09:38:56AM -0800, Ben Widawsky wrote:
The actual post sync op is Write Immediate Data QWord. It is therefore
arguable that we should have always done a qword write.
Not really since the spec explicitly says that we can choose either a
dword or qword write. Note that
Dynamic Refresh Rate Switching (DRRS) is a power conservation feature which
enables swtiching between low and high refresh rates based on the usage
scenario. This feature is applciable for internal eDP panel. Indication that
the panel supports DRRS is given by the panel EDID,
On Wed, 05 Mar 2014, Ben Widawsky benjamin.widaw...@intel.com wrote:
| has a higher precedence than ?. Therefore, the calculation doesn't do
at all what you would expect. Thanks to Ken for convincing me that this
was indeed the issue. Send me back to C programmer school, please.
I'm sort of
From: Pradeep Bhat pradeep.b...@intel.com
This patch reads the DRRS support and Mode type from VBT fields.
The read information will be stored in VBT struct during BIOS
parsing. The above functionality is needed for decision making
whether DRRS feature is supported in i915 driver for eDP panels.
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M N registers and the new M/N values will be used in the next
Definition of VLV RR switch bit and corresponding toggling in
set_drrs function.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Uma Shankar uma.shan...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_dp.c | 10 --
2 files
From: Pradeep Bhat pradeep.b...@intel.com
This patch and finds out the lowest refresh rate supported for the resolution
same as the fixed_mode.
It also checks the VBT fields to see if panel supports seamless DRRS or not.
Based on above data it marks whether eDP panel supports seamless DRRS or
From: Pradeep Bhat pradeep.b...@intel.com
This patch computes and stored 2nd M/N/TU for switching to different
refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
between alternate refresh rates programmed in 2nd M/N/TU registers.
v2: Daniel's review comments
Computing M2/N2
Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable. If there is a page flip or call to
update the plane, then high refresh rate is applied.
The feature is not used in
Users just love to set random piles of options since surely enabling
all the experimental stuff helps. Later on we get bug reports because
it all fell apart.
Even more fun when it's labelled a regression when some change only
just made the feature possible (e.g. stolen memory fixes suddenly
On Wed, Mar 5, 2014 at 9:24 AM, Jani Nikula jani.nik...@intel.com wrote:
On Wed, 05 Mar 2014, Dave Airlie airl...@gmail.com wrote:
On Tue, Mar 4, 2014 at 11:49 PM, Jani Nikula jani.nik...@intel.com wrote:
Hi Dave -
Small fixes all around, mostly stable material. Please pull.
BR,
Jani.
On Wed, Mar 05, 2014 at 03:13:06PM +0530, Vandana Kannan wrote:
+void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_encoder *encoder;
+ struct intel_dp *intel_dp = NULL;
+ struct
On Tue, Feb 18, 2014 at 12:02:08AM +0200, Imre Deak wrote:
Parts that poke port specific HW blocks like the encoder HW state
readout or connector hotplug detect code need a way to check whether
required power domains are on or enable/disable these. For this purpose
add a set of power domains
On Mon, Feb 24, 2014 at 01:56:20PM +0200, Imre Deak wrote:
On Thu, 2014-02-20 at 11:33 -0800, Jesse Barnes wrote:
On Wed, 19 Feb 2014 14:39:58 +0200
Imre Deak imre.d...@intel.com wrote:
On Wed, 2014-02-19 at 14:35 +0200, Ville Syrjälä wrote:
On Tue, Feb 18, 2014 at 12:02:09AM +0200,
On Tue, Feb 18, 2014 at 12:02:10AM +0200, Imre Deak wrote:
Since the encoder is tied to its port, we need to make sure the power
domain for that port is on before reading out the encoder HW state.
Signed-off-by: Imre Deak imre.d...@intel.com
+bool intel_encoder_get_hw_state(struct
On Thu, Feb 20, 2014 at 11:37:25AM -0800, Jesse Barnes wrote:
On Tue, 18 Feb 2014 00:02:11 +0200
Imre Deak imre.d...@intel.com wrote:
We can read out the pipe HW state only if the required power domain is
on. If not we consider the pipe to be off.
Signed-off-by: Imre Deak
On Mon, Feb 24, 2014 at 03:23:23PM +0200, Imre Deak wrote:
On Thu, 2014-02-20 at 11:48 -0800, Jesse Barnes wrote:
On Tue, 18 Feb 2014 00:02:15 +0200
Imre Deak imre.d...@intel.com wrote:
On VLV at least the display IRQ register access and functionality
depends on its power well to be
On Thu, Feb 20, 2014 at 11:51:33AM -0800, Jesse Barnes wrote:
On Tue, 18 Feb 2014 00:02:16 +0200
Imre Deak imre.d...@intel.com wrote:
This way we can reuse the check on other platforms too. Also factor out
a version of the function that doesn't check if the power is on, we'll
need to
On Tue, Feb 18, 2014 at 07:59:05PM +0200, Ville Syrjälä wrote:
On Tue, Feb 18, 2014 at 07:37:01PM +0200, Imre Deak wrote:
On Tue, 2014-02-18 at 18:55 +0200, Ville Syrjälä wrote:
On Tue, Feb 18, 2014 at 12:02:17AM +0200, Imre Deak wrote:
Suggested by Daniel.
Signed-off-by: Imre
On Thu, Feb 20, 2014 at 11:53:07AM -0800, Jesse Barnes wrote:
On Tue, 18 Feb 2014 00:02:19 +0200
Imre Deak imre.d...@intel.com wrote:
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
On Wed, Feb 26, 2014 at 11:52:25AM -0800, Jesse Barnes wrote:
On Wed, 26 Feb 2014 20:02:19 +0200
Imre Deak imre.d...@intel.com wrote:
On Thu, 2014-02-20 at 11:58 -0800, Jesse Barnes wrote:
I'd like to see the code for re-enabling the display state land
eventually too, so we can get
On Tue, Feb 18, 2014 at 10:15:44AM -0800, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
Certain OpenGL features (e.g. transform feedback, performance monitoring)
require userspace code to submit batches containing commands such as
MI_LOAD_REGISTER_IMM to
On Fri, Feb 21, 2014 at 04:33:07PM -0300, Paulo Zanoni wrote:
2014-02-21 14:55 GMT-03:00 Chris Wilson ch...@chris-wilson.co.uk:
We currently call intel_mark_idle() too often, as we do so as a
side-effect of processing the request queue. However, we the calls to
intel_mark_idle() are
From: Sagar Kamble sagar.a.kam...@intel.com
Started documenting drm properties for drm drivers. This patch provides
information about properties in drm, i915, psb and cdv/gma-500. Information
about other properties can be added on top of these.
Cc: Rob Landley r...@landley.net
Cc: Dave Airlie
On Fri, Feb 21, 2014 at 04:06:47PM -0300, Paulo Zanoni wrote:
2014-02-20 21:01 GMT-03:00 Ben Widawsky benjamin.widaw...@intel.com:
This got lost when we shuffled around our internal branch and
GEN7_FEATURES macro. There were no HW changes to support FBC, so we just
need to set the flag.
From: Ville Syrjälä ville.syrj...@linux.intel.com
This series fixes the colors are wrong with YCbCr sprites bug on
BDW, and avoids some other bugs that would happend when someone
enables FBC on BDW.
Ville Syrjälä (3):
drm/i915: Don't clobber CHICKEN_PIPESL_1 on BDW
drm/i915: Use RMW to
From: Ville Syrjälä ville.syrj...@linux.intel.com
gen7_enable_fbc() may write to some registers which we've already
touched, so use RMW so that we don't undo any previous updates.
Also note that we implemnt WaFbcAsynchFlipDisableFbcQueue:bdw.
Signed-off-by: Ville Syrjälä
From: Ville Syrjälä ville.syrj...@linux.intel.com
We have two names for the same register CHICKEN_PIPESL_1 and
HSW_PIPE_SLICE_CHICKEN_1. Unify it to just one.
Also rename the FBCQ disable bit to resemble the name we've
given to a similar bit on earlier platforms.
Signed-off-by: Ville Syrjälä
From: Ville Syrjälä ville.syrj...@linux.intel.com
Misplaced parens cause us to totally clobber the CHICKEN_PIPESL_1
registers with 0x. Move the parens to the correct place
to avoid this.
In particular this caused bit 30 of said registers to be set, which
caused the sprite CSC to produce
On Wed, Mar 05, 2014 at 12:57:21PM +0530, Ds, Sreedhara wrote:
From: Ds, Sreedhara sreedhara...@intel.com
Added build_testdisplay.py under intel_gpu_tools/scripts. This script takes
care of all the dependencies of testdisplay tool like cairo and glib in
android
build environment.
From: Sourab Gupta sourab.gu...@intel.com
Renamed the 'pad' field to 'flags' of gem_create ioctl.
Also, added a new flag I915_CPU_MAP_NOT_NEEDED which can be passed with
gem_create ioctl.
Signed-off-by: Sourab Gupta sourab.gu...@intel.com
Signed-off-by: Akash Goel akash.g...@intel.com
---
From: Sourab Gupta sourab.gu...@intel.com
Added a new libdrm flag and a flag in the gem_create ioctl. This is used to
indicate
that cpu mapping is not required for the buffer object.
Sourab Gupta (2):
include/drm: Rename the 'pad' field to 'flags' of gem_create ioctl
intel: Added a new
From: Sourab Gupta sourab.gu...@intel.com
Added a new flag 'BO_ALLOC_CPU_MAP_NOT_NEEDED' flag which can be passed
to bo_alloc_tiled function. This is used to indicate that cpu mapping is
not required for the buffer object. This info will be passed to driver
in the gem_create ioctl.
From: Sourab Gupta sourab.gu...@intel.com
On VLV, 64MB of system memory was being reserved for stolen
area, but ~8MB of it was being utilized.
For the buffer objects which are not cpu mappable, we can allocate
the space from stolen memory, thus increasing the utilization of stolen
memory area.
From: Sourab Gupta sourab.gu...@intel.com
Adding the truncation logic for buffer objects with backing storage
from stolen memory. The objects will be truncated when user marks them
as purgeable and they are part of the inactive list.
Testcase: igt/gem_stolen_mem
Signed-off-by: Sourab Gupta
From: Sourab Gupta sourab.gu...@intel.com
Adding the flag 'I915_CPU_MAP_NOT_NEEDED' to gem_create ioctl.
This is to indicate the driver that direct cpu access to this
buffer object is not needed and hence Driver can opt to use Stolen
area as a backing store for it.
Testcase: igt/gem_stolen_mem
From: Sourab Gupta sourab.gu...@intel.com
These patches are mainly for increasing the utilization
of stolen memory area on VLV.
Although similar patches were submitted earlier, but this time the
allocation from stolen area will be done based on user's input.
We have now exposed a new libdrm
Try to flush out dirty pages into the swapcache (and from there into the
swapfile) when under memory pressure and forced to drop GEM objects from
memory. In effect, this should just allow us to discard unused pages for
memory reclaim and to start writeback earlier.
Signed-off-by: Chris Wilson
When the machine is under a lot of memory pressure and being stressed by
multiple GPU threads, we quite often report fewer than shrinker-batch
(i.e. SHRINK_BATCH) pages to be freed. This causes the shrink_control to
skip calling into i915.ko to release pages, despite the GPU holding onto
most of
Recent-ish changes to the core shrinker have made the code more prone to
hit OOM, and worse do so without even touching swap. My hypothesis is
that this is a balancing issue between shrinking the VM lists and the
slabs, such that writeback of our objects is not performed starving the
system of
The intention of returning ENOSPC for a page allocation failure due to
memory exhausstion in shmem_getpage_gfp() is purely so that a failure
on a sparse tmpfs mapping will give SIGBUS not OOM. However, for other
callers, for example i915.ko, we want to distinguish the error message
reported to
When we cannot write a page we should use redirty_page_for_writepage()
instead of plain set_page_dirty(). That tells writeback code we have
problems, redirties only the page (redirtying buffers is not needed),
and updates mm accounting of failed page writes.
Signed-off-by: Chris Wilson
We can share a few lines of tricky lock handling we need to use for both
shrinker routines and in the process fix the return value for count()
when reporting a deadlock.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem.c | 42
On Wed, Mar 05, 2014 at 05:05:40PM +0530, sourab.gu...@intel.com wrote:
From: Sourab Gupta sourab.gu...@intel.com
Adding the truncation logic for buffer objects with backing storage
from stolen memory. The objects will be truncated when user marks them
as purgeable and they are part of the
Let the drivers specify the name of the I2C-over-AUX adapter to maintain
backwards compatibility in the sysfs when converting to the new
I2C-over-AUX helper infrastructure.
The i915 driver currently uses DPDDC-A to DPDDC-D as names for the DP
i2c adapters. These names show up in the i2c sysfs
We don't want to suffer scheduling delay when turning off the GPU after
waking it up to touch registers. Ideally, we only want to keep the GPU
awake for the register access sequence, with a single forcewake dance on
the first access and release immediately after the last. We set a timer
on the
On Wed, Mar 05, 2014 at 01:05:45PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Misplaced parens cause us to totally clobber the CHICKEN_PIPESL_1
registers with 0x. Move the parens to the correct place
to avoid this.
In particular
On Mon, Mar 03, 2014 at 11:35:50AM +0530, deepa...@intel.com wrote:
From: Deepak S deepa...@intel.com
With RC6 enabled, BYT has an HW issue in determining the right
Gfx busyness.
WA for Turbo + RC6: Use SW based Gfx busy-ness detection to decide
on increasing/decreasing the freq. This logic
On Wed, Mar 05, 2014 at 12:00:39PM +, Chris Wilson wrote:
We don't want to suffer scheduling delay when turning off the GPU after
waking it up to touch registers. Ideally, we only want to keep the GPU
awake for the register access sequence, with a single forcewake dance on
the first access
On Mon, Feb 24, 2014 at 03:10:26PM +0200, Ville Syrjälä wrote:
On Wed, Feb 19, 2014 at 10:19:19PM -0800, Ben Widawsky wrote:
snip
@@ -634,6 +641,85 @@ static void render_ring_cleanup(struct
intel_ring_buffer *ring)
ring-scratch.obj = NULL;
}
+static int gen8_rcs_signal(struct
On Wed, Mar 5, 2014 at 1:17 PM, Jani Nikula jani.nik...@intel.com wrote:
BDW is no longer flagged as preliminary hw, but without
i915.preliminary_hw_support module param set the logs are filled with
WARNs about it.
Just make semaphores off the BDW per-chip default for now.
CC: Ben Widawsky
Looks like I neglected to give any kind of final conclusion on this series.
It looks like it should do the right thing, apart from the PAGE_MASK vs.
/4 bug. The other things I commented on were just minor nits. And if we
drop the poll and force restore patches, I'm happy with the result ;)
--
On 3/5/2014 5:41 PM, Ville Syrjälä wrote:
On Mon, Mar 03, 2014 at 11:35:50AM +0530, deepa...@intel.com wrote:
From: Deepak S deepa...@intel.com
With RC6 enabled, BYT has an HW issue in determining the right
Gfx busyness.
WA for Turbo + RC6: Use SW based Gfx busy-ness detection to decide
on
On Tue, Mar 04, 2014 at 10:16:02AM +0100, Daniel Vetter wrote:
On Fri, Feb 21, 2014 at 09:03:34PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
If someone holds a vblank reference across the modeset, and after/during
the modeset someone
On Tue, Mar 04, 2014 at 10:24:54AM +0100, Daniel Vetter wrote:
On Fri, Feb 21, 2014 at 09:03:33PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Allow the driver to specify whether all new vblank requests after
drm_vblank_off() should be
On Wed, Mar 05, 2014 at 12:26:26PM +, Gupta, Sourab wrote:
Hi Chris,
Can you please through some light on the bug here, so that we're able to
handle it.
Is it about the handling required for the pread/pwrite ioctls, or is it about
the format of mentioning the testcase?
You truncate
On Wed, Mar 05, 2014 at 02:21:19PM +0200, Ville Syrjälä wrote:
On Wed, Mar 05, 2014 at 12:00:39PM +, Chris Wilson wrote:
We don't want to suffer scheduling delay when turning off the GPU after
waking it up to touch registers. Ideally, we only want to keep the GPU
awake for the register
On Fri, Feb 28, 2014 at 11:18:46AM +0530, Shobhit Kumar wrote:
MIPI Block #52 which provides configuration details for the MIPI panel
including dphy settings as per panel and tcon specs
Block #53 gives information on panel enable sequences
v2: Address review comemnts from Jani
- Move
On Thu, Feb 20, 2014 at 08:50:59PM +, Chris Wilson wrote:
On Thu, Feb 20, 2014 at 12:39:57PM -0800, Jesse Barnes wrote:
Useful for bug reports.
Hey, this would be useful for error state as well :)
I seem to have pissed of Jesse yesterday, so not going to insist here ;-)
Queued for
On Fri, Feb 21, 2014 at 06:13:51PM +0200, Mika Kuoppala wrote:
Mika Kuoppala mika.kuopp...@linux.intel.com writes:
ville.syrj...@linux.intel.com writes:
From: Ville Syrjälä ville.syrj...@linux.intel.com
If we've explicitly stopped the rings for testing purposes, don't ban
the
On Tue, Feb 25, 2014 at 03:38:18PM -0800, Ben Widawsky wrote:
On Tue, Feb 25, 2014 at 02:23:28PM +, Chris Wilson wrote:
In place of true activity counting, we walk the list of vma associated
with an object managing each on the vm's active/inactive list everytime
we call
On Wed, Feb 12, 2014 at 11:32:00AM -0800, Ben Widawsky wrote:
On Wed, Feb 12, 2014 at 07:18:19PM +, Chris Wilson wrote:
On Wed, Feb 12, 2014 at 10:55:07AM -0800, Ben Widawsky wrote:
On Wed, Feb 12, 2014 at 08:15:58AM +, Chris Wilson wrote:
Are you opposed to doing anything at
On Thu, Feb 20, 2014 at 09:26:13AM +, Chris Wilson wrote:
After a hang and failed reset, we cannot use the GPU to execute the page
flip instructions. Instead we can force a synchronous mmio flip. (Later,
we can reduce the synchronicity of the mmio flip by moving some of the
delays off to a
On Fri, Feb 21, 2014 at 04:34:29PM -0300, Paulo Zanoni wrote:
2014-02-21 14:27 GMT-03:00 Chris Wilson ch...@chris-wilson.co.uk:
On Fri, Feb 21, 2014 at 02:04:32PM -0300, Paulo Zanoni wrote:
2014-02-21 13:55 GMT-03:00 Chris Wilson ch...@chris-wilson.co.uk:
On Fri, Feb 21, 2014 at 01:52:18PM
On Fri, Feb 21, 2014 at 09:28:25AM -0800, Jesse Barnes wrote:
On Fri, 21 Feb 2014 13:52:19 -0300
Paulo Zanoni przan...@gmail.com wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Because intel_mark_idle still touches some registers: it needs the
machine to be awake. If you set both
On Wed, Mar 05, 2014 at 02:13:15PM +0100, Daniel Vetter wrote:
Just to double check: Have I merged the right version?
No conflicts or residual with my tree, so yes.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
Intel-gfx mailing
On Fri, Feb 21, 2014 at 12:16:58PM -0800, Jesse Barnes wrote:
On Fri, 21 Feb 2014 17:08:50 -0300
Paulo Zanoni przan...@gmail.com wrote:
2014-02-21 14:34 GMT-03:00 Jesse Barnes jbar...@virtuousgeek.org:
On Fri, 21 Feb 2014 13:52:20 -0300
Paulo Zanoni przan...@gmail.com wrote:
On Fri, Feb 21, 2014 at 01:52:21PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Otherwise, when we run intel_modeset_check_state we may already be
runtime suspended, and our state checking code will read registers
while the device is suspended. This can only happen
On Fri, Feb 21, 2014 at 02:46:55PM -0300, Paulo Zanoni wrote:
2014-02-21 14:41 GMT-03:00 Jesse Barnes jbar...@virtuousgeek.org:
On Fri, 21 Feb 2014 13:52:23 -0300
Paulo Zanoni przan...@gmail.com wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
These are places where we read (not
On Fri, Feb 28, 2014 at 05:11:46PM -0300, Paulo Zanoni wrote:
2014-02-28 10:50 GMT-03:00 Imre Deak imre.d...@intel.com:
On Fri, 2014-02-21 at 13:52 -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Since the addition of dev_priv-mm.busy, there's no more need for
On Wed, Mar 05, 2014 at 01:08:15PM +, Chris Wilson wrote:
On Wed, Feb 12, 2014 at 11:32:00AM -0800, Ben Widawsky wrote:
On Wed, Feb 12, 2014 at 07:18:19PM +, Chris Wilson wrote:
On Wed, Feb 12, 2014 at 10:55:07AM -0800, Ben Widawsky wrote:
On Wed, Feb 12, 2014 at 08:15:58AM
On Fri, Feb 21, 2014 at 01:52:27PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Because gen6_gt_force_wake_{get,put} should already be responsible for
getting/putting runtime PM.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
On Fri, Feb 28, 2014 at 05:16:12PM +0200, Imre Deak wrote:
On Fri, 2014-02-21 at 13:52 -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
I could swear this was already happening in the current code...
Also, put the reads and writes in a generic place, so we don't
On Wed, Mar 05, 2014 at 03:08:27PM +0200, Ville Syrjälä wrote:
On Thu, Feb 20, 2014 at 09:26:13AM +, Chris Wilson wrote:
After a hang and failed reset, we cannot use the GPU to execute the page
flip instructions. Instead we can force a synchronous mmio flip. (Later,
we can reduce the
On Wed, Mar 05, 2014 at 02:44:18PM +0100, Daniel Vetter wrote:
On Fri, Feb 28, 2014 at 05:16:12PM +0200, Imre Deak wrote:
On Fri, 2014-02-21 at 13:52 -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
I could swear this was already happening in the current code...
On Wed, Mar 05, 2014 at 02:34:48PM +0100, Daniel Vetter wrote:
On Wed, Mar 05, 2014 at 01:08:15PM +, Chris Wilson wrote:
On Wed, Feb 12, 2014 at 11:32:00AM -0800, Ben Widawsky wrote:
On Wed, Feb 12, 2014 at 07:18:19PM +, Chris Wilson wrote:
On Wed, Feb 12, 2014 at 10:55:07AM
On Wed, Feb 26, 2014 at 04:22:15PM +, Tvrtko Ursulin wrote:
On 02/21/2014 06:45 PM, Chris Wilson wrote:
[snip]
v20: Refuse to implement read-only support until we have the required
infrastructure - but reserve the bit in flags for future use.
Signed-off-by: Chris Wilson
On Wed, Mar 05, 2014 at 02:38:25PM +0200, Ville Syrjälä wrote:
On Tue, Mar 04, 2014 at 10:24:54AM +0100, Daniel Vetter wrote:
On Fri, Feb 21, 2014 at 09:03:33PM +0200, ville.syrj...@linux.intel.com
wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Allow the driver to specify
On Mon, Feb 24, 2014 at 06:37:35PM -0800, Ben Widawsky wrote:
On Mon, Feb 24, 2014 at 11:56:59AM +, joao.san...@intel.com wrote:
From: Joao Santos joao.san...@intel.com
Making libdrm and kernel drm uniform. The lack of this macro makes igt test
build break.
Change-Id:
On Mon, Feb 24, 2014 at 05:02:08PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Use the render/media specific forcewake counts to properly restore the
forcewake status after a GPU reset on VLV.
Signed-off-by: Ville Syrjälä
On Fri, Feb 28, 2014 at 04:51:16PM +0200, Ville Syrjälä wrote:
On Fri, Feb 28, 2014 at 07:56:56PM +0530, S, Deepak wrote:
On 2/28/2014 1:37 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
It occured to me that when we're trying to wake
On Mon, Feb 24, 2014 at 05:48:16PM +0200, Ville Syrjälä wrote:
On Mon, Feb 24, 2014 at 09:07:05PM +0530, sagar.a.kam...@intel.com wrote:
From: Sagar Kamble sagar.a.kam...@intel.com
Signed-off-by: Sagar Kamble sagar.a.kam...@intel.com
---
tests/kms_cursor_crc.c | 51
On Mon, Feb 24, 2014 at 07:50:49PM +, Rob Bradford wrote:
From: Rob Bradford r...@linux.intel.com
The LLC check echoes the check made by i915_gem_fault() which will
handle the mapping the pages through the GTT.
The aim is that this is functionally equivalent to using the
On Wed, Mar 05, 2014 at 01:05:29PM +, Chris Wilson wrote:
On Tue, Feb 25, 2014 at 03:38:18PM -0800, Ben Widawsky wrote:
On Tue, Feb 25, 2014 at 02:23:28PM +, Chris Wilson wrote:
In place of true activity counting, we walk the list of vma associated
with an object managing each on
The connector detect and get_mode handlers need to access the port
specific HW blocks to read the EDID etc. Get/put the port power domains
around these handlers.
v2:
- get port power domain for HDMI too (Ville)
- get port power domain for the DP,HDMI audio detect handlers (Jesse)
- Leave the
Based on an early draft from Jesse.
Add support for powering on/off the dynamic power wells on VLV by
registering its display and dpio dynamic power wells with the power
domain framework.
For now power on all PHY TX lanes regardless of the actual lane
configuration. Later this can be optimized
These functions will be needed by the valleyview specific power well
update functionality added in an upcoming patch, so move them earlier.
No functional change.
v2:
- no change
v3:
- rebase on latest -nightly
Signed-off-by: Imre Deak imre.d...@intel.com
---
Since the encoder is tied to its port, we need to make sure the power
domain for that port is on before reading out the encoder HW state.
Note that this also covers also all connector get_hw_state handlers,
since all those just call the corresponding encoder get_hw_state
handler, which checks -
On Tue, Feb 25, 2014 at 11:36:15PM -0800, Ben Widawsky wrote:
On Tue, Feb 25, 2014 at 11:27:15PM -0800, Ben Widawsky wrote:
On Tue, Feb 25, 2014 at 06:13:44PM -0800, Ben Widawsky wrote:
This patch converts insert_entries and clear_range, both functions which
are specific to the VM. These
On Wed, Mar 05, 2014 at 01:05:47PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
We have two names for the same register CHICKEN_PIPESL_1 and
HSW_PIPE_SLICE_CHICKEN_1. Unify it to just one.
Also rename the FBCQ disable bit to resemble the
On Wed, Mar 05, 2014 at 02:17:28PM +0200, Jani Nikula wrote:
BDW is no longer flagged as preliminary hw, but without
i915.preliminary_hw_support module param set the logs are filled with
WARNs about it.
Just make semaphores off the BDW per-chip default for now.
CC: Ben Widawsky
On Fri, Feb 21, 2014 at 05:32:03PM +0200, mika.kuopp...@intel.com wrote:
From: Mika Kuoppala mika.kuopp...@intel.com
As we now have intel_uncore_forcewake_reset() no need
to do explicit put after reset.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
I've merged patches 2-4 from this
On Sat, Mar 01, 2014 at 07:34:12AM +, Chris Wilson wrote:
On Fri, Feb 28, 2014 at 07:28:41PM -0300, Paulo Zanoni wrote:
2014-02-27 9:23 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
We normally use 10Khz units when describing DP link
On Mon, Mar 03, 2014 at 11:56:08AM +0200, Ville Syrjälä wrote:
On Fri, Feb 28, 2014 at 06:40:22PM -0300, Paulo Zanoni wrote:
Hi
2014-02-27 9:23 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Write some theoretical SPLL sharing support
On Thu, Feb 27, 2014 at 03:10:50PM -0800, Ben Widawsky wrote:
On Thu, Feb 27, 2014 at 09:59:03PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
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On Wed, 5 Mar 2014 13:55:00 +0100
Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Feb 20, 2014 at 08:50:59PM +, Chris Wilson wrote:
On Thu, Feb 20, 2014 at 12:39:57PM -0800, Jesse Barnes wrote:
Useful for bug reports.
Hey, this would be useful for error state as well :)
I seem to
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