[Intel-gfx] [PATCH] drm/i915: Prevent negative relocation deltas from wrapping

2014-05-23 Thread Daniel Vetter
From: Chris Wilson ch...@chris-wilson.co.uk This is pure evil. Userspace, I'm looking at you SNA, repacks batch buffers on the fly after generation as they are being passed to the kernel for execution. These batches also contain self-referenced relocations as a single buffer encompasses the state

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Fix up fifo underrun tracking, take N

2014-05-23 Thread Ville Syrjälä
On Thu, May 22, 2014 at 10:10:33PM +0200, Daniel Vetter wrote: On Thu, May 22, 2014 at 07:55:52PM +0300, Ville Syrjälä wrote: On Thu, May 22, 2014 at 05:56:32PM +0200, Daniel Vetter wrote: So apparently this is tricky. We need to consider: - We start out with all the hw enabling

Re: [Intel-gfx] [PATCH 1/4] drm/i915: also disable south interrupts when handling them

2014-05-23 Thread Daniel Vetter
On Tue, Mar 5, 2013 at 8:08 PM, Daniel Vetter dan...@ffwll.ch wrote: On Fri, Feb 22, 2013 at 05:05:28PM -0300, Paulo Zanoni wrote: From: Paulo Zanoni paulo.r.zan...@intel.com From the docs: IIR can queue up to two interrupt events. When the IIR is cleared, it will set itself again after

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Fix up fifo underrun tracking, take N

2014-05-23 Thread Daniel Vetter
On Fri, May 23, 2014 at 10:11 AM, Ville Syrjälä ville.syrj...@linux.intel.com wrote: For enabled-enabled I think that can happen in crtc_enable - we unconditionally enable underrun reporting againg to clear out old fail (or firmware setups). But we don't always disable it when disabling the

[Intel-gfx] [PATCH] drm/i915: Only copy back the modified fields to userspace from execbuffer

2014-05-23 Thread Chris Wilson
We only want to modifiy a single field in the userspace view of the execbuffer command buffer, so explicitly change that rather than copy everything back again. This serves two purposes: 1. The single fields are much cheaper to copy (constant size so the copy uses special case code) and much

Re: [Intel-gfx] [PATCH 1/3] drm/crtc: Add property for aspect ratio

2014-05-23 Thread Vandana Kannan
On May-22-2014 5:08 PM, Thierry Reding wrote: On Thu, May 22, 2014 at 04:50:48PM +0530, Vandana Kannan wrote: Added a property to enable user space to set aspect ratio. This patch contains declaration of the property and code to create the property. Signed-off-by: Vandana Kannan

Re: [Intel-gfx] [PATCH 2/3] drm/edid: Check for user aspect ratio input

2014-05-23 Thread Vandana Kannan
On May-22-2014 5:12 PM, Thierry Reding wrote: On Thu, May 22, 2014 at 04:50:49PM +0530, Vandana Kannan wrote: In case user has specified an input for aspect ratio through the property, then the user space value for PAR would take preference over the value from CEA mode list. Signed-off-by:

Re: [Intel-gfx] [PATCH 1/3] drm/crtc: Add property for aspect ratio

2014-05-23 Thread Vandana Kannan
On May-22-2014 5:46 PM, Daniel Vetter wrote: On Thu, May 22, 2014 at 04:50:48PM +0530, Vandana Kannan wrote: Added a property to enable user space to set aspect ratio. This patch contains declaration of the property and code to create the property. Signed-off-by: Vandana Kannan

Re: [Intel-gfx] [PATCH 1/4] drm/i915: also disable south interrupts when handling them

2014-05-23 Thread Paulo Zanoni
2014-05-23 5:13 GMT-03:00 Daniel Vetter dan...@ffwll.ch: On Tue, Mar 5, 2013 at 8:08 PM, Daniel Vetter dan...@ffwll.ch wrote: On Fri, Feb 22, 2013 at 05:05:28PM -0300, Paulo Zanoni wrote: From: Paulo Zanoni paulo.r.zan...@intel.com From the docs: IIR can queue up to two interrupt events.

Re: [Intel-gfx] [PATCH 1/4] drm/i915: also disable south interrupts when handling them

2014-05-23 Thread Daniel Vetter
On Fri, May 23, 2014 at 08:25:59AM -0300, Paulo Zanoni wrote: 2014-05-23 5:13 GMT-03:00 Daniel Vetter dan...@ffwll.ch: On Tue, Mar 5, 2013 at 8:08 PM, Daniel Vetter dan...@ffwll.ch wrote: On Fri, Feb 22, 2013 at 05:05:28PM -0300, Paulo Zanoni wrote: From: Paulo Zanoni

[Intel-gfx] Updated drm-intel-testing

2014-05-23 Thread Daniel Vetter
Hi all, New -testing cycle with cool stuff: - prep refactoring for execlists (Oscar Mateo) - corner-case fixes for runtime pm (Imre) - tons of vblank improvements from Ville - prep work for atomic plane/sprite updates (Ville) - more chv code, now almost complete (tons of different people) -

Re: [Intel-gfx] [PATCH] drm/i915: Only copy back the modified fields to userspace from execbuffer

2014-05-23 Thread Daniel Vetter
On Fri, May 23, 2014 at 10:45:52AM +0100, Chris Wilson wrote: We only want to modifiy a single field in the userspace view of the execbuffer command buffer, so explicitly change that rather than copy everything back again. This serves two purposes: 1. The single fields are much cheaper to

Re: [Intel-gfx] [PATCH 66/66] drm/i915: runtime PM support for DPMS

2014-05-23 Thread Paulo Zanoni
2014-04-24 18:55 GMT-03:00 Daniel Vetter daniel.vet...@ffwll.ch: Keeping track of the power domains is a bit messy since crtc-active is currently updated by the platform hooks, but we need to be aware of which state transition exactly is going on. Maybe we simply need to shovel all the power

[Intel-gfx] [PATCH 2/2] drm/i915: runtime PM support for DPMS

2014-05-23 Thread Paulo Zanoni
From: Daniel Vetter daniel.vet...@ffwll.ch Keeping track of the power domains is a bit messy since crtc-active is currently updated by the platform hooks, but we need to be aware of which state transition exactly is going on. Maybe we simply need to shovel all the power domain handling down into

[Intel-gfx] [PATCH 0/2] Enable runtime PM with DPMS on HSW

2014-05-23 Thread Paulo Zanoni
From: Paulo Zanoni paulo.r.zan...@intel.com Hi Daniel's patch series for this series still has 27 patches to be merged. Since we reached a point on the code review where we have some disagreements over the coding style, I think it is a better idea to allow people to start using the bikeshed

Re: [Intel-gfx] [RFC] drm/i915: Add variable gem object size support to i915

2014-05-23 Thread Siluvery, Arun
On 12/05/2014 18:02, Eric Anholt wrote: arun.siluv...@linux.intel.com writes: From: Siluvery, Arun arun.siluv...@intel.com This patch adds support to have gem objects of variable size. The size of the gem object obj-size is always constant and this fact is tightly coupled in the driver; this

[Intel-gfx] [PATCH 7/7] drm/i915/chv: Freq(opcode) request for CHV.

2014-05-23 Thread deepak . s
From: Deepak S deepa...@linux.intel.com On CHV, All the freq request should be even. So, we need to make sure we request the opcode accordingly. v2: Avoid vairable for freq request (ville) Signed-off-by: Deepak S deepa...@linux.intel.com Reviewed-by: Ben Widawsky b...@bwidawsk.net ---

[Intel-gfx] [PATCH 0/7] Enable RC6/Turbo on CHV

2014-05-23 Thread deepak . s
From: Deepak S deepa...@linux.intel.com Squashed some of the patches and rebased the patches on latest nightly. Deepak S (5): drm/i915/chv: Enable Render Standby (RC6) for Cherryview drm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake stuff

[Intel-gfx] [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview

2014-05-23 Thread deepak . s
From: Deepak S deepa...@linux.intel.com v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville) v3: Mass rename of the dev_priv-rps variables in upstream. v4: Rebase against latest code. (Deepak) v5: Rebase against latest nightly code. (Deepak) Signed-off-by: Deepak S

[Intel-gfx] [PATCH 4/7] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0

2014-05-23 Thread deepak . s
From: Ville Syrjälä ville.syrj...@linux.intel.com Skip __gen6_gt_wait_for_thread_c0() on CHV. Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_uncore.c | 4 ++-- 1 file changed, 2 insertions(+), 2

[Intel-gfx] [PATCH 2/7] drm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake stuff

2014-05-23 Thread deepak . s
From: Deepak S deepa...@linux.intel.com Support to individually control Media/Render well based on the register access. Add CHV specific write function to habdle difference between registers that are sadowed vs those that need forcewake even for writes. Streamline the CHV forcewake functions

[Intel-gfx] [PATCH 5/7] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV

2014-05-23 Thread deepak . s
From: Ville Syrjälä ville.syrj...@linux.intel.com CHV uses the gen8 shadow register mechanism so we shouldn't be checking the GT FIFO status. This effectively removes the posting read, so add an explicit posting read using FORCEWAKE_ACK_VLV (which is what use in vlv_forcewake_reset()).

[Intel-gfx] [PATCH 1/7] drm/i915/chv: Enable Render Standby (RC6) for Cherryview

2014-05-23 Thread deepak . s
From: Deepak S deepa...@linux.intel.com v2: Configure PCBR if BIOS fails allocate pcbr (deepak) v3: Fix PCBR condition check during CHV RC6 Enable flag set v4: Fixup PCBR comment msg. (Chris) Rebase against latest code (Deak) Fixup Spurious hunk (Ben) v5: Fix PCBR and commentis msg

[Intel-gfx] [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating

2014-05-23 Thread deepak . s
From: Deepak S deepa...@linux.intel.com Signed-off-by: Deepak S deepa...@linux.intel.com [vsyrjala: Fix merge fubmle where the code ended up in g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()] Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Acked-by: Ben Widawsky

[Intel-gfx] [v2] drm/i915: Add support for Generic MIPI panel driver

2014-05-23 Thread Shobhit Kumar
This driver makes use of the generic panel information from the VBT. Panel information is classified into two - panel configuration and panel power sequence which is unique to each panel. The generic driver uses the panel configuration and sequence parsed from VBT block #52 and #53 v2: Address

[Intel-gfx] [PATCH] drm/i915: Detect if MIPI panel based on VBT and initialize only if present

2014-05-23 Thread Shobhit Kumar
It seems by default the VBT has MIPI configuration block as well. The Generic driver will assume always MIPI if MIPI configuration block is found. This is causing probelm when actually there is eDP. Fix this by looking into general definition block which will have device configurations. From here

Re: [Intel-gfx] [PATCH] drm/i915/vlv: assert and de-assert sideband reset at boot and resume v3

2014-05-23 Thread Jesse Barnes
On Wed, 21 May 2014 20:54:03 +0300 Ville Syrjälä ville.syrj...@linux.intel.com wrote: + if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC enable) + deassert cmnreset } If those measures aren't enough, then I think this patch would be OK. But right now I have this

[Intel-gfx] [PATCH 3/6] drm/i915/vlv: move CRI refclk enable into __vlv_set_power_well

2014-05-23 Thread Jesse Barnes
This needs to be done before we power back on the CMN_BC well so the PHY can calibrate properly. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_display.c | 8 drivers/gpu/drm/i915/intel_pm.c | 11 +++ 2 files changed, 11 insertions(+),

[Intel-gfx] [PATCH 6/6] drm/i915/vlv: add pll assertion when disabling DPIO common well

2014-05-23 Thread Jesse Barnes
When doing this, all PLLs should be disabled. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_pm.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 948a4aa..452518f 100644 ---

[Intel-gfx] [PATCH 1/6] drm/i915/vlv: assert and de-assert sideband reset at boot and resume v3

2014-05-23 Thread Jesse Barnes
This is a bit like the CMN reset de-assert we do in DPIO_CTL, except that it resets the whole common lane section of the PHY. This is required on machines where the BIOS doesn't do this for us on boot or resume to properly re-calibrate and get the PHY ready to transmit data. Without this patch,

[Intel-gfx] [PATCH 2/6] drm/i915/vlv: drop power well enable in uncore_sanitize

2014-05-23 Thread Jesse Barnes
We do this at runtime and later on now. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_uncore.c | 18 -- 1 file changed, 18 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index

[Intel-gfx] [PATCH 5/6] drm/i915/vlv: move DPIO common reset de-assert into __vlv_set_power_well

2014-05-23 Thread Jesse Barnes
We need to do this anytime we power gate the DPIO common well. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_display.c | 13 drivers/gpu/drm/i915/intel_pm.c | 39 +++- 2 files changed, 30 insertions(+), 22

[Intel-gfx] [PATCH 4/6] drm/i915/vlv: re-order power wells so DPIO common comes after TX

2014-05-23 Thread Jesse Barnes
There may be a dependency here. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_pm.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e8f0c85..fb7e23e

[Intel-gfx] [PATCH] drm/i915: move psr_setup_done to psr struct

2014-05-23 Thread Rodrigo Vivi
Because our driver assumes only one panel is PSR capable, and we already have other PSR information on dev_priv instead of intel_dp. If we ever support multiple PSR panels, we'll have to move struct i915_psr to intel_dp anyway. (by Paulo) v2: Avoid more than one setup. Removing initialization

Re: [Intel-gfx] [PATCH 02/11] drm/i915: Update PSR on resume.

2014-05-23 Thread Paulo Zanoni
2014-05-15 21:13 GMT-03:00 Rodrigo Vivi rodrigo.v...@gmail.com: Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com Can you please write a little bit on the commit message explaining what is the problem with the current code? What does this patch fix? Is this a bug fix? What changes now? Thanks,

[Intel-gfx] [PATCH] drm/i915/bdw: Add Broadwell support for debugfs rps freq info

2014-05-23 Thread Tom . O'Rourke
From: Tom O'Rourke Tom.O'rou...@intel.com Add Broadwell support to i915_frequency_info and i915_max|min_freq_get|set. Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 16 +--- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git