Hi Daniel,
On Mon, 2014-08-04 at 10:07 +0200, Daniel Vetter wrote:
On Fri, Aug 01, 2014 at 12:34:56PM +0530, sagar.a.kam...@intel.com wrote:
From: Sagar Kamble sagar.a.kam...@intel.com
Sequence to get gfx clocks on/off, allow/disallow wake and save/restore of
gunit registers need to be
On Thu, Aug 07, 2014 at 01:04:19PM -0700, Rodrigo Vivi wrote:
I tested here on HSW a full sw nuke/cache clean and I didn't liked the
result.
It seems to compress less than the hw one and to recompress everything a
lot and stay less time compressed.
That is really unexpected. For a modern
On Thu, Aug 07, 2014 at 01:05:52PM -0700, Rodrigo Vivi wrote:
The rest of the series was a reference for the records of what I had and
let semaphores on bdw a bit more stable. But even with them we still get
hungs so please consider only to get the revert for now.
Thanks for the reminder,
On Mon, Aug 04, 2014 at 11:15:19AM -0700, Rodrigo Vivi wrote:
This reverts commit 521e62e49a42661a4ee0102644517dbe2f100a23.
Although POST_SYNC brought a bit of stability to Semaphores on BDW
it didn't solved all issues and some hungs can still occour when
semaphores are enabled on BDW. Also
On Fri, Aug 08, 2014 at 09:13:06AM +0200, Daniel Vetter wrote:
On Mon, Aug 04, 2014 at 11:15:19AM -0700, Rodrigo Vivi wrote:
Besides that, no real performance gain was found on our tests with different
and even multiple workloads.
That either means you didn't try hard enough, or that the
On Fri, Aug 08, 2014 at 12:22:44PM +0530, Sagar Arun Kamble wrote:
Hi Daniel,
On Mon, 2014-08-04 at 10:07 +0200, Daniel Vetter wrote:
On Fri, Aug 01, 2014 at 12:34:56PM +0530, sagar.a.kam...@intel.com wrote:
From: Sagar Kamble sagar.a.kam...@intel.com
@@ -562,7 +567,12 @@ static int
On Fri, 2014-08-08 at 09:42 +0200, Daniel Vetter wrote:
On Fri, Aug 08, 2014 at 12:22:44PM +0530, Sagar Arun Kamble wrote:
Hi Daniel,
On Mon, 2014-08-04 at 10:07 +0200, Daniel Vetter wrote:
On Fri, Aug 01, 2014 at 12:34:56PM +0530, sagar.a.kam...@intel.com wrote:
From: Sagar Kamble
On Fri, Aug 08, 2014 at 02:29:38PM +0530, Sagar Arun Kamble wrote:
On Fri, 2014-08-08 at 09:42 +0200, Daniel Vetter wrote:
On Fri, Aug 08, 2014 at 12:22:44PM +0530, Sagar Arun Kamble wrote:
Hi Daniel,
On Mon, 2014-08-04 at 10:07 +0200, Daniel Vetter wrote:
On Fri, Aug 01, 2014 at
On Fri, 2014-08-08 at 14:29 +0530, Sagar Arun Kamble wrote:
On Fri, 2014-08-08 at 09:42 +0200, Daniel Vetter wrote:
On Fri, Aug 08, 2014 at 12:22:44PM +0530, Sagar Arun Kamble wrote:
Hi Daniel,
On Mon, 2014-08-04 at 10:07 +0200, Daniel Vetter wrote:
On Fri, Aug 01, 2014 at 12:34:56PM
On Wed, Aug 06, 2014 at 10:39:16AM +0200, Daniel Vetter wrote:
On Wed, Aug 06, 2014 at 09:12:32AM +0100, Chris Wilson wrote:
On Wed, Aug 06, 2014 at 09:56:45AM +0200, Daniel Vetter wrote:
On Tue, Aug 05, 2014 at 07:51:14AM -0700, Rodrigo Vivi wrote:
From: Chris Wilson
On Tue, Jul 29, 2014 at 12:26:36PM +0200, Daniel Vetter wrote:
On Tue, Jul 29, 2014 at 08:37:48AM +0100, Chris Wilson wrote:
On Mon, Jul 28, 2014 at 10:54:06AM +0200, Daniel Vetter wrote:
On Sat, Jul 26, 2014 at 11:27:38AM +0100, Chris Wilson wrote:
On Wed, Jun 18, 2014 at 10:54:13PM
On Thu, Jul 10, 2014 at 09:53:43PM +0100, Chris Wilson wrote:
Currently objects for which the hardware needs a contiguous physical
address are allocated a shadow backing storage to satisfy the contraint.
This shadow buffer is not wired into the normal obj-pages and so the
physical object is
On Fri, Aug 08, 2014 at 10:20:40AM +0100, Chris Wilson wrote:
On Tue, Jul 29, 2014 at 12:26:36PM +0200, Daniel Vetter wrote:
On Tue, Jul 29, 2014 at 08:37:48AM +0100, Chris Wilson wrote:
On Mon, Jul 28, 2014 at 10:54:06AM +0200, Daniel Vetter wrote:
On Sat, Jul 26, 2014 at 11:27:38AM
On Tue, 29 Jul 2014, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Jul 29, 2014 at 06:14:16AM -0400, Anders Kaseorg wrote:
On Tue, 29 Jul 2014, Hans de Goede wrote:
I've been thinking a bit about this, and I believe that the right answer
here is to do the linear to logarithmic mapping in
On Fri, Aug 08, 2014 at 10:17:10AM +0100, Chris Wilson wrote:
On Wed, Aug 06, 2014 at 10:39:16AM +0200, Daniel Vetter wrote:
On Wed, Aug 06, 2014 at 09:12:32AM +0100, Chris Wilson wrote:
On Wed, Aug 06, 2014 at 09:56:45AM +0200, Daniel Vetter wrote:
On Tue, Aug 05, 2014 at 07:51:14AM
Re-adding mailing lists, please don't drop ccs like that.
On Fri, Aug 8, 2014 at 11:45 AM, Luuk van der Duim
luukvanderd...@gmail.com wrote:
I'll be happy to test your duct-tape. ;)
What branch do I need to pull? (what is its git location address?)
git://anongit.freedesktop.org/drm-intel
On Fri, Aug 08, 2014 at 11:46:07AM +0200, Daniel Vetter wrote:
On Fri, Aug 08, 2014 at 10:17:10AM +0100, Chris Wilson wrote:
On Wed, Aug 06, 2014 at 10:39:16AM +0200, Daniel Vetter wrote:
On Wed, Aug 06, 2014 at 09:12:32AM +0100, Chris Wilson wrote:
On Wed, Aug 06, 2014 at 09:56:45AM
From: Arun Siluvery arun.siluv...@linux.intel.com
In this patch workarounds for BDW are applied to golden render state.
Only those registers that are part of register state are added to this batch.
Remaining workarounds are still in its current place init_clock_gating() which
are not affected by
From: Arun Siluvery arun.siluv...@linux.intel.com
Workarounds for bdw are currently applied in init_clock_gating() but they
are lost following a gpu reset. Some of the registers are part of register
state context and they are restored with every context switch so initializing
WAs in golden render
From: Arun Siluvery arun.siluv...@linux.intel.com
Some workaround registers are part of register state context and they are
restored with every context switch so initializing them in golden render state
ensures that they are applied even when we start with an uninitialized context
or during hw
From: Arun Siluvery arun.siluv...@linux.intel.com
Currently in BDW workarounds are initialized in init_clock_gating() but
some of them are lost followed by a gpu reset. The solution is to apply
them in golden render state which keeps them valid when starting with an
uninitialized state.
First
From: Arun Siluvery arun.siluv...@linux.intel.com
Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which captures register state before and after
the test scenario.
This test currently verifies only bdw workarounds.
Signed-off-by: Arun Siluvery
On Fri, Aug 08, 2014 at 10:52:57AM +0100, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery arun.siluv...@linux.intel.com
Workarounds for bdw are currently applied in init_clock_gating() but they
are lost following a gpu reset. Some of the registers are part of register
state context
On Fri, 2014-08-08 at 11:15 +0200, Daniel Vetter wrote:
On Fri, Aug 08, 2014 at 02:29:38PM +0530, Sagar Arun Kamble wrote:
On Fri, 2014-08-08 at 09:42 +0200, Daniel Vetter wrote:
On Fri, Aug 08, 2014 at 12:22:44PM +0530, Sagar Arun Kamble wrote:
Hi Daniel,
On Mon, 2014-08-04 at 10:07
On 08/08/2014 10:57, Chris Wilson wrote:
On Fri, Aug 08, 2014 at 10:52:57AM +0100, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery arun.siluv...@linux.intel.com
Workarounds for bdw are currently applied in init_clock_gating() but they
are lost following a gpu reset. Some of the
Hi
On Wed, Aug 6, 2014 at 9:10 AM, Daniel Vetter daniel.vet...@ffwll.ch wrote:
The current refcounting scheme is that the fb lookup idr also holds a
reference. This works out nicely bacause thus far we've always
explicitly cleaned up idr entries for framebuffers:
- Userspace fbs get removed
On Fri, Aug 08, 2014 at 11:34:07AM +0100, Siluvery, Arun wrote:
On 08/08/2014 10:57, Chris Wilson wrote:
On Fri, Aug 08, 2014 at 10:52:57AM +0100, arun.siluv...@linux.intel.com
wrote:
From: Arun Siluvery arun.siluv...@linux.intel.com
Workarounds for bdw are currently applied in
From: Sonika Jindal sonika.jin...@intel.com
Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.
Done using following cocci patch for each define:
@@
@@
# define
From: Sonika Jindal sonika.jin...@intel.com
Adding new defines, older one will be removed in the last patch in the series.
This is to rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the
From: Sonika Jindal sonika.jin...@intel.com
Rename the defines to have levels instead of values for vswing and pre-emph
levels as the values may differ in other scenarios like low vswing of eDP 1.4
where the values are different.
Updated in all the drivers as well
v2: Keeping the old defines in
From: Sonika Jindal sonika.jin...@intel.com
Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.
Done using following cocci patch for each define:
@@
@@
# define
From: Sonika Jindal sonika.jin...@intel.com
Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.
Done using following cocci patch for each define:
@@
@@
# define
From: Sonika Jindal sonika.jin...@intel.com
This is the last patch in the series, so remove old defines
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
include/drm/drm_dp_helper.h |8
1 file changed, 8 deletions(-)
diff --git a/include/drm/drm_dp_helper.h
From: Sonika Jindal sonika.jin...@intel.com
Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.
Done using following cocci patch for each define:
@@
@@
# define
From: Sonika Jindal sonika.jin...@intel.com
Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.
Done using following cocci patch for each define:
@@
@@
# define
On Fri, 2014-08-08 at 15:54 +0530, Sagar Arun Kamble wrote:
On Fri, 2014-08-08 at 11:15 +0200, Daniel Vetter wrote:
On Fri, Aug 08, 2014 at 02:29:38PM +0530, Sagar Arun Kamble wrote:
On Fri, 2014-08-08 at 09:42 +0200, Daniel Vetter wrote:
On Fri, Aug 08, 2014 at 12:22:44PM +0530, Sagar
From: Sonika Jindal sonika.jin...@intel.com
Removing the check for HAS_PCH_SPLIT, it looks redundant here. Anyways all the
platforms are checked separately.
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 40 --
1
On Fri, Aug 08, 2014 at 05:09:14PM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
Removing the check for HAS_PCH_SPLIT, it looks redundant here. Anyways all the
platforms are checked separately.
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
On Fri, Aug 08, 2014 at 10:52:57AM +0100, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery arun.siluv...@linux.intel.com
Workarounds for bdw are currently applied in init_clock_gating() but they
are lost following a gpu reset. Some of the registers are part of register
state context
From: Sonika Jindal sonika.jin...@intel.com
Renaming the HSW-specific macros for ddi buffer translation slot to denote the
slot and not the vswing/pre-emph values as they are platform-dependent.
This patch is based on top of the patch series for renaming the DP training
vswing/pre-emph defines:
On Fri, Aug 08, 2014 at 05:47:25PM +0530, sonika.jin...@intel.com wrote:
/* Start the training iterating through available voltages and emphasis,
* testing each value twice. */
- for (i = 0; i ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
+ for (i = 0; i
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch]
Sent: Wednesday, August 06, 2014 2:05 PM
To: Intel Graphics Development
Cc: Daniel Vetter; Thierry, Michel; Chris Wilson
Subject: [PATCH 02/15] drm/i915: Some cleanups for the ppgtt lifetime
handling
So when
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of Daniel Vetter
Sent: Wednesday, August 06, 2014 2:05 PM
To: Intel Graphics Development
Cc: Daniel Vetter
Subject: [Intel-gfx] [PATCH 05/15] drm/i915: Only refcount ppgtt if it
actually
On Thu, Aug 07, 2014 at 06:40:03PM +0530, Vandana Kannan wrote:
From: Vidya Srinivas vidya.srini...@intel.com
PFI credit programming is required when CD clock (related to data flow from
display pipeline to end display) is greater than CZ clock (related to data
flow from memory to display
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of Daniel Vetter
Sent: Wednesday, August 06, 2014 2:05 PM
To: Intel Graphics Development
Cc: Daniel Vetter
Subject: [Intel-gfx] [PATCH 08/15] drm/i915: Fix up checks for aliasing
ppgtt
A
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch]
Sent: Wednesday, August 06, 2014 7:20 PM
To: Intel Graphics Development
Cc: Daniel Vetter; Thierry, Michel; Ville Syrjälä
Subject: [PATCH 2/2] drm/i915: Initialize the aliasing ppgtt as part of
global gtt
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of Daniel Vetter
Sent: Wednesday, August 06, 2014 2:05 PM
To: Intel Graphics Development
Cc: Daniel Vetter
Subject: [Intel-gfx] [PATCH 11/15] drm/i915: Drop create_vm argument to
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of Daniel Vetter
Sent: Wednesday, August 06, 2014 2:05 PM
To: Intel Graphics Development
Cc: Daniel Vetter
Subject: [Intel-gfx] [PATCH 12/15] drm/i915: Extract common cleanup into
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of Daniel Vetter
Sent: Wednesday, August 06, 2014 2:05 PM
To: Intel Graphics Development
Cc: Daniel Vetter
Subject: [Intel-gfx] [PATCH 14/15] drm/i915: Cleanup aliasging ppgtt
alongside
The driver will no longer initialize the aliasing ppgtt if we have
full ppgtt enabled.
gen8_ppgtt_info uses the aliasing ppgtt or the ppgtt from the
default context. This patch makes it clear.
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of Daniel Vetter
Sent: Wednesday, August 06, 2014 2:05 PM
To: Intel Graphics Development
Cc: Daniel Vetter
Subject: [Intel-gfx] [PATCH 13/15] drm/i915: Extract commmon global gtt
cleanup
On 08/08/2014 13:20, Ville Syrjälä wrote:
On Fri, Aug 08, 2014 at 10:52:57AM +0100, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery arun.siluv...@linux.intel.com
Workarounds for bdw are currently applied in init_clock_gating() but they
are lost following a gpu reset. Some of the
Adding relevant mailing lists.
On Fri, Aug 8, 2014 at 1:23 PM, Juergen Gross jgr...@suse.com wrote:
I'm just about to create a patch for full PAT support in the Linux
kernel, including Xen. For this purpose I introduce a translation
between cache modes and pte bits.
Scanning the kernel
On Fri, Aug 8, 2014 at 12:35 PM, David Herrmann dh.herrm...@gmail.com wrote:
Ewww, this is ugly. You now make the unregistration dynamic and it's
no longer under driver control. The typical device-control flow
assumes there's an authority that controls at which point objects are
registered and
On Mon, 07 Jul 2014, Paul Livingston p...@accokeekwoods.com wrote:
I recently built a new desktop machine using a Shuttle SZ87R6, an I7-4770S
and a Dell U2713HM monitor. Did my initial HW burn-in and testing using a
Fedora 20 KDE Spin Live CD (Kernel 3.11.10-301.fc20.x86_64 KDE Systems
On Fri, Aug 08, 2014 at 11:37:01AM +0200, Daniel Vetter wrote:
On Fri, Aug 08, 2014 at 10:20:40AM +0100, Chris Wilson wrote:
On Tue, Jul 29, 2014 at 12:26:36PM +0200, Daniel Vetter wrote:
On Tue, Jul 29, 2014 at 08:37:48AM +0100, Chris Wilson wrote:
On Mon, Jul 28, 2014 at 10:54:06AM
On Fri, Aug 08, 2014 at 02:34:37PM +0300, Imre Deak wrote:
On Fri, 2014-08-08 at 15:54 +0530, Sagar Arun Kamble wrote:
On Fri, 2014-08-08 at 11:15 +0200, Daniel Vetter wrote:
On Fri, Aug 08, 2014 at 02:29:38PM +0530, Sagar Arun Kamble wrote:
On Fri, 2014-08-08 at 09:42 +0200, Daniel
On Fri, Aug 08, 2014 at 02:10:32PM +0100, Michel Thierry wrote:
The driver will no longer initialize the aliasing ppgtt if we have
full ppgtt enabled.
gen8_ppgtt_info uses the aliasing ppgtt or the ppgtt from the
default context. This patch makes it clear.
Cc: Daniel Vetter
On Fri, Aug 08, 2014 at 01:03:53PM +, Thierry, Michel wrote:
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of Daniel Vetter
Sent: Wednesday, August 06, 2014 2:05 PM
To: Intel Graphics Development
Cc: Daniel Vetter
Subject:
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Friday, August 08, 2014 2:49 PM
To: Thierry, Michel
Cc: Daniel Vetter; Intel Graphics Development
Subject: Re: [Intel-gfx] [PATCH 08/15] drm/i915: Fix up checks for
aliasing
Gn Fri, Aug 08, 2014 at 03:43:49PM +0200, Daniel Vetter wrote:
On Fri, Aug 08, 2014 at 02:34:37PM +0300, Imre Deak wrote:
On Fri, 2014-08-08 at 15:54 +0530, Sagar Arun Kamble wrote:
On Fri, 2014-08-08 at 11:15 +0200, Daniel Vetter wrote:
On Fri, Aug 08, 2014 at 02:29:38PM +0530, Sagar
Daniel Vetter schreef op vr 08-08-2014 om 11:47 [+0200]:
Re-adding mailing lists, please don't drop ccs like that.
I sincerely apologize. I seriously have no idea why I assumed a dance
for two.
On Fri, Aug 8, 2014 at 11:45 AM, Luuk van der Duim
luukvanderd...@gmail.com wrote:
I'll be
On Fri, Aug 08, 2014 at 10:54:56AM +0100, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery arun.siluv...@linux.intel.com
Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which captures register state before and after
the test scenario.
On Fri, Aug 08, 2014 at 02:55:10PM +0300, Ville Syrjälä wrote:
On Fri, Aug 08, 2014 at 05:09:14PM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
Removing the check for HAS_PCH_SPLIT, it looks redundant here. Anyways all
the
platforms are checked
On Fri, Aug 08, 2014 at 04:09:30PM +0200, Luuk van der Duim wrote:
Daniel Vetter schreef op vr 08-08-2014 om 11:47 [+0200]:
Re-adding mailing lists, please don't drop ccs like that.
I sincerely apologize. I seriously have no idea why I assumed a dance
for two.
On Fri, Aug 8, 2014
Hi Dave,
So I heard that proper pull requests have a revert on top ;-) So here we
go with my usual mid-merge-window pile of fixes.
Big fix is the duct-tape for ring init on g4x platforms, we seem to have
found the magic again to make those machines as happy as before (not
perfect though
https://bugs.freedesktop.org/show_bug.cgi?id=80229
We can reproduce this GPU hang here after an hours or so of
testing.
If there are anything I can do to help debug this please let me
know.
Barry
___
Intel-gfx mailing list
New Intel G3258 CPU, new MSI board, same problem:
The GPU interrupt fired like crazy on monitor unplug.
lspci output:
00:02.0 VGA compatible controller: Intel Corporation Device 0402 (rev 06)
Subsystem: Micro-Star International Co., Ltd. Device 7817
Flags: bus master, fast devsel,
On Fri, Aug 08, 2014 at 03:54:04PM +0200, Thomas Jarosch wrote:
New Intel G3258 CPU, new MSI board, same problem:
The GPU interrupt fired like crazy on monitor unplug.
lspci output:
00:02.0 VGA compatible controller: Intel Corporation Device 0402 (rev 06)
Subsystem: Micro-Star
On Thu, Aug 07, 2014 at 03:15:32PM +0100, Chris Wilson wrote:
On Thu, Aug 07, 2014 at 04:07:59PM +0200, Daniel Vetter wrote:
Doing a 1s wait (tops) with the cpu is a bit excessive. Tune it down
like everything else in that code.
Cc: Naresh Kumar Kachhi naresh.kumar.kac...@intel.com
Cc:
On Thu, Aug 07, 2014 at 01:24:26PM +0100, Thomas Daniel wrote:
From: Ben Widawsky b...@bwidawsk.net
This has turned out to be really handy in debug so far.
Update:
Since writing this patch, I've gotten similar code upstream for error
state. I've used it quite a bit in debugfs however, and
On Thu, Aug 07, 2014 at 01:17:40PM +0100, Thomas Daniel wrote:
From: Oscar Mateo oscar.ma...@intel.com
This is mostly for correctness so that we know we are running the LR
context correctly (this is, the PDPs are contained inside the context
object).
v2: Move the check to inside the
On Thu, Aug 07, 2014 at 01:23:20PM +0100, Thomas Daniel wrote:
From: Oscar Mateo oscar.ma...@intel.com
v2: Warn and return if LRCs are not enabled.
v3: Grab the Execlists spinlock (noticed by Daniel Vetter).
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
v4: Lock the struct mutex
On 08/08/2014 15:12, Daniel Vetter wrote:
On Fri, Aug 08, 2014 at 10:54:56AM +0100, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery arun.siluv...@linux.intel.com
Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which captures register
On Fri, Aug 8, 2014 at 6:39 PM, Siluvery, Arun
arun.siluv...@linux.intel.com wrote:
The suspend test doesn't seem to be wire up ...
Also I think it would be worth to have a module-reload version here too.
Suspend/Resume is not working; device is not resuming even after the timer
is elapsed.
adj was defined as u8. The issue is last_adj can be negative and adj is
initialized with:
adj = dev_priv-rps.last_adj;
and we were also happily doing things like:
if (adj 0)
(thank static analysers!)
Cc: Deepak S deepa...@linux.intel.com
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
On Fri, Aug 08, 2014 at 06:34:48PM +0100, Damien Lespiau wrote:
adj was defined as u8. The issue is last_adj can be negative and adj is
initialized with:
adj = dev_priv-rps.last_adj;
and we were also happily doing things like:
if (adj 0)
(thank static analysers!)
Cc: Deepak S
adj was defined as u8. The issue is last_adj can be negative and adj is
initialized with:
adj = dev_priv-rps.last_adj;
and we were also happily doing things like:
if (adj 0)
(thank static analysers!)
v2: Make new_delay an int in case we overflow the u8 in the intermediate
We treat other plane updates in the same fashion. Spotted because
Rodrigo kept reporting a bug in the PSR code where the frontbuffer was
eternally stuck with a dirty cursor bit set.
The psr testcase should have caught this, but that i-g-t is kaputt.
Rodrigo is signed up to fix that.
Cc: Rodrigo
Requested by Chris, and also requested to keep it since it's a
more accurate name in his opinion.
Cc: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_display.c | 13 -
drivers/gpu/drm/i915/intel_drv.h | 6
On Fri, Aug 08, 2014 at 07:25:57PM +0100, Damien Lespiau wrote:
adj was defined as u8. The issue is last_adj can be negative and adj is
initialized with:
adj = dev_priv-rps.last_adj;
and we were also happily doing things like:
if (adj 0)
(thank static analysers!)
v2: Make
On Fri, Aug 08, 2014 at 08:28:48PM +0200, Daniel Vetter wrote:
Requested by Chris, and also requested to keep it since it's a
more accurate name in his opinion.
Cc: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Reviewed-by: Chris Wilson
Hi all,
First -testing cycle for 3.18 already:
- Setting dp M2/N2 values plus state checker support (Vandana Kannan)
- chv power well support (Ville)
- DP training pattern 3 support for chv (Ville)
- cleanup of the hsw/bdw ddi pll code, prep work for skl (Damien)
- dsi video burst mode support
From: Ville Syrjälä ville.syrj...@linux.intel.com
Move the entire DSPCNTR register setup into the .update_primary_plane()
functions. That's where it belongs anyway and it'll also help 830M which
has the extra problem that plane registers reads will return the value
latched at the last vblank, not
On Fri, Aug 08, 2014 at 09:51:10PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Move the entire DSPCNTR register setup into the .update_primary_plane()
functions. That's where it belongs anyway and it'll also help 830M which
has the extra
From: Ville Syrjälä ville.syrj...@linux.intel.com
Make the intel_{enable,disable}_primary_hw_plane() simply call
.update_primary_plane(), thus eliminating the rmw from these functions
which should help the poor old 830M.
Now we can also remove the .update_primary_plane() from the
.crtc_enable()
On Fri, Aug 08, 2014 at 09:32:20PM +0300, Ville Syrjälä wrote:
On Fri, Aug 08, 2014 at 07:25:57PM +0100, Damien Lespiau wrote:
adj was defined as u8. The issue is last_adj can be negative and adj is
initialized with:
adj = dev_priv-rps.last_adj;
and we were also happily doing
On Fri, Aug 08, 2014 at 09:51:11PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Make the intel_{enable,disable}_primary_hw_plane() simply call
.update_primary_plane(), thus eliminating the rmw from these functions
which should help the poor
On Fri, Aug 8, 2014 at 7:34 AM, Daniel Vetter daniel.vet...@ffwll.ch wrote:
git://anongit.freedesktop.org/drm-intel tags/drm-intel-fixes-2014-08-08
Hmm. My laptop no longer resumes properly.
Or rather, I suspect it resumes, but the screen is black.
I will bisect, and I *will* revert if I
On Fri, Aug 8, 2014 at 12:19 PM, Linus Torvalds
torva...@linux-foundation.org wrote:
On Fri, Aug 8, 2014 at 7:34 AM, Daniel Vetter daniel.vet...@ffwll.ch wrote:
git://anongit.freedesktop.org/drm-intel tags/drm-intel-fixes-2014-08-08
Hmm. My laptop no longer resumes properly.
The problem
On Fri, Aug 8, 2014 at 12:37 PM, Linus Torvalds
torva...@linux-foundation.org wrote:
The problem seems to exist already with just the plain drm pull from
Dave. I thought I had tested that, but apparently not.
Still busy bisecting (and it's going into the i915 part of Dave's drm
pull, so the
From: Paulo Zanoni paulo.r.zan...@intel.com
Currently, if the machine is runtime suspended an you read the file,
you will get an Unclaimed register error message.
Testcase: igt/pm_rpm/debugfs-read
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 6
On Fri, Aug 8, 2014 at 10:30 AM, Linus Torvalds
torva...@linux-foundation.org wrote:
This is a Sony Vaio Pro 11, so it's bog-standard intel graphics (Haswell ULT).
Got this while bisecting. I'm not sure it's related, the behavior was
a bit different from the other cases. So I'll try to continue
On Fri, Aug 8, 2014 at 1:52 PM, Linus Torvalds
torva...@linux-foundation.org wrote:
Got this while bisecting. I'm not sure it's related
It's not.
The actual bug was panel self refresh. It's still broken, and doesn't
work. So enabling it by default was a big mistake (commit
b6d547791fd3:
On Friday, August 08, 2014 11:37:01 AM Daniel Vetter wrote:
On Fri, Aug 08, 2014 at 10:20:40AM +0100, Chris Wilson wrote:
On Tue, Jul 29, 2014 at 12:26:36PM +0200, Daniel Vetter wrote:
On Tue, Jul 29, 2014 at 08:37:48AM +0100, Chris Wilson wrote:
On Mon, Jul 28, 2014 at 10:54:06AM +0200,
On Friday, August 08, 2014 06:41:10 AM Greg KH wrote:
On Fri, Aug 08, 2014 at 11:37:01AM +0200, Daniel Vetter wrote:
On Fri, Aug 08, 2014 at 10:20:40AM +0100, Chris Wilson wrote:
On Tue, Jul 29, 2014 at 12:26:36PM +0200, Daniel Vetter wrote:
On Tue, Jul 29, 2014 at 08:37:48AM +0100,
On Fri, Aug 08, 2014 at 03:47:54PM +0200, Daniel Vetter wrote:
On Fri, Aug 08, 2014 at 02:10:32PM +0100, Michel Thierry wrote:
The driver will no longer initialize the aliasing ppgtt if we have
full ppgtt enabled.
gen8_ppgtt_info uses the aliasing ppgtt or the ppgtt from the
default
From: Rodrigo Vivi rodrigo.v...@gmail.com
Some registers set during setup might not be persistent after suspend/resume.
This was causing bugs for some people that was unable to get PSR entry state
after resume cycle.
v2: Adding some comments and better commit message explaining why this is
On Sat, 9 Aug 2014, Rafael J. Wysocki wrote:
Well it works currently. So where do you see the problem?
Sampling registers from an timer - in particular, we really do not want
to disable runtime pm whilst trying to monitor the impact of runtime pm.
In that case you can grab a
99 matches
Mail list logo
