Hi,
Did anybody get a chance to review the patches?
Adding respective owners for different drivers..
Thanks,
Sonika
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Jindal, Sonika
Sent: Tuesday, August 19, 2014 1:42 PM
To:
On Mon, Aug 25, 2014 at 02:47:17PM +0100, Chris Wilson wrote:
On Mon, Aug 25, 2014 at 04:24:56PM +0300, Ville Syrjälä wrote:
On Mon, Aug 25, 2014 at 01:28:11PM +0100, Chris Wilson wrote:
Pineview requires this. But this changes the debug API...
References:
On Mon, Aug 25, 2014 at 10:58:44AM -0700, Rodrigo Vivi wrote:
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
tests/pm_psr.c | 27 ---
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/tests/pm_psr.c b/tests/pm_psr.c
index 3ab7e7a..8b92d84 100644
On Tue, Aug 26, 2014 at 10:42:51AM -0700, vedang.pa...@intel.com wrote:
From: Vedang Patel vedang.pa...@intel.com
The patch introduces fixes for the debugfs attributes emitted by
the i915 driver for GEN8. Currently, it is not emitting the correct
attributes which include the status of RC6
On 26.08.2014 22:51, Daniel Vetter wrote:
Oliver, can you please test the below diff?
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index f19dbff0e73b..915a60b48159 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@
Le 18/08/2014 01:09, Rémi Cardona a écrit :
Not all locales on linux are UTF-8, the most notable being the C locale.
Python will use the ASCII codec for stream IO in this case and will barf
on the Copyright sign at the top of .g4a files.
Bugzilla:
Dear Charles,
thanks a lot for following up on the intel-gfx mailing list.
Am Dienstag, den 26.08.2014, 13:09 -0400 schrieb Charles Devereaux:
I'm trying to use i915.fastboot on a Thinkpad X60t. The bios has been
replaced by coreboot, which supports native video init.
The goal is to boot
From: Akash Goel akash.g...@intel.com
Added a new drm crtc property which provides control
to vary the Pipe Src or Crtc size.
With this, User can flip the frame buffers of resolution, which
is different from the currently selected mode. For this Driver will
appropriately enable the Panel fitter
On Tue, Aug 26, 2014 at 01:28:19PM +0200, Thierry Reding wrote:
On Fri, Aug 08, 2014 at 04:23:40PM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
Adding new defines, older one will be removed in the last patch in the
series.
This is to rename the
On Wed, Aug 27, 2014 at 08:47:54AM +0100, Damien Lespiau wrote:
An alternative would be to provide a second set of defines for eDP 1.4
where the name implies the meaning and then use them as appropriate.
We went through the idea as well and:
I actually think the nominal voltage swing and
On Mon, Aug 18, 2014 at 01:09:15AM +0200, Rémi Cardona wrote:
Not all locales on linux are UTF-8, the most notable being the C locale.
Python will use the ASCII codec for stream IO in this case and will barf
on the Copyright sign at the top of .g4a files.
Bugzilla:
A bunch of warnings fire on some -irq_postinstall hooks since those
can enable interrupts (e.g. rps interrupts). And then our ordering
self-checks fire and complain.
To fix that set the tracking boolen before enabling the irqs with
drm_irq_install. Quoting the discussion with Jesse why that's
Now that vlv has runtime pm we kinda should check for that like on the
pch split platforms. Looks like this was simply lost in the vlv rpm
enabling.
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Cc: Imre Deak imre.d...@intel.com
Cc: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Daniel Vetter
On Wed, Aug 27, 2014 at 10:43:37AM +0200, Daniel Vetter wrote:
Now that vlv has runtime pm we kinda should check for that like on the
pch split platforms. Looks like this was simply lost in the vlv rpm
enabling.
Is there a reason why setting up the pipestat prior to enabling
interrupts is
On Wed, Aug 27, 2014 at 10:11:34AM +0200, Daniel Vetter wrote:
A bunch of warnings fire on some -irq_postinstall hooks since those
can enable interrupts (e.g. rps interrupts). And then our ordering
self-checks fire and complain.
To fix that set the tracking boolen before enabling the irqs
On Tue, 26 Aug 2014, Charles Devereaux intel...@guylhem.net wrote:
The kernel arguments are:
i915.semaphores=1 i915.i915_enable_rc6=7 i915.i915_enable_fbc=1
Side note #1, these parameters are for testing and debugging only, and
it is recommended to stick to the platform specific defaults. We'll
On Tue, Aug 26, 2014 at 04:00:51PM -0700, Eric Rannaud wrote:
On Tue, Aug 26, 2014 at 1:59 PM, Daniel Vetter daniel.vet...@ffwll.ch wrote:
Forcing FBC with i915.enable_fbc=1 brings the idle power consumption
back to under 7W, however.
This is all on 3.15.4-ARCH-00041-gf4db98240ac2.
Any
On Tue, Aug 12, 2014 at 08:05:51PM +0100, Chris Wilson wrote:
At the heart of this change is that the seqno is a too low level of an
abstraction to handle the growing complexities of command tracking, both
with the introduction of multiple command queues with execbuffer and the
potential for
On Wed, Aug 27, 2014 at 08:12:23AM +0200, Daniel Vetter wrote:
On Mon, Aug 25, 2014 at 02:47:17PM +0100, Chris Wilson wrote:
On Mon, Aug 25, 2014 at 04:24:56PM +0300, Ville Syrjälä wrote:
On Mon, Aug 25, 2014 at 01:28:11PM +0100, Chris Wilson wrote:
Pineview requires this. But this
On Wed, Aug 27, 2014 at 09:51:58AM +0100, Chris Wilson wrote:
On Wed, Aug 27, 2014 at 10:43:37AM +0200, Daniel Vetter wrote:
Now that vlv has runtime pm we kinda should check for that like on the
pch split platforms. Looks like this was simply lost in the vlv rpm
enabling.
Is there a
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f886922..1d6d9ac 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++
Instead of going through hoops, just put the driver author directly as
DRM_AUTHOR() argument. This will also make it consistent when we add
Intel to the list.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 3 ++-
drivers/gpu/drm/i915/i915_drv.h | 2
On Wed, Aug 27, 2014 at 11:55:34AM +0200, Daniel Vetter wrote:
On Tue, Aug 12, 2014 at 08:05:51PM +0100, Chris Wilson wrote:
At the heart of this change is that the seqno is a too low level of an
abstraction to handle the growing complexities of command tracking, both
with the introduction
Previously, it was possible for the GPU memory accesses to be swizzled
to try to optimize the fetches for tiled buffers. This swizzling was on
top of what the memory controller in the uncore already does.
With broadwell, we drop that GPU side swizzling, and the corresponding
initialization in 3
On Wed, 27 Aug 2014, Damien Lespiau damien.lesp...@intel.com wrote:
Instead of going through hoops, just put the driver author directly as
DRM_AUTHOR() argument. This will also make it consistent when we add
Intel to the list.
Reviewed-by: Jani Nikula jani.nik...@intel.com
Signed-off-by:
Reviewed-by: Jani Nikula jani.nik...@intel.com
On Wed, 27 Aug 2014, Damien Lespiau damien.lesp...@intel.com wrote:
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c
On Tue, 26 Aug 2014, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 26, 2014 at 04:15:53PM +, Scot Doyle wrote:
On Tue, 26 Aug 2014, Daniel Vetter wrote:
On Thu, Aug 21, 2014 at 07:12:59AM +, Scot Doyle wrote:
When we enter intel_modeset_setup_hw_state during resume
-
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0b504c4ce73b..74a59b3e3bde 100644
---
On Wed, Aug 27, 2014 at 11:30:21AM +0100, Damien Lespiau wrote:
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index
On Fri, Aug 08, 2014 at 01:36:17PM +0100, Damien Lespiau wrote:
On Fri, Aug 08, 2014 at 05:47:25PM +0530, sonika.jin...@intel.com wrote:
/* Start the training iterating through available voltages and emphasis,
* testing each value twice. */
- for (i = 0; i
On Wed, Aug 27, 2014 at 11:51:59AM +0100, Damien Lespiau wrote:
Previously, it was possible for the GPU memory accesses to be swizzled
to try to optimize the fetches for tiled buffers. This swizzling was on
top of what the memory controller in the uncore already does.
With broadwell, we drop
On Wed, Aug 27, 2014 at 02:08:43PM +0300, Jani Nikula wrote:
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index
On Wed, Aug 27, 2014 at 02:16:13PM +0300, Ville Syrjälä wrote:
On Fri, Aug 08, 2014 at 01:36:17PM +0100, Damien Lespiau wrote:
On Fri, Aug 08, 2014 at 05:47:25PM +0530, sonika.jin...@intel.com wrote:
/* Start the training iterating through available voltages and emphasis,
* testing
On Wed, Aug 27, 2014 at 12:23:47PM +0200, Daniel Vetter wrote:
On Wed, Aug 27, 2014 at 09:51:58AM +0100, Chris Wilson wrote:
On Wed, Aug 27, 2014 at 10:43:37AM +0200, Daniel Vetter wrote:
Now that vlv has runtime pm we kinda should check for that like on the
pch split platforms. Looks
Hello Damien Lespiau,
The patch a26aa8baee6c: drm/i915/bdw: Provide the BDW specific HDMI
buffer translation table from Aug 1, 2014, leads to the following
static checker warning:
drivers/gpu/drm/i915/intel_ddi.c:225 intel_prepare_ddi_buffers()
error: buffer overflow
On Wed, Aug 27, 2014 at 08:51:35AM +0100, Damien Lespiau wrote:
On Wed, Aug 27, 2014 at 08:47:54AM +0100, Damien Lespiau wrote:
An alternative would be to provide a second set of defines for eDP 1.4
where the name implies the meaning and then use them as appropriate.
We went through
On Wed, Aug 27, 2014 at 08:47:54AM +0100, Damien Lespiau wrote:
On Tue, Aug 26, 2014 at 01:28:19PM +0200, Thierry Reding wrote:
On Fri, Aug 08, 2014 at 04:23:40PM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
Adding new defines, older one will be
On Wed, Aug 27, 2014 at 04:04:46PM +0300, Dan Carpenter wrote:
Hello Damien Lespiau,
The patch a26aa8baee6c: drm/i915/bdw: Provide the BDW specific HDMI
buffer translation table from Aug 1, 2014, leads to the following
static checker warning:
drivers/gpu/drm/i915/intel_ddi.c:225
Try to avoid confusion with ARRAY_SIZE()/2 and hdmi_level*2.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
This is on top of nightly; I can respin this on top of Sonika's patch
after that gets merged.
BR,
Jani.
---
drivers/gpu/drm/i915/intel_ddi.c | 181
On Wed, Aug 27, 2014 at 1:28 PM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, Aug 27, 2014 at 12:23:47PM +0200, Daniel Vetter wrote:
On Wed, Aug 27, 2014 at 09:51:58AM +0100, Chris Wilson wrote:
On Wed, Aug 27, 2014 at 10:43:37AM +0200, Daniel Vetter wrote:
Now that vlv has runtime
On Mon, Aug 11, 2014 at 08:57:36AM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
Renaming the HSW-specific macros for ddi buffer translation slot to denote the
slot and not the vswing/pre-emph values as they are platform-dependent.
This patch is based on
On Wed, Aug 27, 2014 at 04:27:30PM +0300, Jani Nikula wrote:
/* Entry 9 is for HDMI: */
for (i = 0; i 2; i++) {
- I915_WRITE(reg, ddi_translations_hdmi[hdmi_level * 2 + i]);
+ I915_WRITE(reg, ddi_translations_hdmi[hdmi_level + i].trans1);
+ reg
On Wed, Aug 27, 2014 at 04:27:30PM +0300, Jani Nikula wrote:
Try to avoid confusion with ARRAY_SIZE()/2 and hdmi_level*2.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
This is on top of nightly; I can respin this on top of Sonika's patch
after that gets merged.
Resolved myself
From: Ville Syrjälä ville.syrj...@linux.intel.com
During driver init we may not have a valid framebuffer for the primary
plane even though the plane is enabled due to failed BIOS fb takeover.
This means we have to avoid dereferencing the fb in
.update_primary_plane() when disabling the plane.
From: Ville Syrjälä ville.syrj...@linux.intel.com
Use the pixel_size we got from drm_format_plane_cpp() instead of
fb-bits_per_pixel/8 when computing the primary plane page/linear
offsets. Avoids a few divs and makes the code more future proof
against funky pixel formats where bits_per_pixel
On Wed, Aug 27, 2014 at 02:47:05PM +0100, Damien Lespiau wrote:
On Wed, Aug 27, 2014 at 04:27:30PM +0300, Jani Nikula wrote:
/* Entry 9 is for HDMI: */
for (i = 0; i 2; i++) {
- I915_WRITE(reg, ddi_translations_hdmi[hdmi_level * 2 + i]);
+ I915_WRITE(reg,
-Original Message-
From: Jindal, Sonika [mailto:sonika.jin...@intel.com]
Sent: Wednesday, August 27, 2014 2:09 AM
To: Jindal, Sonika; intel-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org; kgene@samsung.com;
jg1@samsung.com; airl...@linux.ie; Deucher, Alexander;
On Wed, Aug 27, 2014 at 04:51:22PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Use the pixel_size we got from drm_format_plane_cpp() instead of
fb-bits_per_pixel/8 when computing the primary plane page/linear
offsets. Avoids a few divs and
On Wed, Aug 27, 2014 at 04:51:21PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
During driver init we may not have a valid framebuffer for the primary
plane even though the plane is enabled due to failed BIOS fb takeover.
This means we have to
From: Ville Syrjälä ville.syrj...@linux.intel.com
Follow the BDW example and apply the workarounds touching registers
which are saved in the context image through LRIs in the new
ring-init_context() hook.
This makes Mesa much happier and eg. glxgears doesn't hang after
the first frame.
Cc: Arun
From: Ville Syrjälä ville.syrj...@linux.intel.com
During driver init we may not have a valid framebuffer for the primary
plane even though the plane is enabled due to failed BIOS fb takeover.
This means we have to avoid dereferencing the fb in
.update_primary_plane() when disabling the plane.
On Wed, Aug 27, 2014 at 05:33:12PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Follow the BDW example and apply the workarounds touching registers
which are saved in the context image through LRIs in the new
ring-init_context() hook.
This
On Wed, Aug 27, 2014 at 05:48:41PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
During driver init we may not have a valid framebuffer for the primary
plane even though the plane is enabled due to failed BIOS fb takeover.
This means we have to
On Tue, Aug 26, 2014 at 02:44:51PM +0100, Arun Siluvery wrote:
The workarounds that are applied are exported to a debugfs file;
this is used to verify their state after the test case (reset or
suspend/resume etc). This patch is only required to support i-g-t.
Signed-off-by: Arun Siluvery
On Tue, Aug 26, 2014 at 02:50:28PM +0100, Arun Siluvery wrote:
Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which compares register state before and after
the test scenario.
This test currently verifies only bdw workarounds.
v2: address
On Wed, Aug 27, 2014 at 05:44:55PM +0200, Daniel Vetter wrote:
On Tue, Aug 26, 2014 at 02:44:51PM +0100, Arun Siluvery wrote:
The workarounds that are applied are exported to a debugfs file;
this is used to verify their state after the test case (reset or
suspend/resume etc). This patch is
On Wed, Aug 27, 2014 at 03:21:13PM +0100, Chris Wilson wrote:
On Wed, Aug 27, 2014 at 04:51:22PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Use the pixel_size we got from drm_format_plane_cpp() instead of
fb-bits_per_pixel/8 when
On Wed, Aug 27, 2014 at 05:50:16PM +0200, Daniel Vetter wrote:
On Tue, Aug 26, 2014 at 02:50:28PM +0100, Arun Siluvery wrote:
Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which compares register state before and after
the test scenario.
On 27/08/2014 16:44, Daniel Vetter wrote:
On Tue, Aug 26, 2014 at 02:44:51PM +0100, Arun Siluvery wrote:
The workarounds that are applied are exported to a debugfs file;
this is used to verify their state after the test case (reset or
suspend/resume etc). This patch is only required to support
On Monday 18 August 2014 05:12 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV wants even rps opcodes so print a warning of the
min/max/rpe/rp1 values are odd, and warn if an odd value
slips through to valleyview_set_rps() and truncate it to
an
On Monday 18 August 2014 05:12 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
init_clock_gating() is too late to read out the mem_freq. We already
want to print out the GPU MHz numbers before it's called. Move the
mem_freq setup to
On Wed, Aug 27, 2014 at 05:44:55PM +0200, Daniel Vetter wrote:
static inline void intel_ring_emit_wa(struct intel_engine_cs *ring,
u32 addr, u32 value)
{
+ struct drm_device *dev = ring-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
On Wed, Aug 27, 2014 at 05:17:11PM +0100, Siluvery, Arun wrote:
On 27/08/2014 16:59, Chris Wilson wrote:
On Wed, Aug 27, 2014 at 05:50:16PM +0200, Daniel Vetter wrote:
On Tue, Aug 26, 2014 at 02:50:28PM +0100, Arun Siluvery wrote:
Some of the workarounds are lost followed by a gpu reset,
On 27/08/2014 16:59, Chris Wilson wrote:
On Wed, Aug 27, 2014 at 05:50:16PM +0200, Daniel Vetter wrote:
On Tue, Aug 26, 2014 at 02:50:28PM +0100, Arun Siluvery wrote:
Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which compares register state
On 27/08/2014 17:23, Chris Wilson wrote:
On Wed, Aug 27, 2014 at 05:17:11PM +0100, Siluvery, Arun wrote:
On 27/08/2014 16:59, Chris Wilson wrote:
On Wed, Aug 27, 2014 at 05:50:16PM +0200, Daniel Vetter wrote:
On Tue, Aug 26, 2014 at 02:50:28PM +0100, Arun Siluvery wrote:
Some of the
On Wed, Aug 27, 2014 at 2:17 AM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
Not that I can tell.
Powertop report with FBC: http://pastebin.com/5qfJKpTQ
Without FBC: http://pastebin.com/NaYkR4n0
Seems to have gotten messed up somehow. I can't see the package c-state
info there
On Wed, Aug 27, 2014 at 06:02:15PM +0100, Siluvery, Arun wrote:
On 27/08/2014 17:23, Chris Wilson wrote:
On Wed, Aug 27, 2014 at 05:17:11PM +0100, Siluvery, Arun wrote:
On 27/08/2014 16:59, Chris Wilson wrote:
On Wed, Aug 27, 2014 at 05:50:16PM +0200, Daniel Vetter wrote:
On Tue, Aug 26, 2014
On Wed, Aug 27, 2014 at 10:11:34AM +0200, Daniel Vetter wrote:
A bunch of warnings fire on some -irq_postinstall hooks since those
can enable interrupts (e.g. rps interrupts). And then our ordering
self-checks fire and complain.
To fix that set the tracking boolen before enabling the irqs
On Thu, Aug 14, 2014 at 12:37:53PM -0700, Jesse Barnes wrote:
On Mon, 11 Aug 2014 23:33:57 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Aug 11, 2014 at 11:08:38AM -0700, Daisy Sun wrote:
BDW supports GT C0 residency reporting in constant time unit. Driver
calculates GT
Yi, can you get this one run through testing on multiple platforms? We
just want to make sure there's not some path we missed that's gonna
spew a warning with this change.
Thanks,
Jesse
On Tue, 26 Aug 2014 22:51:13 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 26, 2014 at 8:52 PM,
Greetings,
Given the great ideas by Jani and Chris, I will not be requiring any
changes to the i915 driver.
I will use the /sys/module/drm/parameters/debug file to set a value of 14
as Jani indicates below. I have a python script to analyze the dmesg
output.
Thanks everyone for your excellent
:-) We pulled most of the mobile functions from the bridge chip into the main
chip, so that same backlight code might well have been there.
From sandybridge onwards I see that hardware will override the PWM signal to
inactive (0 if backlight polarity is active high, 1 if active low) when PWM
On Wed, Aug 27, 2014 at 9:59 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
Yi, can you get this one run through testing on multiple platforms? We
just want to make sure there's not some path we missed that's gonna
spew a warning with this change.
I think that amount of testing is totally
On Wed, 27 Aug 2014 23:33:05 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Aug 27, 2014 at 9:59 PM, Jesse Barnes jbar...@virtuousgeek.org
wrote:
Yi, can you get this one run through testing on multiple platforms? We
just want to make sure there's not some path we missed that's gonna
On Wed, Aug 27, 2014 at 06:52:57PM +0100, Chris Wilson wrote:
Just to clarify, he was not ok because the list we maintain in the
test can get out of sync with the workarounds we apply in the driver
which can be avoided if it is generated by the kernel itself.
Test driven development would
On Wed, 27 Aug 2014 10:43:37 +0200
Daniel Vetter daniel.vet...@ffwll.ch wrote:
Now that vlv has runtime pm we kinda should check for that like on the
pch split platforms. Looks like this was simply lost in the vlv rpm
enabling.
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Cc: Imre Deak
On Wednesday, August 27, 2014 1:31 PM, Jindal, Sonika wrote:
On 8/26/2014 4:58 PM, Thierry Reding wrote:
On Fri, Aug 08, 2014 at 04:23:40PM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
Adding new defines, older one will be removed in the last patch in
On Friday, August 08, 2014 7:54 PM, Sonika Jindal wrote:
From: Sonika Jindal sonika.jin...@intel.com
Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.
On 8/28/2014 6:25 AM, Jingoo Han wrote:
On Friday, August 08, 2014 7:54 PM, Sonika Jindal wrote:
From: Sonika Jindal sonika.jin...@intel.com
Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
On Fri, Aug 29, 2014 at 08:45:21AM +0530, Deepak S wrote:
On Tuesday 26 August 2014 07:24 PM, Daniel Vetter wrote:
On Fri, Aug 22, 2014 at 08:32:40AM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Programing GT IER interrupts was fumbled while enabling
On Wed, Aug 27, 2014 at 11:30:35PM +0100, Damien Lespiau wrote:
On Wed, Aug 27, 2014 at 06:52:57PM +0100, Chris Wilson wrote:
Just to clarify, he was not ok because the list we maintain in the
test can get out of sync with the workarounds we apply in the driver
which can be avoided if it
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