On Wed, Apr 29, 2015 at 08:20:20AM +0530, Deepak S wrote:
On Wednesday 29 April 2015 12:02 AM, Ville Syrjälä wrote:
On Tue, Apr 28, 2015 at 11:16:29AM -0700, Jesse Barnes wrote:
On 03/04/2015 08:08 PM, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
When GPU
On Wed, Apr 29, 2015 at 03:01:59PM +0530, ankitprasad.r.sha...@intel.com wrote:
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch extends the get_aperture_ioctl to add support
for getting total size of the stolen region and available
size of the stolen region.
testcase:
On Wed, Jan 28, 2015 at 10:59:28AM +0100, Daniel Vetter wrote:
Do we have the libdrm patch for this too? Imo there's not much use in this
if mesa remains broken, especially since this is for gen2/3 ... most DE
use gl nowadays.
On the other hand, there is a bug report open for mesa being broken
On Wed, Apr 29, 2015 at 02:07:19PM +0300, David Weinehall wrote:
On Tue, Apr 28, 2015 at 03:46:46PM +0100, Chris Wilson wrote:
On Tue, Apr 28, 2015 at 02:38:25PM +, Antoine, Peter wrote:
So is the plan to push these patches and have follow-on work to cover the
other paths?
As
On Wed, Apr 29, 2015 at 03:02:20PM +0530, ankitprasad.r.sha...@intel.com wrote:
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch adds the testcases for verifying the new extended
gem_create ioctl. By means of this extended ioctl, memory
placement of the GEM object can be
Due to missing shifting, the vlv infoframe port check only works for
port A. Fix it. Broken since introduction in
commit 535afa2e9e3c1867460d6981d879b04d8b2b9ab3
Author: Jesse Barnes jbar...@virtuousgeek.org
Date: Wed Apr 15 16:52:29 2015 -0700
drm/i915/vlv: check port in infoframe_enabled
On Wed, Apr 29, 2015 at 11:19:18AM +0100, Chris Wilson wrote:
On Wed, Apr 29, 2015 at 03:01:58PM +0530, ankitprasad.r.sha...@intel.com
wrote:
+ while (remain 0) {
+ /* Operation in this page
+*
+* page_base = page offset within aperture
+
On Tue, Apr 28, 2015 at 03:46:46PM +0100, Chris Wilson wrote:
On Tue, Apr 28, 2015 at 02:38:25PM +, Antoine, Peter wrote:
So is the plan to push these patches and have follow-on work to cover the
other paths?
As this fixes the Bugzilla issue that has been raised.
You've identified
On Mon, 27 Apr 2015, Dave Gordon david.s.gor...@intel.com wrote:
On 27/04/15 16:32, Chris Wilson wrote:
drivers/gpu/drm/i915/intel_dvo.c: In function ‘intel_dvo_init’:
drivers/gpu/drm/i915/intel_dvo.c:531:8: warning: array subscript is above
array bounds [-Warray-bounds]
I found this one
On Wed, Apr 29, 2015 at 11:19:47AM +0200, Olivier Fourdan wrote:
Backlight helper PID is set to -1 by default, if for some reason it's
not set, we may end up with waitpid(-1, ...) which will hang forever.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90230
Signed-off-by: Olivier
On Tue, Apr 28, 2015 at 11:46:59AM +0100, Patrick Welche wrote:
In ancient pre-KMS times, I was able to get a particular pineview-based
(Atom D525) desktop computer monitor to run at decent resolutions.
Recently, I have tried the 2.99.917 snapshot, and the best I can
manage is 1024x768.
On Wed, Apr 29, 2015 at 08:36:24AM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
v2: rename reg defn to match spec. (Ville)
v3: Updated bias setting for chv (Deepak)
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch adds support for extending the pread/pwrite functionality
for objects not backed by shmem. The access will be made through
gtt interface.
This will cover prime objects as well as stolen memory backed objects
but for userptr
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch adds support for clearing buffer objects via blitter
engines. This is particularly useful for clearing out the memory
from stolen region.
v2: Add support for using execlists PPGTT
v3: Fix issues in legacy ringbuffer submission
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch adds the testcases for verifying the new extended
gem_create ioctl. By means of this extended ioctl, memory
placement of the GEM object can be specified, i.e. either
shmem or stolen memory.
These testcases include functional tests
From: Chris Wilson ch...@chris-wilson.co.uk
If we run out of stolen memory when trying to allocate an object, see if
we can reap enough purgeable objects to free up enough contiguous free
space for the allocation. This is in principle very much like evicting
objects to free up enough contiguous
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
Extend the drm_i915_gem_create structure to add support for
creating Stolen memory backed objects. Added a new flag through
which user can specify the preference to allocate the object from
stolen memory, which if set, an attempt will be
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch extends the get_aperture_ioctl to add support
for getting total size of the stolen region and available
size of the stolen region.
testcase: igt/gem_create_stolen
Signed-off-by: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch series adds support for creating/using Stolen memory backed
objects.
Despite being a unified memory architecture (UMA) some bits of memory
are more equal than others. In particular we have the thorny issue of
stolen memory,
Backlight helper PID is set to -1 by default, if for some reason it's
not set, we may end up with waitpid(-1, ...) which will hang forever.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90230
Signed-off-by: Olivier Fourdan ofour...@redhat.com
---
src/backlight.c | 2 +-
1 file changed,
From: Lu, Han han...@intel.com
In SKL, HDMI/DP codec and PCH HD Audio Controller are in different power wells,
so it's necessary to reset display audio codecs when power well on, otherwise
display audio codecs will disappear when resume from low power state.
Reset steps when power on:
enable
From: Lu, Han han...@intel.com
Add support for enabling codec wakeup override signal to allow
re-enumeration of the controller on SKL after resume from low power state.
v3 by Jani: Simplify to only support toggling the appropriate chicken bit.
Signed-off-by: Lu, Han han...@intel.com
On Wed, Apr 29, 2015 at 09:49:30AM +0300, Mika Kuoppala wrote:
When we have bound vma into an address space, the layout
of page table structures is immutable. So we can be absolutely
certain that if vma is already bound, there is no need to
(re)allocate a virtual address range for it.
v2: -
Hi Jani,
Sorry I didn't find method to access chicken bit registers or any other 0x65000
based registers
through audio mmio bar in ALSA side. It looks like the only way to access i915
registers from audio
side is through i915 callback (please correct me if I was wrong). So I apply
your patch
Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
On 4/29/2015 11:47 AM, Mika Kahola wrote:
This patch adds DP link training optimization by reusing the
previously trained values.
v2:
- rebase
V3:
- rebase
V4:
- when HPD long pulse is received, the flag is cleared
that
When we have bound vma into an address space, the layout
of page table structures is immutable. So we can be absolutely
certain that if vma is already bound, there is no need to
(re)allocate a virtual address range for it.
v2: - add sanity checks and remove superfluous GLOBAL_BIND set
- we
Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
On 4/29/2015 11:47 AM, Mika Kahola wrote:
This is a first of series patches that optimize DP link
training. The first patch is for eDP only where we reuse
the previously trained link training values from cache
i.e. voltage swing
This patch adds DP link training optimization by reusing the
previously trained values.
v2:
- rebase
V3:
- rebase
V4:
- when HPD long pulse is received, the flag is cleared
that indicates if DP link training is required or not
(based on Sivakumar's comment)
Signed-off-by: Mika Kahola
This is a first of series patches that optimize DP link
training. The first patch is for eDP only where we reuse
the previously trained link training values from cache
i.e. voltage swing and pre-emphasis levels.
In case we are not able to train the link by reusing
the known values, the link
This is patch series optimizes DP link training by reusing
the link parameter settings if DP link has bee previously
trained. In case we are not able to train the link by reusing
the known values, the link training parameters are set
to zero and training is restarted.
The first patch is for eDP
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
New subtests to excercise flips from tiled to tiled and from
linear to tiled frame buffers.
These will catch display programming issues like not preserving the
tiling mode in page flips or not re-programming the watermarks.
v2: Cleanup crc object
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Rendering into Y and Yf tiled frame buffers with Cairo was losing the
previous content ie. was starting from black. This is different than the
behaviour with linear and X tiled so make it the same by blitting the
initial content when creating the
On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote:
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
Reviewed-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote:
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
Add port check for ibx similar to vlv in
commit 535afa2e9e3c1867460d6981d879b04d8b2b9ab3
Author: Jesse Barnes jbar...@virtuousgeek.org
Date: Wed Apr 15 16:52:29 2015 -0700
drm/i915/vlv: check port in infoframe_enabled v2
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
On Mon, 27 Apr 2015, Chandra Konduru chandra.kond...@intel.com wrote:
This patch enables skylake primary plane scaling using shared
scalers atomic desgin.
v2:
-use single copy of scaler limits (Matt)
v3:
-move detach_scalers to crtc commit path (Matt)
-use values in plane_state-src as
On Fri, 24 Apr 2015, Shobhit Kumar shobhit.ku...@intel.com wrote:
In case we unload and load a driver module again that is registering a
lookup table, without this it will result in multiple entries. Provide
an option to remove the lookup table on driver unload
v2: Ccing maintainers
Shobhit,
On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote:
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
On Wed, Apr 29, 2015 at 03:01:58PM +0530, ankitprasad.r.sha...@intel.com wrote:
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch adds support for extending the pread/pwrite functionality
for objects not backed by shmem. The access will be made through
gtt interface.
This
On Wed, Jan 28, 2015 at 10:59:28AM +0100, Daniel Vetter wrote:
On Mon, Jan 26, 2015 at 04:43:18AM -0800, Rodrigo Vivi wrote:
When constructing a batchbuffer, it is sometimes crucial to know the
largest hole into which we can fit a fenceable buffer (for example when
handling very large
On Wed, Apr 29, 2015 at 04:05:40PM +0100, Tvrtko Ursulin wrote:
On 04/27/2015 01:41 PM, Chris Wilson wrote:
With the removal of the pin_ioctl, we need only consider
obj-pin_display when looking at available aperture space.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
On 04/29/2015 05:30 AM, Jani Nikula wrote:
Add port check for ibx similar to vlv in
commit 535afa2e9e3c1867460d6981d879b04d8b2b9ab3
Author: Jesse Barnes jbar...@virtuousgeek.org
Date: Wed Apr 15 16:52:29 2015 -0700
drm/i915/vlv: check port in infoframe_enabled v2
Signed-off-by:
-Original Message-
From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
Sent: Wednesday, April 29, 2015 5:13 AM
To: Konduru, Chandra; intel-gfx@lists.freedesktop.org; Roper, Matthew D
Cc: Vetter, Daniel; Conselvan De Oliveira, Ander
Subject: Re: [Intel-gfx] [PATCH 13/14] drm/i915:
From: A.Sunil Kamath sunil.kam...@intel.com
Display Context Save and Restore support is needed for
various SKL Display C states like DC5, DC6.
This implementation is added based on first version of DMC CSR program
that we received from h/w team.
Here we are using request_firmware based design.
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6279
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Wed, Apr 29, 2015 at 06:31:56PM +0300, Ville Syrjälä wrote:
On Wed, Apr 29, 2015 at 08:23:21AM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU min/idel freq to
RPe.
Punit is expecting us to
From: Alex Dai yu@intel.com
Allocate a gem obj to hold GuC log data. Also a debugfs interface
(i915_guc_log_dump) is provided to print out the log content.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 41 +
From: Alex Dai yu@intel.com
These are the subset of GuC interface that we are going to use to
enable command submission through GuC. The definition of these
struct and bit setting need to match those in firmware.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
---
From: Alex Dai yu@intel.com
Add GuC firmware loader. It uses the unified firmware loader to
fetch firmware blob first, then load to hw in driver main thread.
This patch is derived from GuC loading work originally done by
Vinit Azad and Ben Widawsky. It has been reconstructed to accord
with
From: Alex Dai yu@intel.com
Now print out Bootrom, uKernel and MIA Core status. The scratch reg
0 15 are used for communication between driver and firmware. Their
status is also printed out.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c
From: Alex Dai yu@intel.com
Implementation of GuC client. A GuC client has its own doorbell
and workqueue. It maintains the doorbell cache line, process
description object and work queue item.
A default guc_client is created to do the in-order legacy execlist
submission.
Issue: VIZ-4884
From: Dave Gordon david.s.gor...@intel.com
In order to fully initialise the default contexts, we have to execute
batchbuffer commands on the GPU engines. But we can't do that until any
required firmware has been loaded, which may not be possible during
driver load, because the filesystem(s)
From: Alex Dai yu@intel.com
Add overview design of GuC, plus some key points related to
the implementation.
Signed-off-by: Alex Dai yu@intel.com
---
Documentation/DocBook/drm.tmpl | 19 +++
1 file changed, 19 insertions(+)
diff --git a/Documentation/DocBook/drm.tmpl
From: Alex Dai yu@intel.com
All gem objects used by GuC are pinned to ggtt space out of range
[0, WOPCM size]. In GuC address space mapping, [0, WPOCM size] is
used internally for its Boot ROM, SRAM etc. Currently this WPOCM
size is 512K. This is done by using of PIN_OFFSET_BIAS.
Issue:
From: Michael H. Nguyen michael.h.ngu...@intel.com
Move defines from intel_lrc.c to i915_reg.h so they are
accessible by the guc files
Issue: VIZ-4884
Signed-off-by: Michael H. Nguyen michael.h.ngu...@intel.com
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 77
From: Alex Dai yu@intel.com
Turn on interrupt steering to route necessary interrupts to GuC.
Issue: VIZ-4884
Signed-off-by: Dave Gordon david.s.gor...@intel.com
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/i915_reg.h| 11 --
From: Michael H. Nguyen michael.h.ngu...@intel.com
i915_gem_object_write() is a generic function to copy data from
user memory to gem object.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gem.c | 28
From: Alex Dai yu@intel.com
Add functions to submit work queue item and ring the door bell.
GuC TLB needs to be invalided if LRC context changes.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/intel_guc.h| 3 +
From: Dave Gordon david.s.gor...@intel.com
Factor out the common code of loading firmware into a new file,
leaving only the uC-specific parts in the GuC loaders.
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
From: Alex Dai yu@intel.com
To enable GuC command submission / scheduling, we need to setup
firmware initializaion properly. i915.enable_guc_scheduling is
introduced to enable / disable GuC submission.
GuC firmware uses the one page after Ring Context as shared data.
However, GuC uses same
From: Alex Dai yu@intel.com
This series of patch is to enable ExecList submission via GuC. It is verified
by some basic IGT tests on HAS and SKL HW. Here are some key points related to
this series, not in particular order.
v6:
- Changed the firmware name to skl_guc_ver1.bin, followed naming
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6281
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On 04/27/2015 01:41 PM, Chris Wilson wrote:
Currently, we only track the last request globally across all engines.
This prevents us from issuing concurrent read requests on e.g. the RCS
and BCS engines (or more likely the render and media engines). Without
semaphores, we incur costly stalls as
On Wed, Apr 29, 2015 at 01:24:34PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Rendering into Y and Yf tiled frame buffers with Cairo was losing the
previous content ie. was starting from black. This is different than the
behaviour with linear and X tiled so
Hi,
On 04/27/2015 01:41 PM, Chris Wilson wrote:
This trims a little overhead from the common case of not needing to
synchronize between rings.
v2: execlists is special and likes to duplicate code.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
The CRC (Crystal Cove) PMIC, controls the panel enable and disable
signals for BYT for dsi panels. This is indicated in the VBT fields. Use
that to initialize and use GPIO based control for these signals.
v2: Use the newer gpiod interface(Alexandre)
v3: Remove the redundant checks and unused code
Use the CRC PWM device in intel_panel.c and add new MIPI backlight
specififc callbacks
v2: Modify to use pwm_config callback
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
On Wed, Apr 29, 2015 at 01:28:19PM +, Daniel, Thomas wrote:
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of
Chris Wilson
Sent: Friday, March 6, 2015 9:44 AM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH]
Needed for PWM control suuported by the PMIC
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
The Crystalcove PMIC controls PWM signals and this driver exports that
capability as a PWM chip driver. This is platform device implementtaion
of the drivers/mfd cell device for CRC PMIC
v2: Use the existing config callback with duty_ns and period_ns(Thierry)
CC: Samuel Ortiz
Hi All,
On some of the BYT devices, for DSI panels, the panel enable/disable signals
and backlight control are done using the Crystalcove PMIC. This series provides
support for the same and has been reviewed earlier on -
http://lists.freedesktop.org/archives/intel-gfx/2015-March/061908.html
This
On some Intel SoC platforms, the panel enable/disable signals are
controlled by CRC PMIC. Add those control as a new GPIO in a lookup
table for gpio-crystalcove chip during CRC driver load
v2: Make the lookup table static (Thierry)
Remove the lookup table during driver remove (Thierry)
CC:
In case we unload and load a driver module again that is registering a
lookup table, without this it will result in multiple entries. Provide
an option to remove the lookup table on driver unload
v2: Ccing maintainers
Cc: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij
On some BYT PLatform the PWM is controlled using CRC PMIC. Add a lookup
entry for the same to be used by the consumer (Intel GFX)
v2: Remove the lookup table on driver unload (Thierry)
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot
In case some drivers are unloading, they can remove lookup tables which
they would have registered during their load time to avoid redundant
entries if loaded again
v2: Ccing maintainers
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Chris Wilson
Sent: Friday, March 6, 2015 9:44 AM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915: Add soft-pinning API for execbuffer
Userspace can pass in an
On ti, 2015-04-07 at 11:45 +0100, Nick Hoath wrote:
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 8 +
drivers/gpu/drm/i915/intel_pm.c | 2 ++
drivers/gpu/drm/i915/intel_ringbuffer.c | 53
+++--
3
On Sun, 12 Apr 2015, Lukas Wunner lu...@wunner.de wrote:
Single channel LVDS maxes out at 112 MHz. All 17 models with i915
graphics had a resolution of 1920x1200 (193 MHz), necessitating dual
channel LVDS. The 15 pre-retina models had either 1440x900 (106 MHz)
or 1680x1050 (119 MHz), both
On Wed, Apr 29, 2015 at 03:03:43PM +0100, Tvrtko Ursulin wrote:
Hi,
On 04/27/2015 01:41 PM, Chris Wilson wrote:
This trims a little overhead from the common case of not needing to
synchronize between rings.
v2: execlists is special and likes to duplicate code.
Signed-off-by: Chris
On Fri, Apr 17, 2015 at 12:22:00PM +0100, Chris Wilson wrote:
On Fri, Apr 17, 2015 at 11:57:28AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
In order to use userptr, the kernel tracks the owner's mm with a
mmu_notifier. Setting that is very expensive - it
On pe, 2015-03-20 at 09:29 +, Nick Hoath wrote:
This stepping isn't listed separately in the specs, so needs confirmation.
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git
On 04/27/2015 01:41 PM, Chris Wilson wrote:
Since the remove of the pin-ioctl, we only care about not changing the
cache level on buffers pinned to the hardware as indicated by
obj-pin_display. So we can safely replace i915_gem_object_is_pinned()
here with a plain obj-pin_display check. During
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6282
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Wed, Apr 29, 2015 at 08:23:21AM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU min/idel freq to
RPe.
Punit is expecting us to operate GPU between Rpe Rp0. If we drop the
frequency to RPn, punit is
Andi,
Thanks for your comments and that makes sense for me, just check kernel version
is not
an ideal method for those unofficial kernels with back porting patches. Then we
have the
following open questions in my mind:
How do we check whether the i915 KMD support secure batch buffer
From: Alex Dai yu@intel.com
This is to avoid bad IO access caused by writing NOOP to wrap the
ring buffer whilst ring is unpinned.
Signed-off-by: Alex Dai yu@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
On Wed, Apr 29, 2015 at 03:50:13PM +0100, Tvrtko Ursulin wrote:
On 04/27/2015 01:41 PM, Chris Wilson wrote:
Since the remove of the pin-ioctl, we only care about not changing the
cache level on buffers pinned to the hardware as indicated by
obj-pin_display. So we can safely replace
By the way, your subject lines are messed up.
They should adhere to the conventions laid down by the Maintainers.
`git log --oneline -- drivers/subsystem`
On some Intel SoC platforms, the panel enable/disable signals are
controlled by CRC PMIC. Add those control as a new GPIO in a lookup
On Wed, 29 Apr 2015, Shobhit Kumar wrote:
On some BYT PLatform the PWM is controlled using CRC PMIC. Add a lookup
entry for the same to be used by the consumer (Intel GFX)
v2: Remove the lookup table on driver unload (Thierry)
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij
On Wed, 29 Apr 2015, Shobhit Kumar wrote:
Needed for PWM control suuported by the PMIC
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
Signed-off-by: Shobhit Kumar
On Wed, 29 Apr 2015, Shobhit Kumar wrote:
On some Intel SoC platforms, the panel enable/disable signals are
controlled by CRC PMIC. Add those control as a new GPIO in a lookup
table for gpio-crystalcove chip during CRC driver load
v2: Make the lookup table static (Thierry)
Remove the
On 04/27/2015 01:41 PM, Chris Wilson wrote:
With the removal of the pin_ioctl, we need only consider
obj-pin_display when looking at available aperture space.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
1 file changed, 1 insertion(+), 1
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6268
-Summary-
Platform Delta drm-intel-nightly Series Applied
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