Re: [Intel-gfx] [v3] drm/i915/skl: If needed sanitize bios programmed cdclk

On 10/16/2015 06:48 PM, Shobhit Kumar wrote: Especially in cases where pre-os does not enable display, cdclk might not be in sane state. During sanitization initialize cdclk with maximum value till we get dynamic cdclk support. v2: Check if BIOS programmed correctly rather than always calling

Re: [Intel-gfx] [PATCH 02/15] drm/i915: Don't pass *DP around to link training functions

On Mon, 2015-10-19 at 10:15 +0530, Thulasimani, Sivakumar wrote: > > On 10/5/2015 12:31 PM, Ander Conselvan de Oliveira wrote: > > It just makes the code more confusing, so just reference intel_dp_>DP > > directly. The old behavior of not updating the value in intel_dp if link > > training fail

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Move max voltage and pre emphasis to intel_dp_link_training.c

On Mon, 2015-10-19 at 10:44 +0530, Thulasimani, Sivakumar wrote: > As an FYI, both of these functions need to be rewritten when we want the > code to be > compliant to DP spec. > We should read the pre-emphasis given by the panel and if vwing exeeds > max value > we should use the max vswing

Re: [Intel-gfx] v4.3-rc4: i915: ThinkPad Yoga 12: *ERROR* The master control interrupt lied (SDE)! [regression]

could please upload the log before this error. thanks On Oct 14, 2015 3:14 PM, "Jani Nikula" wrote: > > On Wed, 14 Oct 2015, "Miramontes Caton, Jairo Daniel" < jairo.daniel.miramontes.ca...@intel.com> wrote: > > Created bug in fdo bugzilla to keep track of this

Re: [Intel-gfx] [PATCH 4.1, 4.2] drm/i915: Silence DDR DVFS errors on CHV

On Sat, 17 Oct 2015, Greg KH wrote: > On Mon, Sep 28, 2015 at 10:09:11PM +0300, ville.syrj...@linux.intel.com wrote: >> From: Ville Syrjälä >> >> commit 58590c14d80defc94e900308a9d8fa55284de6f2 upstream. > > This is not the commit id of

Re: [Intel-gfx] [PATCH] drm/i915/skl: Correct other-pipe watermark update condition check

On Mon, Oct 19, 2015 at 11:29:59AM +0200, Daniel Vetter wrote: > On Mon, Sep 21, 2015 at 11:32:44PM +0530, Kumar, Mahesh wrote: > > If ddb allocation for planes in current CRTC is changed, that doesn't > > lead to ddb allocation change for other CRTCs, because our DDB allocation > > is not dynamic

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Improve dynamic management/eviction of lrc backing objects

On 19/10/2015 10:48, Daniel Vetter wrote: On Fri, Oct 16, 2015 at 03:42:53PM +0100, Nick Hoath wrote: On 08/10/2015 14:35, Chris Wilson wrote: On Wed, Oct 07, 2015 at 06:05:46PM +0200, Daniel Vetter wrote: On Tue, Oct 06, 2015 at 03:52:02PM +0100, Nick Hoath wrote: Shovel all context related

Re: [Intel-gfx] [PATCH] drm/i915: Consider plane rotation when calculating stride in skl_do_mmio_flip

Hi, On 07/10/15 13:15, Tvrtko Ursulin wrote: On 07/10/15 13:10, Jindal, Sonika wrote: On 10/7/2015 3:31 PM, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Previously rotation was ignored and wrong stride programmed into the plane registers resulting in a corrupt

Re: [Intel-gfx] [PATCH] drm/i915: track relative-constants-mode per-context not per-device

On 13/10/15 16:28, Daniel Vetter wrote: On Tue, Oct 13, 2015 at 02:20:05PM +0100, Dave Gordon wrote: 'relative_constants_mode' has always been tracked per-device, but this is wrong in execlists (or GuC) mode, as INSTPM is saved and restored with the logical context, and the per-context value

[Intel-gfx] [libdrm] intel: Query full context GTT sizes for use with execbuffer

With the advent of full per-process GTT, the per context GTT may be a different size to the global GTT as reported by the get_aperture ioctl. It is also likely to be 4GiB or larger, exposing some fragility in the code for summing batch sizes. Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Improve dynamic management/eviction of lrc backing objects

On Fri, Oct 16, 2015 at 03:42:53PM +0100, Nick Hoath wrote: > On 08/10/2015 14:35, Chris Wilson wrote: > >On Wed, Oct 07, 2015 at 06:05:46PM +0200, Daniel Vetter wrote: > >>On Tue, Oct 06, 2015 at 03:52:02PM +0100, Nick Hoath wrote: > >>>Shovel all context related objects through the active queue

Re: [Intel-gfx] [PATCH] drm: Explicitly compute the last cacheline for clflush on range

On Sun, Oct 18, 2015 at 05:07:06PM +0100, Chris Wilson wrote: > On Sun, Oct 18, 2015 at 02:07:13PM +0100, Chris Wilson wrote: > > > I couldn't spot the difference either. I am beginning to suspect it is > > > gcc as > > > > > > diff --git a/drivers/gpu/drm/drm_cache.c

Re: [Intel-gfx] [PATCH] drm/i915/skl: Correct other-pipe watermark update condition check

On Mon, Sep 21, 2015 at 11:32:44PM +0530, Kumar, Mahesh wrote: > If ddb allocation for planes in current CRTC is changed, that doesn't > lead to ddb allocation change for other CRTCs, because our DDB allocation > is not dynamic according to plane parameters, ddb is allocated according > to number

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Only call commit_planes when there are things to commit.

On Fri, Oct 16, 2015 at 03:47:37PM +0300, Ville Syrjälä wrote: > On Wed, Sep 23, 2015 at 04:29:39PM +0200, Maarten Lankhorst wrote: > > The atomic helpers set planes_changed on a crtc_state if there is > > any plane_state bound to that crtc. If there's none and there is > > no pipe update required

Re: [Intel-gfx] [PATCH v6 4/4] drm/i915: set proper N/CTS in modeset

On Wed, 02 Sep 2015, Takashi Iwai wrote: > On Wed, 02 Sep 2015 11:02:42 +0200, > Jani Nikula wrote: >> >> >> Nitpick. I'd prefer some sharing with the similar blocks from the >> >> earlier patch. Also a debug message on n == 0 would be nice; you >> >> probably didn't notice your

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gen8: Flip the 48b switch

On Fri, Oct 16, 2015 at 01:23:41PM +0100, Michel Thierry wrote: > On 10/1/2015 2:16 PM, Daniel Vetter wrote: > >On Wed, Sep 30, 2015 at 03:36:19PM +0100, Michel Thierry wrote: > >>Use 48b addresses if hw supports it (i915.enable_ppgtt=3). > >>Update the sanitize_enable_ppgtt for 48 bit PPGTT mode.

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gen8: Flip the 48b switch

On Mon, Oct 19, 2015 at 11:44:12AM +0200, Daniel Vetter wrote: > On Fri, Oct 16, 2015 at 01:23:41PM +0100, Michel Thierry wrote: > > On 10/1/2015 2:16 PM, Daniel Vetter wrote: > > >On Wed, Sep 30, 2015 at 03:36:19PM +0100, Michel Thierry wrote: > > >>Use 48b addresses if hw supports it

Re: [Intel-gfx] [PATCH] drm/i915: Report context GTT size

On Fri, Oct 16, 2015 at 05:34:55PM +0100, Tvrtko Ursulin wrote: > > On 14/10/15 14:17, Chris Wilson wrote: > >Since the beginning we have conflated the size of the global GTT with > >that of the per-process context sizes. In recent times (gen8+), those > >are no longer the same where the global

Re: [Intel-gfx] [DMC_BUGFIX_V3] drm/i915/skl: Making DC6 entry is the last call in suspend flow.

On Fri, Oct 16, 2015 at 03:22:45PM +0300, Imre Deak wrote: > On ti, 2015-09-29 at 11:01 +0530, Animesh Manna wrote: > > Mmio register access after dc6/dc5 entry is not allowed when > > DC6 power states are enabled according to bspec (bspec-id 0527), > > so enabling dc6 as the last call in suspend

Re: [Intel-gfx] [PATCH v2] drm/i915/hsw: keep gamma and CSC enabled for primary plane disable

On Fri, Oct 16, 2015 at 03:53:22PM -0700, Bob Paauwe wrote: > On Thu, 15 Oct 2015 15:41:30 +0300 > Ville Syrjälä wrote: > > > On Thu, Oct 15, 2015 at 02:31:09PM +0200, Daniel Vetter wrote: > > > > > > On Thu, Oct 15, 2015 at 12:51 AM, Kevin Strasser > > >

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Make prepare_plane_fb fully interruptible.

On Fri, Oct 16, 2015 at 02:21:26PM +0300, Ander Conselvan De Oliveira wrote: > On Wed, 2015-09-23 at 13:27 +0200, Maarten Lankhorst wrote: > > Now that we agreed on not preserving framebuffers pinning is finally > > allowed to fail because of signals. Use this to make pinning > > and acquire the

Re: [Intel-gfx] [PATCH] igt/kms_addfb_basic: New subtest to check for fb modifier and tiling mode mismatch

On Thu, Oct 15, 2015 at 06:10:46PM -0700, Vivek Kasireddy wrote: > Hi Tvrtko, > > On Fri, 9 Oct 2015 09:34:25 +0100 > Tvrtko Ursulin wrote: > > > > > > > On 08/10/15 09:55, Tvrtko Ursulin wrote: > > > On 07/10/15 22:07, Vivek Kasireddy wrote: > > >> > > >> Hi

Re: [Intel-gfx] [PATCH] igt/kms_rotation_crc: Add a subtest to validate Y-tiled obj + Y fb modifier

Hi, On 17/10/15 03:47, Vivek Kasireddy wrote: The main goal of this subtest is to verify whether flipping a framebuffer with a Y fb modifier (90/270 degree rotation) and an associated Y-tiled object works or not. Cc: Tvrtko Ursulin Signed-off-by: Vivek Kasireddy

[Intel-gfx] [QA 2015-10-10 ww42] Testing report for `drm-intel-testing`

Hello, We launched Intel GPU Tools on 54 platforms: Skylake-Y, Braswell-M, Broadwell-U, Baytrail-M and Haswell-U to validate tag drm-intel-testing-2015-10-10 (kernel 4.3-rc4). Here are the results: New bugs reported:

Re: [Intel-gfx] [PATCH v6 4/4] drm/i915: set proper N/CTS in modeset

On Mon, 19 Oct 2015 10:25:22 +0200, Jani Nikula wrote: > > On Wed, 02 Sep 2015, Takashi Iwai wrote: > > On Wed, 02 Sep 2015 11:02:42 +0200, > > Jani Nikula wrote: > >> > >> >> Nitpick. I'd prefer some sharing with the similar blocks from the > >> >> earlier patch. Also a debug

Re: [Intel-gfx] [PATCH 02/15] drm/i915: Don't pass *DP around to link training functions

On Mon, 2015-10-19 at 10:15 +0530, Thulasimani, Sivakumar wrote: > > On 10/5/2015 12:31 PM, Ander Conselvan de Oliveira wrote: > > It just makes the code more confusing, so just reference intel_dp_>DP > > directly. The old behavior of not updating the value in intel_dp if link > > training fail

Re: [Intel-gfx] [PATCH 02/15] drm/i915: Don't pass *DP around to link training functions

On 10/19/2015 2:26 PM, Ander Conselvan De Oliveira wrote: On Mon, 2015-10-19 at 10:15 +0530, Thulasimani, Sivakumar wrote: On 10/5/2015 12:31 PM, Ander Conselvan de Oliveira wrote: It just makes the code more confusing, so just reference intel_dp_>DP directly. The old behavior of not

Re: [Intel-gfx] [PATCH v3] drm/i915: Improve kernel-doc for i915_audio_component struct

On Fri, Oct 16, 2015 at 11:24:24AM +0200, David Henningsson wrote: > Signed-off-by: David Henningsson Queued for -next, thanks for the patch. -Daniel > --- > > Now rebased against drm-intel git master. > > include/drm/i915_component.h | 69 >

[Intel-gfx] [PATCH 1/2] dim: Don't run stuff that needs dim setup

Yet another case where something fell off - we can't compute dim_branches before setup is done, so shovel it somewhere where that's not the case. v2: Also fixup bash completion. Reported-by: Tvrtko Ursulin Signed-off-by: Daniel Vetter

[Intel-gfx] [PATCH 2/2] dim: Add success notice to setup

Also add a few output lines in between for progress. Signed-off-by: Daniel Vetter --- dim | 5 + 1 file changed, 5 insertions(+) diff --git a/dim b/dim index 298874355c84..5f0039c41fc6 100755 --- a/dim +++ b/dim @@ -618,6 +618,7 @@ function setup_dim fi

Re: [Intel-gfx] [PATCH] dim: Don't run stuff that needs dim setup

On Mon, 19 Oct 2015, Jani Nikula wrote: > Yet another case where something fell off - we can't compute > dim_branches before setup is done, so handle the commands that don't > need setup first. This should've had an explanation saying that I'd prefer this kind of approach,

[Intel-gfx] [DIM PATCH] maintainer-tools: extract the man page from the dim script

Add some magic to find the man page on dim help, and display the man page like before. Add make target to create dim.html version of the man page. --- Makefile | 9 +- dim | 324 +++ dim.rst | 309

[Intel-gfx] [PATCH] drm/core: Fix error condition in __setplane_internal.

Just like the other checks the crtc coordinates need to use goto out. This fixes a framebuffer leak introduced by commit 3968be946a057baa. "drm: Make integer overflow checking cover universal cursor updates (v2)" Cc: Matt Roper Fixes: 3968be946a057baa Signed-off-by:

Re: [Intel-gfx] [PATCH] drm/i915: track relative-constants-mode per-context not per-device

On Mon, Oct 19, 2015 at 01:16:18PM +0100, Dave Gordon wrote: > On 13/10/15 16:28, Daniel Vetter wrote: > >On Tue, Oct 13, 2015 at 02:20:05PM +0100, Dave Gordon wrote: > >>'relative_constants_mode' has always been tracked per-device, but this > >>is wrong in execlists (or GuC) mode, as INSTPM is

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Make wait_for_flips interruptible.

On Wed, 2015-09-23 at 13:27 +0200, Maarten Lankhorst wrote: > Move it from intel_crtc_atomic_commit to prepare_plane_fb. > Waiting is done before committing, otherwise it's too late > to undo the changes. > > Signed-off-by: Maarten Lankhorst > --- >

[Intel-gfx] [PULL] drm-intel-next

Hi Dave, drm-intel-next-2015-10-10: - dmc fixes from Animesh (not yet all) for deeper sleep states - piles of prep patches from Ville to make mmio functions type-safe - more fbc work from Paulo all over - w/a shuffling from Arun Siluvery - first part of atomic watermark updates from Matt and

Re: [Intel-gfx] [PATCH] drm/i915/skl: Correct other-pipe watermark update condition check

On Mon, Oct 19, 2015 at 04:00:18PM +0300, Ville Syrjälä wrote: > On Mon, Oct 19, 2015 at 11:29:59AM +0200, Daniel Vetter wrote: > > On Mon, Sep 21, 2015 at 11:32:44PM +0530, Kumar, Mahesh wrote: > > > If ddb allocation for planes in current CRTC is changed, that doesn't > > > lead to ddb

Re: [Intel-gfx] [PATCH] drm/core: Fix error condition in __setplane_internal.

On Mon, Oct 19, 2015 at 03:14:52PM +0200, Maarten Lankhorst wrote: > Just like the other checks the crtc coordinates need to use goto out. > > This fixes a framebuffer leak introduced by commit 3968be946a057baa. > "drm: Make integer overflow checking cover universal cursor updates (v2)" > > Cc:

[Intel-gfx] [PATCH] dim: Don't run stuff that needs dim setup

Yet another case where something fell off - we can't compute dim_branches before setup is done, so handle the commands that don't need setup first. Reported-by: Tvrtko Ursulin Signed-off-by: Jani Nikula --- this is on top of the man page

[Intel-gfx] [PULL] topic/drm-misc

Hi Dave, More drm-misc for 4.4. - fb refcount fix in atomic fbdev - various locking reworks to reduce drm_global_mutex and dev->struct_mutex - rename docbook to gpu.tmpl and include vga_switcheroo stuff, plus more vga_switcheroo (Lukas Wunner) - viewport check fixes for atomic drivers from

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Make wait_for_flips interruptible.

On Mon, Oct 19, 2015 at 04:16:53PM +0300, Ander Conselvan De Oliveira wrote: > On Wed, 2015-09-23 at 13:27 +0200, Maarten Lankhorst wrote: > > @@ -13306,6 +13299,29 @@ intel_prepare_plane_fb(struct drm_plane *plane, > > if (ret) > > return ret; > > > > + if (old_obj) { > > +

Re: [Intel-gfx] [v3] drm/i915/skl: If needed sanitize bios programmed cdclk

On Fri, Oct 16, 2015 at 06:48:53PM +0530, Shobhit Kumar wrote: > Especially in cases where pre-os does not enable display, cdclk might > not be in sane state. During sanitization initialize cdclk with maximum > value till we get dynamic cdclk support. > > v2: Check if BIOS programmed correctly

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Make wait_for_flips interruptible.

Op 19-10-15 om 15:16 schreef Ander Conselvan De Oliveira: > On Wed, 2015-09-23 at 13:27 +0200, Maarten Lankhorst wrote: >> Move it from intel_crtc_atomic_commit to prepare_plane_fb. >> Waiting is done before committing, otherwise it's too late >> to undo the changes. >> >> Signed-off-by: Maarten

[Intel-gfx] [PATCH 2.9/5] drm/i915: Do not wait for flips in intel_crtc_disable_noatomic.

Op 19-10-15 om 15:16 schreef Ander Conselvan De Oliveira: > On Wed, 2015-09-23 at 13:27 +0200, Maarten Lankhorst wrote: >> Move it from intel_crtc_atomic_commit to prepare_plane_fb. >> Waiting is done before committing, otherwise it's too late >> to undo the changes. >> >> Signed-off-by: Maarten

[Intel-gfx] [PATCH resend v2 3/8] drm/i915: Cope with request list state change during error state capture

Since we're not synchronizing the ring request list during error state capture the request list state might change between the time the corresponding error request list was allocated and dimensioned to the time when the ring request list is actually captured into the error state. If this happens

Re: [Intel-gfx] [PATCH 4.1, 4.2] drm/i915: Silence DDR DVFS errors on CHV

On Mon, Oct 19, 2015 at 11:02:35AM +0300, Jani Nikula wrote: > On Sat, 17 Oct 2015, Greg KH wrote: > > On Mon, Sep 28, 2015 at 10:09:11PM +0300, ville.syrj...@linux.intel.com > > wrote: > >> From: Ville Syrjälä > >> > >> commit

[Intel-gfx] [PATCH v2 3/8] drm/i915: Cope with request list state change during error state capture

Since we're not synchronizing the ring request list during error state capture the request list state might change between the time the corresponding error request list was allocated and dimensioned to the time when the ring request list is actually captured into the error state. If this happens

[Intel-gfx] [PATCH v2 7/8] drm/i915: Grab execlist spinlock to avoid post-reset concurrency issues.

Grab execlist lock when cleaning up execlist queues after GPU reset to avoid concurrency problems between the context event interrupt handler and the reset path immediately following a GPU reset. * v2 (Chris Wilson): Do execlist check and use simpler form of spinlock functions. Signed-off-by:

Re: [Intel-gfx] [PATCH 1/3] drm/edid: Fix up clock for CEA/HDMI modes specified via detailed timings

On Fri, Oct 09, 2015 at 01:54:58PM +0300, Jani Nikula wrote: > On Thu, 08 Oct 2015, Daniel Vetter wrote: > > On Thu, Oct 08, 2015 at 12:22:31PM -0400, Adam Jackson wrote: > >> On Thu, 2015-10-08 at 11:43 +0300, ville.syrj...@linux.intel.com wrote: > >> > From: Ville Syrjälä

Re: [Intel-gfx] [PATCH resend v2 3/8] drm/i915: Cope with request list state change during error state capture

On Mon, Oct 19, 2015 at 03:55:48PM +0100, Tomas Elf wrote: > Since we're not synchronizing the ring request list during error state capture > the request list state might change between the time the corresponding error > request list was allocated and dimensioned to the time when the ring request

Re: [Intel-gfx] [PATCH v2 3/8] drm/i915: Cope with request list state change during error state capture

On Mon, Oct 19, 2015 at 03:52:53PM +0100, Tomas Elf wrote: > Since we're not synchronizing the ring request list during error state capture > the request list state might change between the time the corresponding error > request list was allocated and dimensioned to the time when the ring request

Re: [Intel-gfx] [PATCH 4.1, 4.2] drm/i915: Silence DDR DVFS errors on CHV

On Mon, Oct 19, 2015 at 08:13:05AM -0700, Greg KH wrote: > On Mon, Oct 19, 2015 at 11:02:35AM +0300, Jani Nikula wrote: > > On Sat, 17 Oct 2015, Greg KH wrote: > > > On Mon, Sep 28, 2015 at 10:09:11PM +0300, ville.syrj...@linux.intel.com > > > wrote: > > >> From:

Re: [Intel-gfx] [regression] [git pull] drm for 4.3

On Wed, Sep 30, 2015 at 08:56:26AM +0200, Daniel Vetter wrote: > > The warning on boot seems to be gone as of rc3, but I can now trigger this > > pretty easily.. > > http://patchwork.freedesktop.org/patch/60618/ Back from several weeks of travel.. I tried again with rc6, and I'm still

Re: [Intel-gfx] [PATCH v6 14/23] drm/i915: CHV: Pipe level degamma correction

On 10/19/2015 11:54 AM, Daniel Vetter wrote: > On Mon, Oct 19, 2015 at 06:08:52PM +, Smith, Gary K wrote: >> FYI - this shouldn't block the commits, but should be optimized later >> (fairly soon). >> >> I believe the current implementation ends up executing >> while (count <

Re: [Intel-gfx] [PATCH] drm/i915: Consider plane rotation when calculating stride in skl_do_mmio_flip

On Wed, Oct 07, 2015 at 11:01:23AM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > Previously rotation was ignored and wrong stride programmed > into the plane registers resulting in a corrupt image on screen. > > Signed-off-by: Tvrtko Ursulin

Re: [Intel-gfx] [PATCH v6 14/23] drm/i915: CHV: Pipe level degamma correction

On Mon, Oct 19, 2015 at 06:08:52PM +, Smith, Gary K wrote: > FYI - this shouldn't block the commits, but should be optimized later (fairly > soon). > > I believe the current implementation ends up executing > while (count < CHV_DEGAMMA_MAX_VALS) { > //

Re: [Intel-gfx] [PATCH v6 14/23] drm/i915: CHV: Pipe level degamma correction

FYI - this shouldn't block the commits, but should be optimized later (fairly soon). I believe the current implementation ends up executing while (count < CHV_DEGAMMA_MAX_VALS) { // Do lots of caclulation

Re: [Intel-gfx] [PATCH v6 14/23] drm/i915: CHV: Pipe level degamma correction

Unless legacy mode enables it of course. Thanks Gary "Smith, Gary K" wrote: Bear in mind that it will only happen after the property has been set. Initially there will be no clients setting the property - so I think it should be OK. Thanks Gary Daniel Vetter

Re: [Intel-gfx] [regression] [git pull] drm for 4.3

On Mon, Oct 19, 2015 at 04:19:08PM -0400, da...@codemonkey.org.uk wrote: > On Wed, Sep 30, 2015 at 08:56:26AM +0200, Daniel Vetter wrote: > > > > The warning on boot seems to be gone as of rc3, but I can now trigger > this pretty easily.. > > > > http://patchwork.freedesktop.org/patch/60618/

[Intel-gfx] [PATCH] drm/i915/guc: Fix a false alert of memory leak when free LRC

From: Alex Dai There is a memory leak warning message from i915_gem_context_clean when GuC submission is enabled. The reason is that the request (so the LRC associated with it) is freed early than moving the vma list to inactive. When retire a gem object, this patch moves its

[Intel-gfx] [PATCH v6] drm/i915/guc: Add GuC css header parser

From: Alex Dai The size / offset information of all firmware ingredients are now caculated from header. Driver will validate the header and rsa key size. If any component is out of boundary, driver will reject the loading too. v6: Clean up warnings from make docs v5: Tidy up

Re: [Intel-gfx] [PATCH v6 14/23] drm/i915: CHV: Pipe level degamma correction

On Mon, Oct 19, 2015 at 08:39:54PM +, Bish, Jim wrote: > > > On 10/19/2015 11:54 AM, Daniel Vetter wrote: > > On Mon, Oct 19, 2015 at 06:08:52PM +, Smith, Gary K wrote: > >> FYI - this shouldn't block the commits, but should be optimized later > >> (fairly soon). > >> > >> I believe

[Intel-gfx] [PATCH v6] drm-intel-nightly: 2015y-10m-19d-20h-41m-28s UTC integration manifest

From: Matt Roper --- integration-manifest | 24 1 file changed, 24 insertions(+) create mode 100644 integration-manifest diff --git a/integration-manifest b/integration-manifest new file mode 100644 index 000..a726d7c --- /dev/null +++

Re: [Intel-gfx] [PATCH v6 14/23] drm/i915: CHV: Pipe level degamma correction

Daniel? Annie Matheson Intel Corporation Phone: (503) 712-0586 Email: annie.j.mathe...@intel.com From: Smith, Gary K Sent: Monday, October 19, 2015 3:27 PM To: Daniel Vetter Cc: Bish, Jim; Sharma, Shashank; dri-de...@lists.freedesktop.org;

Re: [Intel-gfx] [PATCH v6 14/23] drm/i915: CHV: Pipe level degamma correction

Bear in mind that it will only happen after the property has been set. Initially there will be no clients setting the property - so I think it should be OK. Thanks Gary Daniel Vetter wrote: On Mon, Oct 19, 2015 at 08:39:54PM +, Bish, Jim wrote: > > > On 10/19/2015 11:54

[Intel-gfx] [PATCH] drm/i915: Retry on every aux read.

We have an inconsistency on our code on using intel_dp_dpcd_read_wake with retries and when using drm_dp_dpcd_read helper without retry. Since the retries help in many cases let's be consistent and be on the safe side retrying on every aux read, including i2c ones. So we can kill the

Re: [Intel-gfx] [regression] [git pull] drm for 4.3

On 20 October 2015 at 07:54, Daniel Vetter wrote: > On Mon, Oct 19, 2015 at 04:19:08PM -0400, da...@codemonkey.org.uk wrote: >> On Wed, Sep 30, 2015 at 08:56:26AM +0200, Daniel Vetter wrote: >> >> > > The warning on boot seems to be gone as of rc3, but I can now trigger >> this

Re: [Intel-gfx] [PATCH] igt/kms_addfb_basic: New subtest to check for fb modifier and tiling mode mismatch

On Mon, 19 Oct 2015 11:50:25 +0200 Daniel Vetter wrote: > On Thu, Oct 15, 2015 at 06:10:46PM -0700, Vivek Kasireddy wrote: > > Hi Tvrtko, > > > > On Fri, 9 Oct 2015 09:34:25 +0100 > > Tvrtko Ursulin wrote: > > > > > > > > > > > On 08/10/15

Re: [Intel-gfx] [PATCH v2] drm/i915/hsw: keep gamma and CSC enabled for primary plane disable

On Mon, Oct 19, 2015 at 12:15:41PM +0200, Daniel Vetter wrote: > On Fri, Oct 16, 2015 at 03:53:22PM -0700, Bob Paauwe wrote: > > On Thu, 15 Oct 2015 15:41:30 +0300 > > Ville Syrjälä wrote: > > > > > On Thu, Oct 15, 2015 at 02:31:09PM +0200, Daniel Vetter wrote: > >

Re: [Intel-gfx] [PATCH] drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL-style WM (v4)

Em Qui, 2015-10-15 às 15:42 -0700, Matt Roper escreveu: > Just pull the info out of the state structures rather than staging > it in an additional set of structures.  To make this more > straightforward, we change the signature of several internal WM > functions to take the crtc state as a

Re: [Intel-gfx] [PATCH] igt/kms_rotation_crc: Add a subtest to validate Y-tiled obj + Y fb modifier

Hi Tvrtko, On Mon, 19 Oct 2015 11:20:05 +0100 Tvrtko Ursulin wrote: > > Hi, > > On 17/10/15 03:47, Vivek Kasireddy wrote: > > The main goal of this subtest is to verify whether flipping a > > framebuffer with a Y fb modifier (90/270 degree rotation) and > > an

Re: [Intel-gfx] [PATCH v6 14/23] drm/i915: CHV: Pipe level degamma correction

Sounds like a good suggestion to me, it would be efficient to do so. By the time we discus on this, I would see a possibility of adding one patch on top of the series, with this optimization. Regards Shashank From: Matheson, Annie J Sent: Tuesday, October 20, 2015 5:18 AM To: Smith, Gary K;

[Intel-gfx] [PATCH v3 7/8] drm/i915: Cope with request list state change during error state capture

Since we're not synchronizing the ring request list during error state capture the request list state might change between the time the corresponding error request list was allocated and dimensioned to the time when the ring request list is actually captured into the error state. If this happens

Re: [Intel-gfx] [PATCH 4.1, 4.2] drm/i915: Silence DDR DVFS errors on CHV

On Mon, Oct 19, 2015 at 06:10:39PM +0200, Daniel Vetter wrote: > On Mon, Oct 19, 2015 at 08:13:05AM -0700, Greg KH wrote: > > On Mon, Oct 19, 2015 at 11:02:35AM +0300, Jani Nikula wrote: > > > On Sat, 17 Oct 2015, Greg KH wrote: > > > > On Mon, Sep 28, 2015 at

Re: [Intel-gfx] [PATCH 4.1, 4.2] drm/i915: Silence DDR DVFS errors on CHV

On Mon, Oct 19, 2015 at 08:13:05AM -0700, Greg KH wrote: > On Mon, Oct 19, 2015 at 11:02:35AM +0300, Jani Nikula wrote: > > On Sat, 17 Oct 2015, Greg KH wrote: > > > On Mon, Sep 28, 2015 at 10:09:11PM +0300, ville.syrj...@linux.intel.com > > > wrote: > > >> From: